coreboot April 2017

coreboot@coreboot.org

65 participants
143 discussions

How to flash Coreboot on a Thinkpad T430s
by kitestramuort 14 Apr '17

14 Apr '17

The T430s is supported by coreboot, however there's very little documentation on the flashing procedure itself. I couldn't even identify the BIOS chip on the motherboard. From what I've read the chip is not SOIC8, unlike those on the non-S T430 and X230, therefore the raspberry pi method should not be applicable. Is desoldering the chip the only way to install Coreboot on this machine? Is there a guide/howto somewhere? Thanks

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KGPE-D16: Most severe hang failure sorted out + boot time measures
by Daniel Kulesz 14 Apr '17

14 Apr '17

Hi folks, as reported, the KGPE-D16 was mostly unusable for me in my 2x Opteron 6276 + 128 GB RAM configuration as it simply did not boot reliably - even with serial console debugging disabled completely. After experimenting with various config options and comparing my best "known half-working" config from earlier attempts, I finally found out that the hangs were related to the configuration and not to a specific coreboot version. I attached the configs showing my current "reliable" setup (that survived 10 cold and 10 warm reboots without a single hangup!) and one of the previous "unreliable" setups which often needed several cold boots to successfully boot up once. There are several options which might be reposible for these hangs. Personally, I believe what helps is to completely disable the serial console and not just disable debugging to serial console. As asked for previously, I also took some boot time measures from pressing the power button to "grub beep" in my 128 GB RAM configuration. Here they are: vendor bios, unoptimized with iPXE setup: 59s coreboot, current with the "reliable" config: 73s coreboot, Jan 17 2017, with the "reliable" config: 91s coreboot, current with the "unreliable" config: 131s I assume that further investigation of the root cause could help to locate the real bug (like e.g. the setup of the serial console). Yet, I hope that having a "working-good" config will be useful for people suffering from the same issue as I did. For me, this setup is still far from being what I expected (memory is clocked too low and idle power consumption is 170W instead of 90W), but at least the machine boots up reliably every time now. Cheers, Daniel

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ASUS KGPE-D16 Automated Test Failure [master]
by Raptor Engineering Automated Coreboot Test Stand 14 Apr '17

14 Apr '17

The ASUS KGPE-D16 fails verification for branch master as of commit f13e2501525f0025b03f4b2ee3487999bb0ade2b The following tests failed: BOOT_FAILURE Commits since last successful test: See attached log for details This message was automatically generated from Raptor Engineering's ASUS KGPE-D16 test stand Want to test on your own equipment? Check out https://www.raptorengineering.com/content/REACTS/intro.html Raptor Engineering also offers coreboot consulting services! Please visit https://www.raptorengineering.com for more information Please contact Timothy Pearson at Raptor Engineering <tpearson(a)raptorengineering.com> regarding any issues stemming from this notification

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Re: [coreboot] How to disassembly the coreboot.rom file
by Julius Werner 13 Apr '17

13 Apr '17

coreboot has multiple stages that run one after the other. If you don't have UART output you can't be sure how far coreboot gets before it hangs, so you'll want to check all of them and see which ones contain the addresses you get from your JTAG. Disassemble /build/cbfs/fallback/bootblock.debug, romstage.debug and ramstage.debug to see which one applies. (These binaries get stripped and packed into coreboot.rom by the build process, but it's easier to just disassemble them from the /build directory than to try to pry them out of a finished image again.) On Thu, Apr 13, 2017 at 5:07 AM, Maxim Gusev via coreboot < coreboot(a)coreboot.org> wrote: > Hello, friends > > I have a couple of questions. > > When I run the coreboot on my motherboard it doesn't work. > I have some IPs of instructions which I received by JTAG. > So I want to see the instructions that are plased in the final object file. > > How to disassembly the coreboot.rom file? > > As I know it has the filesystem CBFS. So it is not the object file. > I can to disasembler the object files placed in ./build/* that have the > *.o format > but I don't know in which of them there are corresponding instructions. > > Thanks. > Regards, Maxim > > > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot >

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Re: [coreboot] ThinkPad X201/X230 and COMPEX WLE900VX-7A wifi module
by Marek Behun 13 Apr '17

13 Apr '17

Hello Alexander, > a) you're using WWAN slot and not WLAN (on some models wwan slot is a > full mini-pcie, but on most it's just usb) No, I used the Wifi slot. As I have written, I had to file out the bump so that I could put the full-sized card there. > b) the slot is disabled in nvram - try to use nvramtool. If such a > slot is disabled, the slot is hidden on pcie level, not sure if the > power is cut as well. The slot is not disabled, another Atheros card (half-sized Rivet Networks Killer Wireless-AC 1525) is working. I've just realized that on the compexshop webpage http://www.compexshop.com/product_info.php/cPath/104_105/products_id/452 there is written Attention : Atheros 11ac radio can't be used in PC or laptop, as BIOS do not detects it, as Atheros do not release such driver. Pls read reviews for more details about supported PC boards We found that with our Linux PC the WLE600VX card radio (using miniPCIe to PCIe adapter card) is working well. Installed Ubuntu Vivid Vervet Alpha 2 with WLE600VX already inserted. Wireless detected immediately so the OS installation proceeded with automatically downloading updates. Is it possible that some initialization has to be done in coreboot, something like the src/drivers/intel/wifi does for some Intel cards? Marek

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Re: [coreboot] ifdtool newlayout errors
by Elisenda Cuadros 13 Apr '17

13 Apr '17

Hi Nicola & List, I have the same problem as you with ifdtool & newlayout. I tried a modified and also the original layout with same result ------------------------------ The image has changed in size. The old image is 8388608 bytes. The new image is 16777216 bytes. Copy Descriptor 0 (Flash Descriptor) (4096 bytes) from 00000000+00000000:00000fff ( 4096) to 00000000+00000000:00000fff ( 4096) Copy Descriptor 1 (BIOS) (7340032 bytes) from 00500000+00000000:00bfffff ( 7340032) to 0019b000+00365000:00bfffff ( 10899456) Segmentation fault ------------------------------ Were you able to solve the problem? Best regards, Elisenda On 19/08/16 10:49, Nicola Corna wrote: Hi everyone, I have a Thinkpad X220t with coreboot and I'm trying to replace the 5MB ME firmware with the small (2MB) one, extracted from a Sandy Bridge Chromebook. The small ME blob works but now I want to reclaim the free space by modifying the Intel descriptor, partly following the x220 guide (https://www.coreboot.org/Board:lenovo/x220#Bigger_SPI_ROM). If I extract the layout and modify it from 00000000:00000fff fd 00500000:007fffff bios 00003000:004fffff me 00001000:00002fff gbe 00fff000:00000fff pd 00fff000:00ffffff res1 00fff000:00ffffff res2 00fff000:00ffffff res3 00000000:00ffffff ec to 00000000:00000fff fd 00183000:007fffff bios 00003000:00182fff me 00001000:00002fff gbe 00fff000:00000fff pd 00fff000:00ffffff res1 00fff000:00ffffff res2 00fff000:00ffffff res3 00000000:00ffffff ec ifdtool --newlayout fails with "Region would overlap." (gdb shows me that the overlapping regions are fd and ec). If I remove the overlap exit, ifdtool segfaults with this output: File coreboot.rom is 8388608 bytes Regions would overlap. Regions would overlap. Regions would overlap. Regions would overlap. Regions would overlap. Regions would overlap. Regions would overlap. Regions would overlap. Regions would overlap. Regions would overlap. The image has changed in size. The old image is 8388608 bytes. The new image is 16777216 bytes. Copy Descriptor 0 (Flash Descriptor) (4096 bytes) from 00000000+00000000:00000fff ( 4096) to 00000000+00000000:00000fff ( 4096) Copy Descriptor 1 (BIOS) (3145728 bytes) from 00500000+00000000:007fffff ( 3145728) to 00500000+00000000:007fffff ( 3145728) Copy Descriptor 2 (Intel ME) (5230592 bytes) from 00003000+00000000:004fffff ( 5230592) to 00003000+00000000:004fffff ( 5230592) Copy Descriptor 3 (GbE) (8192 bytes) from 00001000+00000000:00002fff ( 8192) to 00001000+00000000:00002fff ( 8192) Copy Descriptor 5 (Reserved) (4096 bytes) from 00fff000+00000000:00ffffff ( 4096) to 00fff000+00000000:00ffffff ( 4096) [1] 8451 segmentation fault ../util/ifdtool/ifdtool --newlayout layout.txt coreboot.rom If I use an unmodified layout as newlayout the result is the same (overlap + segfault). Suggestions? Thanks Nicola Corna

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Re: [coreboot] How to disassembly the coreboot.rom file
by tturne＠codeaurora.org 13 Apr '17

13 Apr '17

I didn't copy group on original reply, my bad. On 2017-04-13 11:40, tturne(a)codeaurora.org wrote: > On 2017-04-13 05:07, Maxim Gusev via coreboot wrote: >> Hello, friends >> >> I have a couple of questions. >> >> When I run the coreboot on my motherboard it doesn't work. >> >> I have some IPs of instructions which I received by JTAG. >> >> So I want to see the instructions that are plased in the final object >> file. >> >> How to disassembly the coreboot.rom file? > > ./cbfstool --help is your friend > > What you need to do is list the FMAP regions in the device, e.g. > ./cbfstool coreboot.rom layout > You can read a whole FMAP region into its own file and/or extract a > payload directly > > Pay attention to these sub-commands: layout, print, extract and read > > I was able to extract a payload from a recovery image coreboot.rom and > confirm Depthcharge was the payload, using cbfstool to extract the > payload and strings to list the ASCII strings in the file. Once you > have the elf file extracted you can use bin-utils tools directly to > disassemble, etc. > Cheers, > T.mike > >> >> As I know it has the filesystem CBFS. So it is not the object file. >> >> I can to disasembler the object files placed in ./build/* that have >> the *.o format >> >> but I don't know in which of them there are corresponding >> instructions. >> >> Thanks. >> >> Regards, Maxim

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ECC RAM in coreboot-compatible X-series ThinkPads?
by Sam Kuper 13 Apr '17

13 Apr '17

IIUC, conventional ECC RAM requires support from both the motherboard and the CPU. This support is not present in current coreboot-compatible X-series ThinkPads (e.g. X60, X200, X201, X220, X230). There was a discussion on the coreboot mailing list a couple of months ago about RAM modules from "I'M Intelligent Memory". That discussion focused on the fact that they are 16GB in size. https://mail.coreboot.org/pipermail/coreboot/2017-February/083330.html Potentially more interesting, though, is that at least some modules from that company offer *integrated ECC*, which provides ECC in RAM without requiring support from either the CPU or the motherboard: http://www.electronicsbus.com/new-256mb-and-512mb-sdram-x8x16x32-memories-w… As I understand it, none of the modules from that manufacturer are currently able to work in coreboot-compatible X-series ThinkPads, but this did get me wondering: - Are there any other manufacturers offering RAM modules with integrated ECC that *are* compatible with those ThinkPads? - Is there any other way to achieve ECC in coreboot-compatible X-series ThinkPads? (E.g. use I'M Intelligent Memory 16GB ECC RAM sticks but only address the first 8GB of each one?) This is a shot in the dark, I know, but it seemed worth asking :)

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ThinkPad X201/X230 and COMPEX WLE900VX-7A wifi module
by Marek Behun 13 Apr '17

13 Apr '17

Hello, so I have tried to insert the COMPEX WLE900VX-7A wifi module (http://www.compexshop.com/product_info.php/cPath/104_105/products_id/452 ) into the wifi slot of ThinkPad X230 and X201 (since on X230 the wifi slot is for half-sized module only, I had to file out the bump that is on one side istead of the hole for the screw). For some reason this module does not show on lspci on either of this laptops (with coreboot installed). On Lenovo 3000 N200, it does show up. Any idea what is the reason? Is this due to some pins being not powered on the Wifi slots on ThinkPads, or something like that? If it is not possible, I think I am going to create a expresscard-to-minipcie reduction for this reason :D Thanks. MB

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ThinkPad X201 status?
by Marek Behun 13 Apr '17

13 Apr '17

Hello, this week I have been trying coreboot master and coreboot-4.5 on my ThinkPad X201. coreboot-4.5 does not work (display stays dark) coreboot-master boots, is working, but: - when powering off, the system halts (display stays on), the cpu is in some kind of a loop since there is heat coming out from the fan - suspending to ram does not work: the same thing happens as when powering off, I have to manually disable it Is there some commit that is known to be working? Thank you. MB

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coreboot April 2017