coreboot April 2017

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143 discussions

Re: [coreboot] Booting issue --AMD Olive Hill plus mainboard
by ron minnich 24 Apr '17

24 Apr '17

unless you're dead certain you don't need them, include microcode updates. did you hook up a serial port? On Mon, Apr 24, 2017 at 2:44 PM Idwer Vollering <vidwer(a)gmail.com> wrote: > 2017-04-24 21:08 GMT+02:00 Nagabhushan Shastry <bhushansastry(a)gmail.com>: > > Hi, > > > > I am trying to bring up the AMD G series Olive hill plus mainboard with > > coreboot. > > > > These are the options i have enabled in make menuconfig but I am not > able > > to see anything on the screen when i power on the board. > > Could someone please let me know if I am missing something. > > > > • General / Use CMOS for configuration values = enable (CMOS defaults are > > located in your boards directory src/mainboard/OEM/MODEL/cmos.default) > > • General / Include the coreboot .config file into the ROM image > > • General / Compress ramstage with LZMA > > • Mainboard / Mainboard vendor = AMD > > • Mainboard / Mainboard model = Olive Hill plus > > • Mainboard / ROM chip size = 8 MB > > • Chipset / Include CPU microcode in CBFS = Do not include microcode > updates > > (NOTE: you probably want to enable it on some systems) > > • Chipset / Enable Hudson XHCI Controller > > • Chipset / Add xhci firmware > > • (3rdparty/blobs/southbridge/amd/avalon/xhci.bin) XHCI firmware path and > > filename > >  (3rdparty/blobs/southbridge/amd/avalon/PSP/AmdPubKey.bin) AMD public > Key > > • Devices / Run VGA Option ROMs > > • Devices / Add a VGA BIOS image > >  (3rdparty/blobs/northbridge/amd/00730F01/VBIOS.bin) VGA BIOS path and > > filename > >  (1002,9850) VGA device PCI IDs > > These PCI IDs, are they correct? Is the VBIOS, which I don't know > anything about, executed? You need to have a way to see console > output, either using the board's serial port or - presuming the > mainboard boots to linux - through the utility found in util/cbmem/ > > > • Display / Keep VESA framebuffer = disable (disable for text-mode > graphics, > > enable for coreboot vesa framebuffer) > > • Generic Drivers / Serial port on SuperIO > > • Generic Drivers / Support Intel PCI-e WiFi adapters > > • Console / Squelch AP CPUs from early console. > > • Console / Serial port console output > > • Console / Use onboard VGA as primary video device > > • Console / Send console output to a CBMEM buffer > > • Console / Send POST codes to an external device > > • Console / Send POST codes to an IO port > > • System tables / [*] Generate an MP table > > • System tables / [*] Generate a PIRQ table > > • System tables / [*] Generate SMBIOS tables > > • Payload / SeaBIOS version (1.10.2) ---> > > • Payload / Use LZMA compression for payloads > > > > -- > > coreboot mailing list: coreboot(a)coreboot.org > > https://mail.coreboot.org/mailman/listinfo/coreboot > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot

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Re: [coreboot] Booting issue --AMD Olive Hill plus mainboard
by Idwer Vollering 24 Apr '17

24 Apr '17

2017-04-24 21:08 GMT+02:00 Nagabhushan Shastry <bhushansastry(a)gmail.com>: > Hi, > > I am trying to bring up the AMD G series Olive hill plus mainboard with > coreboot. > > These are the options i have enabled in make menuconfig but I am not able > to see anything on the screen when i power on the board. > Could someone please let me know if I am missing something. > > • General / Use CMOS for configuration values = enable (CMOS defaults are > located in your boards directory src/mainboard/OEM/MODEL/cmos.default) > • General / Include the coreboot .config file into the ROM image > • General / Compress ramstage with LZMA > • Mainboard / Mainboard vendor = AMD > • Mainboard / Mainboard model = Olive Hill plus > • Mainboard / ROM chip size = 8 MB > • Chipset / Include CPU microcode in CBFS = Do not include microcode updates > (NOTE: you probably want to enable it on some systems) > • Chipset / Enable Hudson XHCI Controller > • Chipset / Add xhci firmware > • (3rdparty/blobs/southbridge/amd/avalon/xhci.bin) XHCI firmware path and > filename >  (3rdparty/blobs/southbridge/amd/avalon/PSP/AmdPubKey.bin) AMD public Key > • Devices / Run VGA Option ROMs > • Devices / Add a VGA BIOS image >  (3rdparty/blobs/northbridge/amd/00730F01/VBIOS.bin) VGA BIOS path and > filename >  (1002,9850) VGA device PCI IDs These PCI IDs, are they correct? Is the VBIOS, which I don't know anything about, executed? You need to have a way to see console output, either using the board's serial port or - presuming the mainboard boots to linux - through the utility found in util/cbmem/ > • Display / Keep VESA framebuffer = disable (disable for text-mode graphics, > enable for coreboot vesa framebuffer) > • Generic Drivers / Serial port on SuperIO > • Generic Drivers / Support Intel PCI-e WiFi adapters > • Console / Squelch AP CPUs from early console. > • Console / Serial port console output > • Console / Use onboard VGA as primary video device > • Console / Send console output to a CBMEM buffer > • Console / Send POST codes to an external device > • Console / Send POST codes to an IO port > • System tables / [*] Generate an MP table > • System tables / [*] Generate a PIRQ table > • System tables / [*] Generate SMBIOS tables > • Payload / SeaBIOS version (1.10.2) ---> > • Payload / Use LZMA compression for payloads > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot

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Booting issue --AMD Olive Hill plus mainboard
by Nagabhushan Shastry 24 Apr '17

24 Apr '17

Hi, I am trying to bring up the AMD G series Olive hill plus mainboard with coreboot. These are the options i have enabled in make menuconfig but I am not able to see anything on the screen when i power on the board. Could someone please let me know if I am missing something. • General / Use CMOS for configuration values = enable (CMOS defaults are located in your boards directory src/mainboard/OEM/MODEL/cmos.default) • General / Include the coreboot .config file into the ROM image • General / Compress ramstage with LZMA • Mainboard / Mainboard vendor = AMD • Mainboard / Mainboard model = Olive Hill plus • Mainboard / ROM chip size = 8 MB • Chipset / Include CPU microcode in CBFS = Do not include microcode updates (NOTE: you probably want to enable it on some systems) • Chipset / Enable Hudson XHCI Controller • Chipset / Add xhci firmware • (3rdparty/blobs/southbridge/amd/avalon/xhci.bin) XHCI firmware path and filename  (3rdparty/blobs/southbridge/amd/avalon/PSP/AmdPubKey.bin) AMD public Key • Devices / Run VGA Option ROMs • Devices / Add a VGA BIOS image  (3rdparty/blobs/northbridge/amd/00730F01/VBIOS.bin) VGA BIOS path and filename  (1002,9850) VGA device PCI IDs • Display / Keep VESA framebuffer = disable (disable for text-mode graphics, enable for coreboot vesa framebuffer) • Generic Drivers / Serial port on SuperIO • Generic Drivers / Support Intel PCI-e WiFi adapters • Console / Squelch AP CPUs from early console. • Console / Serial port console output • Console / Use onboard VGA as primary video device • Console / Send console output to a CBMEM buffer • Console / Send POST codes to an external device • Console / Send POST codes to an IO port • System tables / [*] Generate an MP table • System tables / [*] Generate a PIRQ table • System tables / [*] Generate SMBIOS tables • Payload / SeaBIOS version (1.10.2) ---> • Payload / Use LZMA compression for payloads

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[Apollo-lake]How to create Apollo-lake IFWI.bin for coreboot coding use
by James_Lee 24 Apr '17

24 Apr '17

Dear all, I bring up Apollo lake +DDR-3L board, use Coreboot + Intel FSP, I have follow Apollolake implementation <https://embedded.communities.intel.com/external-link.jspa?url=https%3A%2F%2 Fwww.coreboot.org%2Fimages%2F2%2F23%2FApollolake_SoC.pdf> this document to do, But I can Not to create IFWI.bin, always have below error message Error 5: [CsmeBinaryGen] Error executing pre-build actions. Error 15: Failed to build. Failed to build! Can give me a correct XML setting file? let me can reference it, thanks. -James

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Re: [coreboot] server board support - Supermicro H8DGi-F ?
by Taiidan＠gmx.com 23 Apr '17

23 Apr '17

On 04/23/2017 02:03 PM, Idwer Vollering wrote: > 2017-04-23 19:55 GMT+02:00 Michael L. Wilson <michael.l.wilson(a)utu.fi>: >> Hello Idwer Vollering, >> >> I came across an old mailing list item concerning the H8SGL Opteron >> motherboards. >> >> https://mail.coreboot.org/pipermail/coreboot/2013-April/075629.html >> >> Is it truly the case that the single socket boards are already supported by >> Coreboot (as well as the C32 Opteron version)? I cannot find any other >> information about these elsewhere. Any information that you might have would >> be extremely appreciated. >> >> -- >> Michael L. Wilson > Some boards are supported, those mentioned here and in the subject > line seem absent. > See https://www.coreboot.org/Supported_Motherboards and > https://github.com/coreboot/coreboot/tree/master/src/mainboard/supermicro > for what is up-to-date. > It wouldn't be very difficult to add support, all you really have to do is change IRQ assignments and HT mapping etc, I myself am working on a port of the H8SCM to the native coreboot code as the AGESA version doesn't have IOMMU support. There are several supermicro boards that are better than the ASUS D8/D16's, as they have dual northbridge (more pci-e lanes), better onboards nics, onboard SR-IOV RAID controller etc and of course they are newer (2014 vs 2010) I wouldn't recommend putting in the work however as they won't support the upcoming OpenBMC like the asus ones although you could maybe replace the onboard BMC BGA chip to get it if the pinouts are the same for both. The best G34 board period is the H8QG4-LN4F.

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Re: [coreboot] server board support - Supermicro H8DGi-F ?
by Michael L. Wilson 23 Apr '17

23 Apr '17

Many thanks! On 04/23/2017 09:03 PM, Idwer Vollering wrote: > 2017-04-23 19:55 GMT+02:00 Michael L. Wilson <michael.l.wilson(a)utu.fi>: >> Hello Idwer Vollering, >> >> I came across an old mailing list item concerning the H8SGL Opteron >> motherboards. >> >> https://mail.coreboot.org/pipermail/coreboot/2013-April/075629.html >> >> Is it truly the case that the single socket boards are already supported by >> Coreboot (as well as the C32 Opteron version)? I cannot find any other >> information about these elsewhere. Any information that you might have would >> be extremely appreciated. >> >> -- >> Michael L. Wilson > > Some boards are supported, those mentioned here and in the subject > line seem absent. > See https://www.coreboot.org/Supported_Motherboards and > https://github.com/coreboot/coreboot/tree/master/src/mainboard/supermicro > for what is up-to-date. >

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Re: [coreboot] server board support - Supermicro H8DGi-F ?
by Idwer Vollering 23 Apr '17

23 Apr '17

2017-04-23 19:55 GMT+02:00 Michael L. Wilson <michael.l.wilson(a)utu.fi>: > Hello Idwer Vollering, > > I came across an old mailing list item concerning the H8SGL Opteron > motherboards. > > https://mail.coreboot.org/pipermail/coreboot/2013-April/075629.html > > Is it truly the case that the single socket boards are already supported by > Coreboot (as well as the C32 Opteron version)? I cannot find any other > information about these elsewhere. Any information that you might have would > be extremely appreciated. > > -- > Michael L. Wilson Some boards are supported, those mentioned here and in the subject line seem absent. See https://www.coreboot.org/Supported_Motherboards and https://github.com/coreboot/coreboot/tree/master/src/mainboard/supermicro for what is up-to-date.

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Resume problems on Lenovo X60t
by Paul Menzel 23 Apr '17

23 Apr '17

Dear coreboot folks, With Linux 4.11-rcX sometimes the Lenovo X60t doesn’t correctly resume anymore. I still have to do some more tests, but I believe I am unable to reproduce this issue with Linux 4.10.8. But as I also do not know how to reproduce it, despite doing suspend and resuming, and see how it goes, I cannot know for sure. With Linux 4.11-rcX, I’d say the issue happens one out of ten or 15 times. ``` 12.951: [ 350.898287] BUG: unable to handle kernel paging request at f8281008 12.951: [ 350.898346] IP: gen2_write32+0x62/0x130 [i915] 12.951: [ 350.898347] *pde = 34c88067 12.951: [ 350.898349] *pte = 00000000 12.951: [ 350.898349] 12.951: [ 350.898352] Oops: 0002 [#1] SMP 12.951: [ 350.898353] Modules linked in: joydev(E) wacom_w8001(E) serport(E) cpufreq_powersave(E) cpufreq_conservative(E) cpufreq_userspace(E) iTCO_wdt(E) iTCO_vendor_support(E) acpi_cpufreq(E) coretemp(E) arc4 (E) kvm_intel(E) lpc_ich(E) kvm(E) mfd_core(E) irqbypass(E) iwl3945(E) iwlegacy(E) i915(E) evdev(E) snd_hda_codec_analog(E) snd_hda_codec_generic(E) snd_pcsp(E) pcmcia(E) serio_raw(E) mac80211(E) rng_core(E) snd _hda_intel(E) yenta_socket(E) pcmcia_rsrc(E) drm_kms_helper(E) pcmcia_core(E) snd_hda_codec(E) snd_hda_core(E) snd_hwdep(E) thinkpad_acpi(E) snd_pcm(E) drm(E) cfg80211(E) battery(E) nvram(E) i2c_algo_bit(E) snd_ timer(E) fb_sys_fops(E) syscopyarea(E) sysfillrect(E) snd(E) rfkill(E) sysimgblt(E) soundcore(E) video(E) ac(E) button(E) shpchp(E) tpm_tis(E) tpm_tis_core(E) tpm(E) fuse(E) parport_pc(E) 12.951: [ 350.898397] ppdev(E) lp(E) parport(E) autofs4(E) ext4(E) crc16(E) jbd2(E) fscrypto(E) mbcache(E) ecb(E) cbc(E) algif_skcipher(E) af_alg(E) dm_crypt(E) dm_mod(E) sg(E) sr_mod(E) sd_mod(E) cdrom(E) ata _generic(E) sdhci_pci(E) psmouse(E) sdhci(E) uhci_hcd(E) e1000e(E) ata_piix(E) ahci(E) ehci_pci(E) firewire_ohci(E) libahci(E) i2c_i801(E) libata(E) ehci_hcd(E) ptp(E) mmc_core(E) firewire_core(E) crc_itu_t(E) s csi_mod(E) usbcore(E) pps_core(E) thermal(E) 12.951: [ 350.898429] CPU: 1 PID: 1113 Comm: kworker/u4:32 Tainted: G E 4.11.0-rc7 #23 12.951: [ 350.898431] Hardware name: LENOVO 636338U/636338U, BIOS CBET4000 4.5-1596-gccdb801 04/19/2017 12.951: [ 350.898436] Workqueue: events_unbound async_run_entry_fn 12.951: [ 350.898438] task: f2588480 task.stack: f258c000 12.951: [ 350.898483] EIP: gen2_write32+0x62/0x130 [i915] 12.951: [ 350.898484] EFLAGS: 00210282 CPU: 1 12.951: [ 350.898486] EAX: f8281008 EBX: f8d80eb0 ECX: 00000001 EDX: f8180000 12.951: [ 350.898487] ESI: f658403c EDI: 00000001 EBP: f258de44 ESP: f258de14 12.951: [ 350.898488] DS: 007b ES: 007b FS: 00d8 GS: 00e0 SS: 0068 12.951: [ 350.898490] CR0: 80050033 CR2: f8281008 CR3: 17589000 CR4: 000006d0 12.951: [ 350.898492] Call Trace: 12.951: [ 350.898537] ? i915_gem_restore_gtt_mappings+0x1ca/0x290 [i915] 12.951: [ 350.898581] ? gen9_decoupled_read64+0x270/0x270 [i915] 12.951: [ 350.898622] ? gen6_ggtt_invalidate+0x25/0x30 [i915] 12.951: [ 350.898665] ? i915_gem_resume+0x2d/0x80 [i915] 12.951: [ 350.898701] ? i915_drm_resume+0x38/0x180 [i915] 12.952: [ 350.898705] ? pci_pm_resume+0x4b/0xc0 12.952: [ 350.898709] ? dpm_run_callback+0x53/0x150 12.952: [ 350.898713] ? wait_for_completion+0x2a/0x140 12.952: [ 350.898716] ? pci_pm_thaw+0x90/0x90 12.952: [ 350.898718] ? device_resume+0x87/0x170 12.952: [ 350.898720] ? async_resume+0x1e/0x50 12.952: [ 350.898722] ? async_run_entry_fn+0x35/0x190 12.952: [ 350.898726] ? process_one_work+0x15f/0x3a0 12.952: [ 350.898729] ? worker_thread+0x39/0x470 12.952: [ 350.898732] ? kthread+0xdb/0x110 12.952: [ 350.898734] ? process_one_work+0x3a0/0x3a0 12.952: [ 350.898736] ? kthread_create_on_node+0x30/0x30 12.952: [ 350.898739] ? ret_from_fork+0x1c/0x28 12.952: [ 350.898741] Code: d4 a6 e1 f8 bb 02 00 00 00 89 4c 24 08 89 5c 24 04 c7 04 24 49 d1 e0 f8 e8 bc 92 c8 ff 8b 97 d4 03 00 00 8b 45 e8 8b 7d e4 01 d0 <89> 38 83 c4 24 5b 5e 5f 5d c3 8d 74 26 00 64 8b 15 00 31 57 d7 12.952: [ 350.898813] EIP: gen2_write32+0x62/0x130 [i915] SS:ESP: 0068:f258de14 12.952: [ 350.898814] CR2: 00000000f8281008 12.952: [ 350.898817] ---[ end trace 478b15034b0b3e6a ]--- ``` Ticket #100739 in the Freedesktop.org Bugzilla [1] tracks this issue. Chris Wilson replied already. > The stacktrace is mostly garbage. A register mmio goes wrong. One of > the suggestions is that the ioremap of the PCI bar is invalid upon > resume. coreboot has the TPM patches applied, and is built with native graphics initialization. Has anybody else experienced any issues on the Lenovo X60t? In #coreboot(a)irc.freenode.net it was mentioned that there might be low memory corruptions on the Intel 945 devices. I’d welcome help also from “normal users” to reproduce this issue. Kind regards, Paul [1] https://bugs.freedesktop.org/show_bug.cgi?id=100739

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chromeos-firmwareupdate
by tturne＠codeaurora.org 21 Apr '17

21 Apr '17

Folks, If this query more correctly belongs on ChromiumOS list, I will re-post. This utility appears to be the safe/practical way to interact with the coreboot firmware on an actual chromebook device. The factory image for kevin has this located at /usr/sbin/chromeos-firmwareupdate. I have locally built three "flavors" of kevin: "normal" dev and test. I can boot all three of these images in Developer-Mode and none of them have /usr/sbin/chromeos-firmwareupdate present. Q.1) How do I get chromeos-firmwareupdate populated on a local build? Do I have to generate a recovery image from my test image? Cheers, T.mike

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Re: [coreboot] Website pages are unreadable in a window or with a sidebar opened
by Zaolin 21 Apr '17

21 Apr '17

You can easily fix it for yourself by pushing a new change to gerrit. Have fun! git clone ssh://your-username@review.coreboot.org:29418/homepage https://www.coreboot.org/Git On 04/21/2017 01:03 PM, Cordylus Interneter wrote: > Can be fixed by using max-width instead of max-device-width in the style.css file. > >

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coreboot April 2017