coreboot April 2017

coreboot@coreboot.org

65 participants
143 discussions

Warm reset support in Coreboot
by Sibi.Rajasekaran＠dell.com 28 Apr '17

28 Apr '17

Hi, Is there a way to do warm reset in Rangeley based systems in Coreboot? I tried writing 0x6 to the 0xcf9 interface, but it was a cold reset rather than a warm reset. Thanks, Sibi

1 0

Re: [coreboot] Intel ME The Way of the Static Analysis
by Zoran Stojsavljevic 28 Apr '17

28 Apr '17

> It's the year of minix on the desktop! and the server! and the laptop! One only knows... You, Google people, you are too fast. Way too fast. :-( I would be (being you, Google) more patient.. Much more, since I see attempts from Google Coreboot leaders to cringe to INTEL. I would advise Google NOT to do so! Just to be plain, strip to the bones, brutal Impartial. ;-) Thank you, Zoran On Thu, Apr 27, 2017 at 1:16 AM, ron minnich <rminnich(a)gmail.com> wrote: > It's the year of minix on the desktop! and the server! and the laptop! > > > > On Wed, Apr 26, 2017 at 1:58 PM Patrick Georgi via coreboot < > coreboot(a)coreboot.org> wrote: > >> Fun tidbit: The ME is running MINIX3 (confirmed by a file in the >> Google cache: http://webcache.googleusercontent.com/search? >> q=cache:tCcU0NRwTnQJ:ftp://ftp.supermicro.com/CDR-X11-UP_ >> 1.10_for_Intel_X11_UP_platform/Intel/ME/Other_ >> Licenses/Minix3_License.txt+&cd=1&hl=de&ct=clnk&gl=de&lr= >> lang_de%7Clang_en) >> >> 2017-04-26 22:47 GMT+02:00 Youness Alaoui <kakaroto(a)kakaroto.homelinux. >> net>: >> > Thanks for the links. >> > This is the article that I had seen : >> > http://blog.ptsecurity.com/2017/04/intel-me-way-of-static-analysis.html >> > >> > >> > On Tue, Apr 25, 2017 at 10:38 AM, Shawn <citypw(a)gmail.com> wrote: >> >> >> >> slide: >> >> https://www.troopers.de/downloads/troopers17/TR17_ME11_Static.pdf >> >> >> >> video: >> >> https://www.youtube.com/watch?v=2_aokrfcoUk >> >> >> >> -- >> >> coreboot mailing list: coreboot(a)coreboot.org >> >> https://mail.coreboot.org/mailman/listinfo/coreboot >> > >> > >> > >> > -- >> > coreboot mailing list: coreboot(a)coreboot.org >> > https://mail.coreboot.org/mailman/listinfo/coreboot >> >> >> >> -- >> Google Germany GmbH, ABC-Str. 19, 20354 Hamburg >> Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft: >> Hamburg >> Geschäftsführer: Matthew Scott Sucherman, Paul Terence Manicle >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> https://mail.coreboot.org/mailman/listinfo/coreboot > > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot >

1 0

Re: [coreboot] [RFH] Please test current code on your devices before coreboot 4.6 release
by Patrick Rudolph 28 Apr '17

28 Apr '17

Hi Persmule, I did some tests on thinkpad T430. I disabled SeaBios CONFIG_TCGBIOS and was able to communicate with TPM in GNU Linux, did a self test and took ownership. It doesn't report as temporarily deactivated any more. It looks like SeaBIOS' TPM driver is broken, possible related to this fix: https://patchwork.kernel.org/patch/9191647/ Regards, Patrick On Thu, 27 Apr 2017 21:53:07 +0800 persmule <persmule(a)gmail.com> wrote: > Hi Paul, > > Today I found that on my thinkpad x230 > (https://review.coreboot.org/cgit/board-status.git/tree/lenovo/x230/4.5-1640…), > TPM remains in deactivated state after boot, and there is no config > menu item in seabios' menu, while my t420's > (https://review.coreboot.org/cgit/board-status.git/tree/lenovo/t420/4.5-1640…) > TPM works fine. Their TPM Kconfig seem same. > > Besides, I have also tried an OEM bios with ME cleansed just like my > coreboot build on my x230, and TPM works fine on it. > > It seems TPM init and activate code breaks a little on x230. > > Persmule > > 在 2017年04月14日 07:48, Paul Menzel via coreboot 写道: > > Dear coreboot folks, > > > > > > coreboot 4.6 is planned to be released on Monday, so please take ten > > minutes, and build the current master branch for your board, flash > > it, boot it, and upload the status to the board status repository. > > > > And if you notice a regression, please send a message to the list or > > create an issue in the issue tracker [1]. > > > > Currently it’s unknown if on Lenovo laptops [2], the TPM is still > > works, when TPM support is selected in Kconfig. Please note, that > > there were two regressions in the Linux Kernel, so that you should > > not use Linux 4.9 or the Linux 4.11 release candidates for testing. > > > > If somebody tested the different QEMU targets that’d be great too. > > > > > > Thanks, > > > > Paul > > > > > > [1] https://ticket.coreboot.org/ > > [2] https://review.coreboot.org/10411 > > > > > > >

2 1

coreboot community meeting minutes for April 27th, 2017
by Martin Roth 27 Apr '17

27 Apr '17

These are the minutes from today's coreboot community meeting. Information about the next meeting is at the bottom. ####################################################################### Thursday, April 27, 2017 General coreboot news & discussions * 4.6 release delayed? - It will happen this weekend. - Is there anything that still needs to go in? - Maybe TPM workarounds if they're ready by the weekend. - How do we improve communication in case of delays? - There wasn't really any delay. We always have a 2 week window planned for the release - 4/15 - 4/30 and 10/15 - 10/31. Maybe that should have been communicated better, but always, we need better documentation. Next time Martin shouldn't be so optimistic about the release dates. - Martin will document the release process so that this isn't dependent on him, and so that there's better understanding in the community of the process. * Linux coreboot CBMEM console driver upstreamed: https://git.kernel.org/pub/scm/linux/kernel/git/gregkht/char-misc.git/commi… - Jwerner told us he not against renaming of the kernel config option - It woud be nice to further integrate that with systemd-analyze * Conferences - Sign up. * The TPM issue has been found - tcgbios impl of SeaBIOS is broken since 1.9.X - Further investigation needs to happen. * Issue/bug tracker discussion started: https://mail.coreboot.org/pipermail/coreboot/2017-April/084069.html - Please participate * How to get more active corporate developers to participate in the CCM? - Directly contact corporate developers. - Would a different time be better for corporate developers? - Note that we had people from Google, Facebook, Intel, and SecuNet in the meeting. * License for coreboot documentation: - We've selected CC-BY 4.0 - We need to make sure things are licensed that way. - We should add a license file to the top of the coreboot documentation tree and include it in the generated HTML. - GPL code in the documentation needs to be small enough that it's covered by fair-use - a few lines copied in is fine, large chunks would be better referenced as links. - When linking to files, please use archive.org - https://web.archive.org/web/20080725184640/coreboot.org * Philipp would like some help working on the website. - Ask for developers on the mailing list? Infrastructure Issues & News * Build servers were down over the weekend due to a router failure. * Grumpybuilder will be brought back online shortly. ################################################################## Next meeting is Thursday, May 11, 2017 Check the coreboot calendar for the time in your timezone https://www.coreboot.org/calendar.html Join using the bluejeans web app or the phone bridge: https://bluejeans.com/616384323 Phone bridge call in numbers: https://www.bluejeans.com/numbers Meeting ID: 616384323 Current agenda & history: https://coreboot-meeting.pads.ccc.de/CommunityMeetingTopics

1 0

BIOS region alignment on ivybridge platforms.
by persmule 27 Apr '17

27 Apr '17

Hi Nicola Corna and Marek Behun, I have reported that a coreboot image with a cleansed and truncated ME region may cause the first boot costing more than 5 minutes (https://mail.coreboot.org/pipermail/coreboot/2017-April/084004.html). Now I confirm that in order to prevent this, the bios region should be aligned to 64KiB (0x10000) on ivybridges. Sandybridges do not have such limitation. Persmule

1 0

[RFH] Please test current code on your devices before coreboot 4.6 release
by Paul Menzel 27 Apr '17

27 Apr '17

Dear coreboot folks, coreboot 4.6 is planned to be released on Monday, so please take ten minutes, and build the current master branch for your board, flash it, boot it, and upload the status to the board status repository. And if you notice a regression, please send a message to the list or create an issue in the issue tracker [1]. Currently it’s unknown if on Lenovo laptops [2], the TPM is still works, when TPM support is selected in Kconfig. Please note, that there were two regressions in the Linux Kernel, so that you should not use Linux 4.9 or the Linux 4.11 release candidates for testing. If somebody tested the different QEMU targets that’d be great too. Thanks, Paul [1] https://ticket.coreboot.org/ [2] https://review.coreboot.org/10411

3 6

ASUS KGPE-D16 Automated Test Failure [master]
by Raptor Engineering Automated Coreboot Test Stand 27 Apr '17

27 Apr '17

The ASUS KGPE-D16 fails verification for branch master as of commit a2b7bd859a313db85632dd0d6d6e467c4a4f995d The following tests failed: BOOT_FAILURE Commits since last successful test: a2b7bd8 i82801gx: Enable PCI-to-PCI bridge fb2f667 nb/amd/amdk8: Link raminit_f.c c0f7a1b google/fizz: Configure HDMI HPD to use native function e8365aa google/fizz: Enable SATA on port 1 See attached log for details This message was automatically generated from Raptor Engineering's ASUS KGPE-D16 test stand Want to test on your own equipment? Check out https://www.raptorengineering.com/content/REACTS/intro.html Raptor Engineering also offers coreboot consulting services! Please visit https://www.raptorengineering.com for more information Please contact Timothy Pearson at Raptor Engineering <tpearson(a)raptorengineering.com> regarding any issues stemming from this notification

1 0

Re: [coreboot] Booting issue --AMD Olive Hill plus mainboard
by Haleigh Novak 27 Apr '17

27 Apr '17

Yes, that is correct; I actually struggled with this sort of problem for a while, on my system the issue was that it would get past coreboot to stop within SeaBIOS execution. Does your system have usb ports? If it does, the usb enumeration happens within coreboot, so a test might be to see what happens if you plug a usb keyboard into the system before starting it. If the lights on the keyboard blink after you start your machine then you are at least getting part way into coreboot. HN From: Nagabhushan Shastry <bhushansastry(a)gmail.com> Sent: Tuesday, April 25, 2017 11:22 AM To: Haleigh Novak; ron minnich Cc: Idwer Vollering; coreboot Subject: Re: [coreboot] Booting issue --AMD Olive Hill plus mainboard Hi, Thanks for the steps, I appreciate it. If I understand correctly I would be able to use this tool when Linux boots with coreboot. But the issue I have is, coreboot not coming up on the board rather I am not sure if it's coming up because I don't see anything on the screen and there is no serial port on the board(except the cpu fan running). Any insight/suggestions would be appreciated. On Tue, Apr 25, 2017, 10:53 PM Haleigh Novak <haleigh(a)edt.com> wrote: Hello , cbmem is a utility located in .../coreboot/util/cbmem. You will have to fully boot into linux to use this coreboot utility. You will also have to have the ability to re-flash your coreboot rom because there are some coreboot configuration changes. What I do to install and run is as follows: (Install) 1) Mount your coreboot source folder to the running system you wish to use the cbmem utility on. 2) Navigate to .../coreboot/util/cbmem folder. 3) Type "$ make install" into your terminal. (cbmem should install on the system in the /usr/local/sbin folder.) (Use - coreboot setup; requires a re-flash of your coreboot rom.) 1) In your coreboot folder run "$ make menuconfig". 2) Under the console tab: (explanations are above the configuration line and //[commented].) //[Enable console output (below) by highlighting and typing 'y'.] [*] Send console output to a CBMEM buffer //[I had to increase the size for debugging (below).] (0x40000) Room allocated for console output in CBMEM //[Set the default level to SPEW (everything) if it is not set like that already.] Default console log level (8: SPEW) ---> With those settings you should be able to successfully run the cbmem utility and get all the output you could need. If you wish to add debug statements anywhere you can do that as well, though it will require a re-flash of your coreboot rom again. All you need to do is add the following replacing <...> as desired anywhere in the coreboot code and it will be displayed in the cbmem output. "printk(BIOS_INFO, "<statement> <variable print> <statement>.\n", <variable>);" (Use - Run cbmem utility, you will need to be root for this.) 1) "cbmem -c" -or- "/usr/local/sbin/cbmem -c" HN From: coreboot <coreboot-bounces(a)coreboot.org> on behalf of Nagabhushan Shastry <bhushansastry(a)gmail.com> Sent: Tuesday, April 25, 2017 9:41 AM To: ron minnich Cc: Idwer Vollering; coreboot Subject: Re: [coreboot] Booting issue --AMD Olive Hill plus mainboard I included the microcode updates but no luck. The PCI IDs seem to be correct for Mullins [Radeon R3 Graphics] (http://pci-ids.ucw.cz/read/PC/1002). There is no serial port in the Olive Hill Plus board. What are my options? Also how do i use this tool in util/cbmem/ ? I am using the default SeaBios as the payload. On Tue, Apr 25, 2017 at 3:15 AM, ron minnich <rminnich(a)gmail.com> wrote: unless you're dead certain you don't need them, include microcode updates. did you hook up a serial port? On Mon, Apr 24, 2017 at 2:44 PM Idwer Vollering <vidwer(a)gmail.com> wrote: 2017-04-24 21:08 GMT+02:00 Nagabhushan Shastry <bhushansastry(a)gmail.com>: > Hi, > > I am trying to bring up the AMD G series Olive hill plus mainboard with > coreboot. > > These are the options i have enabled in make menuconfig but I am not able > to see anything on the screen when i power on the board. > Could someone please let me know if I am missing something. > > • General / Use CMOS for configuration values = enable (CMOS defaults are > located in your boards directory src/mainboard/OEM/MODEL/cmos.default) > • General / Include the coreboot .config file into the ROM image > • General / Compress ramstage with LZMA > • Mainboard / Mainboard vendor = AMD > • Mainboard / Mainboard model = Olive Hill plus > • Mainboard / ROM chip size = 8 MB > • Chipset / Include CPU microcode in CBFS = Do not include microcode updates > (NOTE: you probably want to enable it on some systems) > • Chipset / Enable Hudson XHCI Controller > • Chipset / Add xhci firmware > • (3rdparty/blobs/southbridge/amd/avalon/xhci.bin) XHCI firmware path and > filename >  (3rdparty/blobs/southbridge/amd/avalon/PSP/AmdPubKey.bin) AMD public Key > • Devices / Run VGA Option ROMs > • Devices / Add a VGA BIOS image >  (3rdparty/blobs/northbridge/amd/00730F01/VBIOS.bin) VGA BIOS path and > filename >  (1002,9850) VGA device PCI IDs These PCI IDs, are they correct? Is the VBIOS, which I don't know anything about, executed? You need to have a way to see console output, either using the board's serial port or - presuming the mainboard boots to linux - through the utility found in util/cbmem/ > • Display / Keep VESA framebuffer = disable (disable for text-mode graphics, > enable for coreboot vesa framebuffer) > • Generic Drivers / Serial port on SuperIO > • Generic Drivers / Support Intel PCI-e WiFi adapters > • Console / Squelch AP CPUs from early console. > • Console / Serial port console output > • Console / Use onboard VGA as primary video device > • Console / Send console output to a CBMEM buffer > • Console / Send POST codes to an external device > • Console / Send POST codes to an IO port > • System tables / [*] Generate an MP table > • System tables / [*] Generate a PIRQ table > • System tables / [*] Generate SMBIOS tables > • Payload / SeaBIOS version (1.10.2) ---> > • Payload / Use LZMA compression for payloads > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot(a)coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot(a)coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot

3 3

Coreboot on the Supermicro H8SCM-F
by PeerCorps Trust Fund 27 Apr '17

27 Apr '17

Greetings All, I recently came across the following listing concerning Coreboot on the Supermicro H8SCM-F. https://www.coreboot.org/Board:supermicro/h8scm You will note that the last update was in January of 2014. I also noticed a note in the page concerning "OS Booting - Proprietary BIOS". Is there anyone who can elaborate as to what this means? -- Michael

5 7

[RFC] What to do with the issue/bug tracker and bugs?
by Paul Menzel 27 Apr '17

27 Apr '17

Dear coreboot folks, In the past an issue/bug tracker was requested, and Lynxis set it up [1] and maintains it. Currently, there are 109 issue, where 78 of them are open. In the last coreboot community meeting, it was discussed, if that needs to and could be improved, and it was decided to start a discussion on the mailing list. The main question to the developers is, if a issue/bug tracker is still wanted, and, if yes, what prevents you from using it more? Unawareness? Bad usability? One issue already pointed out is, that the issue/bug tracker should be better integrated with Gerrit [2]. The next question is, how open bugs could be fixed? One proposal is, that the “subsystem” maintainers should be responsible for that, at least that the report is looked at and responded to. Thanks, Paul [1] https://ticket.coreboot.org/issues/ [2] http://review.coreboot.org/

2 1

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot April 2017