coreboot April 2017

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Website pages are unreadable in a window or with a sidebar opened
by Cordylus Interneter 21 Apr '17

21 Apr '17

Can be fixed by using max-width instead of max-device-width in the style.css file.

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Some weird phenomina related to suspension on my x230 with coreboot and cleansed ME.
by Persmule 20 Apr '17

20 Apr '17

Hi Nicola Corna, Recently I have observed some weird phenomina related to suspension on my x230 with coreboot and ME cleansed with latest me_cleaner: 1. If its first boot after flash is done on a powered expansion dock, it has a high probability to fail to light the screen during recovery from suspension. 2. If its first boot after flash is done with battery power, the screen will be lit during recovery if usb3 ports has never been used before suspension, otherwise it 100% fails. 3. If its first boot after flash is done with a power supplier directly attached, the recovery from suspension can always light the screen. Such "settings" are completely determined with how the first boot after flash gets powered, and are memorized across power cycles, but unrelated to where later boot is done, nor whether expansion docks are used after the first boot is DONE. I guess it may be related to the MRC cache. Persmule

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ASUS KGPE-D16 Automated Test Failure [master]
by Raptor Engineering Automated Coreboot Test Stand 19 Apr '17

19 Apr '17

The ASUS KGPE-D16 fails verification for branch master as of commit e0a60383b2a8e42f54b6e8a650236d44ef6ff58c The following tests failed: BOOT_FAILURE Commits since last successful test: e0a6038 soc/intel/quark: Move include of reg_access.h See attached log for details This message was automatically generated from Raptor Engineering's ASUS KGPE-D16 test stand Want to test on your own equipment? Check out https://www.raptorengineering.com/content/REACTS/intro.html Raptor Engineering also offers coreboot consulting services! Please visit https://www.raptorengineering.com for more information Please contact Timothy Pearson at Raptor Engineering <tpearson(a)raptorengineering.com> regarding any issues stemming from this notification

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Can't build cb+grub2
by Philipp Stanner 19 Apr '17

19 Apr '17

hi, I can build cb+FILO and cb+seaBIOS, but I can't build it with grub (what would be my favorite payload as I don't need bios calls and don't want to flash an entire kernel). I'll attach the build-protocol. Any ideas what the problem is? Philipp

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Re: [coreboot] ThinkPad X230 with working truncated ME and 11 MB space for payload
by Patrick Rudolph 18 Apr '17

18 Apr '17

On Tue, 18 Apr 2017 16:08:09 +0200 Marek Behun <kabel(a)blackhole.sk> wrote: > > I would try the following to narrow it down: Run the memory training > > with the original ME firmware; keep the MRC cache intact while > > switching to the truncated ME firmware; boot. If it doesn't work > > with the cached values, something around the memory clock might be > > off. If you have de- bug access, you could also directly compare > > the training results from a boot with the original ME firmware vs. > > the modded firmware. If not you can still compare the results from > > MRC-cache dumps. But you'd have to decode them first... > > So I tried to put mrc.cache generated with ME into CBFS, but after > reboot, mrc cache was regenerated. I investigated, and found out: > 1) in mrc.cache with ME, the data begins 4 bytes sooner than in > mrc.cache without ME. This could be the reason why mrc.cache was > regenerated: the one that was found there (generated by coreboot > with ME) was invalid for coreboot without ME? Looks like you corrupted the mrc.cache. Every entry is protected by CRC32. If the first few bytes (mobile) are zero, there's something very wrong, as this is a constant value. The other timings are fine and may vary a little bit, due to noise while training the memory modules. > 2) there are different timings in the cache generated without ME. > I have written an utility to print the data stored there. I am > attaching those two together with a diff. > > I am going to try to somehow change the mrc.cache generated by > coreboot with ME so that coreboot without ME accepts it as valid and > does not regenerate. > > Marek

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ThinkPad X230 with working truncated ME and 11 MB space for payload
by Marek Behun 18 Apr '17

18 Apr '17

I have just now managed to flash my X230 with ME truncated to 828 KiB. I used an older version of me_cleaner (commit d1abbca2). This is because the current version of me_cleaner (which truncates ME to 96 KiB) does not work for me (X230 won't boot). The currently active modules in my ME are (listed with unhuffme): BUP CLS ClsPriv FTCS HOSTCOMM KERNEL POLICY ROMP RSA SESSMGR TDT UPDATE Note that originally ME contained all this modules: admin_cm BOP BUP CLS ClsPriv CONF_STACK eac FTCS HOSTCOMM ICC JOM KERNEL krb LOCL_GER MPC NET_SERVICES NET_STACK NFC Pavp PLDM POLICY ROMP RSA sal secio SESSMGR TDT tls UPDATE utilities WCOD_PUMA wlan So the remove modules are: admin_cm BUP CONF_STACK eac ICC JOM krb LOCL_GER MPC NET_SERVICES NET_STACK NFC Pavp PLDM sal secio tls utilities WCOD_PUMA wlan I do not know what all can the modules that I left there do, but my e1000e is working. The current layout of the flash is: 00000000:00000fff fd 000d2000:00bfffff bios 00003000:000d1fff me 00001000:00002fff gbe This left me with 10.85 MiB for the payload. I am attaching my current descriptor.bin and me.bin, if someone wants to try. Marek

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ASUS KGPE-D16 Automated Test Failure [master]
by Raptor Engineering Automated Coreboot Test Stand 17 Apr '17

17 Apr '17

The ASUS KGPE-D16 fails verification for branch master as of commit 79a27ac8b810e15509ec5656fa4b44b906f09385 The following tests failed: BOOT_FAILURE Commits since last successful test: 79a27ac mb/lenovo/t60: Remove PCI reset code from romstage aeb6101 arch/x86/acpi: Allow "transparent" ACPI device names See attached log for details This message was automatically generated from Raptor Engineering's ASUS KGPE-D16 test stand Want to test on your own equipment? Check out https://www.raptorengineering.com/content/REACTS/intro.html Raptor Engineering also offers coreboot consulting services! Please visit https://www.raptorengineering.com for more information Please contact Timothy Pearson at Raptor Engineering <tpearson(a)raptorengineering.com> regarding any issues stemming from this notification

2 1

Trouble initializing gfx on X200(s)
by Daniel Kulesz 17 Apr '17

17 Apr '17

Hi folks, using the latest coreboot master, I tried several combinations and various config options but I did not succeed to initialize gfx on a X200s so that typical graphical boots work such as: - Ubuntu CD Installer Splashscreen - Windows 7 Installer - Windows 10 Installer - ... I tried with both native gfx init and the vga blob using various resolutions, fb options etc. but no success so far. :/ Of course, graphics initialization works fine in Linux. One thing I noticed: When using the vga blob, Seabios gives only a blinking cursor while GRUB works fine. When loading Seabios as a payload from GRUB (was hard to get that done!), the blinking cursor issue does not occur. However, the above mentioned operating system installers still fail to boot Any ideas? Or did someone ever get one of those graphical things booted on a X200 with Coreboot? Cheers, Daniel

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Re: [coreboot] KGPE-D16 BMC Port Offer (was: Fund a TALOS Secure Workstation as coreboot build system)
by Timothy Pearson 17 Apr '17

17 Apr '17

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 On 01/19/2017 11:36 AM, Martin Roth wrote: > Hey Merlin, > I was taking and keeping track of the pledges for Talos, so I'd be > happy to continue. > > Martin I just wanted to bring this back up for discussion. Raptor is chipping in funding for over half of the development work, and Martin is matching pledges, so if there's interest in this port your contributions will go a long way, but it still depends on community interest. Are you willing to contribute to this development project? It is a limited time offer, so the quicker we can reach the relatively low goal to get this work underway the better. :-) Thanks! - -- Timothy Pearson Raptor Engineering +1 (415) 727-8645 (direct line) +1 (512) 690-0200 (switchboard) https://www.raptorengineering.com -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iQEcBAEBAgAGBQJYijUnAAoJEK+E3vEXDOFbQKAIAKPqeHZylATs3aZXC2QeTmUG p0bnwfU4G+0qkXEwApoYk+y8WRKEkhBsug5EvzEXw65fAAmwi4COVjUBvm2l9kUI m3/51sfrZRpo+H8c1lXld0WiwomTGapm9FX3rqAjLZn354TOqnrfoGYoJQC+ovKm 0AYXCGN8fmWkr6nTj9Q1tWwxEXrRv48YudF8bDFZhbMjOswnagNzImQNTC6wLgnY +7UyqBgpihc8vh3GoGuPQT1mNpAtUwv1PS8HFGnDO86zW9gWB7+xHEGBhMyy+Rys CTNWkI15X4dy8pz6XIsqjuBNSUcgTnVVAelecdm1BfykpgSyPyOf/39JQc/O41M= =HzeR -----END PGP SIGNATURE-----

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Re: [coreboot] minnowmax expertise needed
by Zoran Stojsavljevic 17 Apr '17

17 Apr '17

Hello Ron, Hmmmm.... I am afraid, you embarked on/boarded/asked the wrong forum. My best advice: you should go to Tiano Core forum to ask there these questions. Something like that: https://sourceforge.net/projects/tianocore/support Maybe even better pointer: http://www.tianocore.org/edk2/# This forum, you asked these questions, actually supports a bootloader called Coreboot, only. If you did not know!? :p What is MinnowMax? I always thought that MinnowMax is an INTEL IOTG BYT HW platform, INTEL development board. It actually started from ISG desire to support embedded Tunnel Creek/TNC (remember this one, ONLY 32bit ISG CPU creation, in Y2010, by INTEL ISG executives X & Y (X=JJ, Y=DD)? ISG (what is ISG, anyway?) experts developed this one, TNC, to compete with ARMv7. Hmmmmm... Did they succeed? JJ and DD certainly did. For sure! Both retired, although JJ ONLY once, DD many times (still dead loop executing)... ;-) And here is modernized version of one, you would like to do (some?!) job on it: http://elinux.org/Minnowboard:MinnowMax My best guess. Best, for sure. I have no idea why you need all of this, but what you would like to do is actually to use: [1] Either UEFI AMI BIOS on MinnowMax (BYT wise); [2] Either SEC+PEI (in binary form) + Tiano Core on MinnowMax (BYT wise). Anyway, the interesting question (after all) is the following: Why do you need this use case: "I want a single DXE, which PEI starts, and the DXE never returns. In this case it will be a linux kernel." I could not (as much as I am trying, now) envision such an use case (what are the features/requirements requested)...And for what??? Thank you, Ron! Zoran _______ On 4/17/17, ron minnich <rminnich(a)gmail.com> wrote: > On Mon, Apr 17, 2017 at 1:40 AM Zoran Stojsavljevic < > zoran.stojsavljevic(a)gmail.com> wrote: > >> >> >> As my best understanding is, INTEL FSP is nothing else, but stripped >> to the bones BIOS, with ONLY PEI phase in the charge (NOT the entire >> PEI, Platform init is selectively implemented in FSP). We have there >> CPU init, PCH init, and, at the very end. Platform init. >> > > is that what's in minnowmax? I am a bit unsure. > > >> >> Now, said that, I will ask the entire community the following questions: >> [1] What is the definition of Coreboot (in my naive vision, minimal/a >> must DXE + OS Boot Loader phase preparation - example: SeaBIOS >> payload)? >> > > my question is not really about coreboot. I'm not using coreboot in this > case. I'm hoping to gain from the expertise of this list. > > >> [2] What does it mean in your interpretation: "single DXE"? >> > > just that. I want a single DXE, which PEI starts, and the DXE never > returns. In this case it will be a linux kernel. > > >> [3] If you are talking about MinnowMax. I assume you are talking about >> ATOM BYT M/I skus, aren't you? >> > > Is that what turbot is? > > >> [4] Why, in the first place, INTEL FSP experts are NOT answering your >> quest, since they (I guess) better understand what you are asking >> for??? >> > > I don't know. > > >> [5] What does it mean: "our own Tiano Core"? Does INTEL does NOT own >> Tiano Core? Or Coreboot (Google) created its own Tiano Core??? >> >> > by 'our own tiano core' I simply mean a tiano core built from source. > > ron >

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coreboot April 2017