coreboot April 2017

coreboot@coreboot.org

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143 discussions

Re: [coreboot] minnowmax expertise needed
by ron minnich 17 Apr '17

17 Apr '17

On Mon, Apr 17, 2017 at 1:40 AM Zoran Stojsavljevic < zoran.stojsavljevic(a)gmail.com> wrote: > > > As my best understanding is, INTEL FSP is nothing else, but stripped > to the bones BIOS, with ONLY PEI phase in the charge (NOT the entire > PEI, Platform init is selectively implemented in FSP). We have there > CPU init, PCH init, and, at the very end. Platform init. > is that what's in minnowmax? I am a bit unsure. > > Now, said that, I will ask the entire community the following questions: > [1] What is the definition of Coreboot (in my naive vision, minimal/a > must DXE + OS Boot Loader phase preparation - example: SeaBIOS > payload)? > my question is not really about coreboot. I'm not using coreboot in this case. I'm hoping to gain from the expertise of this list. > [2] What does it mean in your interpretation: "single DXE"? > just that. I want a single DXE, which PEI starts, and the DXE never returns. In this case it will be a linux kernel. > [3] If you are talking about MinnowMax. I assume you are talking about > ATOM BYT M/I skus, aren't you? > Is that what turbot is? > [4] Why, in the first place, INTEL FSP experts are NOT answering your > quest, since they (I guess) better understand what you are asking > for??? > I don't know. > [5] What does it mean: "our own Tiano Core"? Does INTEL does NOT own > Tiano Core? Or Coreboot (Google) created its own Tiano Core??? > > by 'our own tiano core' I simply mean a tiano core built from source. ron

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Re: [coreboot] minnowmax expertise needed
by Zoran Stojsavljevic 17 Apr '17

17 Apr '17

Hello Ron, I have here significant problem to understand you. It is not a first time, but I would sign/stick this misunderstanding to my ignorance. :-( As my best understanding is, INTEL FSP is nothing else, but stripped to the bones BIOS, with ONLY PEI phase in the charge (NOT the entire PEI, Platform init is selectively implemented in FSP). We have there CPU init, PCH init, and, at the very end. Platform init. Now, said that, I will ask the entire community the following questions: [1] What is the definition of Coreboot (in my naive vision, minimal/a must DXE + OS Boot Loader phase preparation - example: SeaBIOS payload)? [2] What does it mean in your interpretation: "single DXE"? [3] If you are talking about MinnowMax. I assume you are talking about ATOM BYT M/I skus, aren't you? [4] Why, in the first place, INTEL FSP experts are NOT answering your quest, since they (I guess) better understand what you are asking for??? [5] What does it mean: "our own Tiano Core"? Does INTEL does NOT own Tiano Core? Or Coreboot (Google) created its own Tiano Core??? At least, you've heard from me. ;-) Thank you, Zoran _______ On 4/15/17, ron minnich <rminnich(a)gmail.com> wrote: > Hi, I'm starting to look at the minnowmax firmware images. I have a rather > odd requirement. I'd like to scrape the image down to just PEI, nothing > more, and then have that PEI load a single DXE, which will then take over. > > We've had success with this on a few other EFI sytsems, but the minnowmax > seems to be slightly special. We've done a small amount of work to > rearrange the firmware volume and quickly learned that you can't relocate > anything in the firmware volume ... they appear to have built it with > hardwired pointers to things like nvram variables (why bother with a flash > file system if you're going to do things like that ... oh well) ... so it > looks like at minimum we need to build/burn our own tiano core to start. > > Anyway, if you have looked at the minnowmax, I'd like to hear from you. > > Thanks! > > ron >

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Re: [coreboot] do i have to install gcc-multilib, in order to build coreboot 4.5?
by Zoran Stojsavljevic 17 Apr '17

17 Apr '17

Hello JC, Good to hear. :-) If anything deeper (more problems), please, continue sending @s to the whole list (reply to all), and. please, especially include Martin (Roth), since lot of these Coreboot environmental questions are just on the top of his head, and Martin will answer in no time. ;-) Zoran _______ On 4/17/17, jc <chaujohnthan(a)163.com> wrote: > Yes, i have, i am using slackware 13.1 64, so i can have any choice gcc > toolchain i wanted, > and i prefer that way > > > this does help, thank you very much! > > > > > > > > > > > At 2017-04-08 12:47:29, "Zoran Stojsavljevic" > <zoran.stojsavljyesevic(a)gmail.com> wrote: > >> So i need elf gcc 32/64 both, bulit with newlib in place of glibc? > > > > JC, I have no idea what architecture you are using, but here are the > pointers how to install Coreboot gcc: > https://www.coreboot.org/Build_HOWTO > > > > Instructions for gcc: assuming you just want to build x86 platforms, > refreshing the tools should still just be: > make crossgcc-clean > make crossgcc-i386 > > > If you want to store the tools somewhere outside of the coreboot tree, you > can put the xgcc/bin/ directory in your path, or set the XGCCPATH > environment variable pointing to it. (This must include the final slash.) > > > Hope this helps. > > > Zoran > _______ > > > On Sat, Apr 8, 2017 at 3:27 AM, jc <chaujohnthan(a)163.com> wrote: > > > > So i need elf gcc 32/64 both, bulit with newlib in place of glibc? > > > > > > > > > 在 2017-04-08 00:36:31，"Zoran Stojsavljevic" <zoran.stojsavljevic(a)gmail.com> > 写道： > > Naive question... !? > > > Zoran > > > On Wed, Apr 5, 2017 at 12:09 PM, jc <chaujohnthan(a)163.com> wrote: > > ? > > -- > coreboot mailing list: coreboot(a)mail.coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot > > > > >

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minnowmax expertise needed
by ron minnich 15 Apr '17

15 Apr '17

Hi, I'm starting to look at the minnowmax firmware images. I have a rather odd requirement. I'd like to scrape the image down to just PEI, nothing more, and then have that PEI load a single DXE, which will then take over. We've had success with this on a few other EFI sytsems, but the minnowmax seems to be slightly special. We've done a small amount of work to rearrange the firmware volume and quickly learned that you can't relocate anything in the firmware volume ... they appear to have built it with hardwired pointers to things like nvram variables (why bother with a flash file system if you're going to do things like that ... oh well) ... so it looks like at minimum we need to build/burn our own tiano core to start. Anyway, if you have looked at the minnowmax, I'd like to hear from you. Thanks! ron

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BeagleBone Black [Master/Slave] Connection
by Haleigh Novak 15 Apr '17

15 Apr '17

Hello All, I am trying to connect a BBB (setup properly for ehci debugging) to a machine that was designed here at my work [well call it '(Cust)' for simplicity] I also have the running 'model' machine [lets call this one '(Orig)'] that the custom one was designed to mimic. I'm hoping that through this email I will reach enough people who have used the BeagleBone Black [BBB] to answer these questions based on the information below the questions. (Forgive me if the question is badly worded, its complicated to explain without visuals - let me know if you need a better explanation.) 0) Is there a way to tell 100% for certain (a query or status of some sort) which device is considered the Master/Host and which device is considered the Slave/Peripheral in a usb connection between two fully functional stand alone machines? 1) For proper use does the BBB have to be classified as the Master/Host in the usb connection? 2) For proper use does the BBB require the connected machine (the one that ehci debugging info is desired from) to be a Master/Host, or a Slave/Peripheral device, or does it not matter; to allow successful ehci debugging? [The above questions I have been Goggling, I have not found a strait forward, verified/well explained answer.] 3) The conversion cord I am using I strongly suspect is an OTG, and therefore as it is connected, defines the (Cust) to be the Master/Host - would this cause a 'fight' for Master/Host status that the BBB looses and is as a result classified as a Peripheral/Slave device and rendered non-functional for my needs? [p.s - I know this conversion cord works because I can plug it into (Cust) and on the other end have a peripheral (usb flash, mouse, keyboard - all tested) plugged in and utilize the peripheral without any issue.] 4) If (1) is yes, (2) is doesn't matter or slave/peripheral; is there a way to force the usb to reclassify? Say force (Cust) to be a Slave/Peripheral device and the BBB to be the Master/Host? The BBB connects to an ehci capable port (for ehci debugging) via a MINI B connector in the BBB and a full sized usb to connect to the debug machine. Now (Orig) has full sized usb ports to which I can connect the BBB directly to and I successfully get the echi debugging information. However (Cust) only has MICRO B connectors - so I have to use a conversion cable on the end of the BBB cable to get the proper size. The ports on the respective 'debug' machines are verified ehci capable ports, both machines have coreboot - exactly the same except for the VGA Device IDs. However (Cust) will not recognize the BBB properly, and sets it up as an ohci device - rendering the BBB virtually useless. Below is the dmesg on both machines of removing and re-inserting the BBB debug cable from the equivalent port. # DMESG addition on (Orig) after removing and re-inserting the BBB usb into the same port usb 1-3: USB disconnect, device number 2 usb 1-3: new high speed USB device number 3 using ehci_hcd usb 1-3: unable to read config index 0 descriptor/start: -32 usb 1-3: chopping to 0 config(s) usb 1-3: New USB device found, idVendor=0525, idProduct=c0de usb 1-3: New USB device strings: Mfr=0, Product=0, SerialNumber=0 usb 1-3: no configuration chosen from 0 choices # DMESG addition on (Cust) after removing and re-inserting the BBB usb into the same port usb 4-1: USB disconnect, device number 2 usb 1-1: new high speed USB device number 6 using ehci_hcd usb 1-1: device descriptor read/64, error -71 usb 1-1: device descriptor read/64, error -71 usb 1-1: new high speed USB device number 7 using ehci_hcd usb 1-1: device descriptor read/64, error -71 usb 1-1: device descriptor read/64, error -71 usb 1-1: new high speed USB device number 8 using ehci_hcd usb 1-1: device not accepting address 8, error -71 usb 1-1: new high speed USB device number 9 using ehci_hcd usb 1-1: device not accepting address 9, error -71 hub 1-0:1.0: unable to enumerate USB device on port 1 usb 4-1: new full speed USB device number 3 using ohci_hcd usb 4-1: unable to read config index 0 descriptor/start: -32 usb 4-1: chopping to 0 config(s) usb 4-1: New USB device found, idVendor=0525, idProduct=c0de usb 4-1: New USB device strings: Mfr=0, Product=0, SerialNumber=0 usb 4-1: no configuration chosen from 0 choices Thank you for taking the time to read this. If anyone has any other suggestions as to what might be causing my issue I welcome any thoughts :). H

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Re: [coreboot] ThinkPad X230 alternative flash chips?
by Trammell Hudson 15 Apr '17

15 Apr '17

4 MB was quite limiting and it seemed like an artificial restriction, especially since all the other machines have larger space available. Since flashing both chips with an external programmer is a bit of a pain, there is still a 4 MB version built with just flashrom and the USB drivers. So you can flash that one, reboot into it, mount your flash drive and then run flashrom to write the full 7 MB image with all the tools. If the management engine is cleaned there is even more space available, with the caveat that the e1000 ethernet stops working since the kernel can't coordinate its handoff with the ME. To paraphrase billg: "7MB ought to be enouh for anybody". -- Trammell On Sat, Apr 15, 2017 at 06:11:14AM +0000, Thierry Laurion wrote: > In fact, all the 7mb is now available. > Check that out! https://github.com/osresearch/heads/releases/tag/v0.2.0 > > Le ven. 14 avr. 2017 à 23:38, Thierry Laurion <thierry.laurion(a)gmail.com> a > écrit : > > > The x230 has two rom chips. One that has 4mb that boots the system, and > > one that is 8mb that holds ME. http://osresearch.net/ planned on using > > freed space in the ME after deactivating it, but I haven't seen usage of > > that freed space yet. > > > > Le ven. 14 avr. 2017 à 21:15, Marek Behun <kabel(a)blackhole.sk> a écrit : > > > >> > It looks like the X230 already has a large flash chip > >> > (BOARD_ROMSIZE_12288?). How big were you thinking? The main issue > >> > would be that chips bigger than 16MB use 4-byte addresses and the SPI > >> > controller in Ivy Bridge probably only supports 3-byte addresses. > >> > >> I have ordered two 32 MB Macronix chips, with the hope to have 64 MB of > >> space. If what you say is true, they won't work :( > >> > >> Marek > >> -- > >> coreboot mailing list: coreboot(a)coreboot.org > >> https://mail.coreboot.org/mailman/listinfo/coreboot > > > > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot

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Re: [coreboot] ThinkPad X230 alternative flash chips?
by Thierry Laurion 15 Apr '17

15 Apr '17

In fact, all the 7mb is now available. Check that out! https://github.com/osresearch/heads/releases/tag/v0.2.0 Le ven. 14 avr. 2017 à 23:38, Thierry Laurion <thierry.laurion(a)gmail.com> a écrit : > The x230 has two rom chips. One that has 4mb that boots the system, and > one that is 8mb that holds ME. http://osresearch.net/ planned on using > freed space in the ME after deactivating it, but I haven't seen usage of > that freed space yet. > > Le ven. 14 avr. 2017 à 21:15, Marek Behun <kabel(a)blackhole.sk> a écrit : > >> > It looks like the X230 already has a large flash chip >> > (BOARD_ROMSIZE_12288?). How big were you thinking? The main issue >> > would be that chips bigger than 16MB use 4-byte addresses and the SPI >> > controller in Ivy Bridge probably only supports 3-byte addresses. >> >> I have ordered two 32 MB Macronix chips, with the hope to have 64 MB of >> space. If what you say is true, they won't work :( >> >> Marek >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> https://mail.coreboot.org/mailman/listinfo/coreboot > >

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Re: [coreboot] ThinkPad X230 alternative flash chips?
by Marek Behun 15 Apr '17

15 Apr '17

> It looks like the X230 already has a large flash chip > (BOARD_ROMSIZE_12288?). How big were you thinking? The main issue > would be that chips bigger than 16MB use 4-byte addresses and the SPI > controller in Ivy Bridge probably only supports 3-byte addresses. I have ordered two 32 MB Macronix chips, with the hope to have 64 MB of space. If what you say is true, they won't work :( Marek

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ThinkPad X230 alternative flash chips?
by Marek Behun 14 Apr '17

14 Apr '17

Hello, does someone know if it is possible to solder a bigger flash chip onto ThinkPad X230? Would it work? It would be awesome if I could fit a bigger kernel as a payload... MB

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List of my changes to merge for coreboot 4.6
by Paul Menzel 14 Apr '17

14 Apr '17

Dear coreboot folks, It’d be great if the small changes below could be reviewed and submitted before coreboot 4.6 is released. 1. https://review.coreboot.org/18907/ 2. https://review.coreboot.org/18906/ 3. https://review.coreboot.org/18794/ 4. https://review.coreboot.org/18829/ Thanks, Paul

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coreboot April 2017