coreboot April 2017

coreboot@coreboot.org

65 participants
143 discussions

Please revert change of List-Id
by Paul Menzel 08 Apr '17

08 Apr '17

Dear coreboot server list administrators, It looks like the List-Id of the lists provided by the coreboot server – at least coreboot, flashrom, SeaBIOS – changed from List-Id: coreboot project mailing list <coreboot.coreboot.org> to List-Id: coreboot project mailing list <coreboot.mail.coreboot.org> which looks like a change in the domain name/host name from *coreboot.org* to *mail.coreboot.org*. That affects the configured filters of probably a lot of subscribers. It’d be awesome, if the ID could be reverted to the old one. Thanks, Paul

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Re: [coreboot] do i have to install gcc-multilib, in order to build coreboot 4.5?
by Zoran Stojsavljevic 08 Apr '17

08 Apr '17

> So i need elf gcc 32/64 both, bulit with newlib in place of glibc? JC, I have no idea what architecture you are using, but here are the pointers how to install Coreboot gcc: https://www.coreboot.org/Build_HOWTO Instructions for gcc: assuming you just want to build x86 platforms, refreshing the tools should still just be: make crossgcc-clean make crossgcc-i386 If you want to store the tools somewhere outside of the coreboot tree, you can put the xgcc/bin/ directory in your path, or set the XGCCPATH environment variable pointing to it. (This must include the final slash.) Hope this helps. Zoran _______ On Sat, Apr 8, 2017 at 3:27 AM, jc <chaujohnthan(a)163.com> wrote: > > So i need elf gcc 32/64 both, bulit with newlib in place of glibc? > > > > > 在 2017-04-08 00:36:31，"Zoran Stojsavljevic" <zoran.stojsavljevic(a)gmail.com> > 写道： > > Naive question... !? > > Zoran > > On Wed, Apr 5, 2017 at 12:09 PM, jc <chaujohnthan(a)163.com> wrote: > >> ? >> >> -- >> coreboot mailing list: coreboot(a)mail.coreboot.org >> https://mail.coreboot.org/mailman/listinfo/coreboot >> > >

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Re: [coreboot] do i have to install gcc-multilib, in order to build coreboot 4.5?
by Nico Huber 07 Apr '17

07 Apr '17

On 07.04.2017 18:36, Zoran Stojsavljevic wrote: > Naive question... !? Well, the answer is no. You don't have to. You should build the coreboot toolchain instead: `make crossgcc-i386` or see `make help`. Nico PS. Please write your questions into the email body, you'll get better answers and hit less spam filters.

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do i have to install gcc-multilib, in order to build coreboot 4.5?
by jc 07 Apr '17

07 Apr '17

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Re: [coreboot] Help on debug, add a new mainboard.
by tturne＠codeaurora.org 07 Apr '17

07 Apr '17

On 2017-04-06 07:34, Kory Maincent wrote: > Hi everyone, > > I would like to learn how to add a new mainboard to coreboot. > I have a Fujitsu D2990-A1, with chipset intel H61, sandybridge and a > Superio Nuvoton NCT5571D. > I use the autoport tools to generate the files. > I know that I have to change them to add new configuration but I don't > really know how. > Can you help me to get started with the debug part or to give me some > advice about it. Hi Kory, I started with Coreboot for an ARMv8 target last Fall, with no prior exposure. This outlines the steps I followed, close as I recall. 1) clone the repo, build the tools and build a "safe" target (e.g. one of the emulator, qemu) 2) find a target board that uses same chipset as your target and build 3) copy mainboard/ directory to new one with your codename for a board 4) change config and function names, etc. to reflect new board 5) stub-out what needs to be stubbed out to get a build to complete At this point you have a new sandbox for your board based on an existing board that uses same chipset. There are Kconfig files in the soc/ or cpu/ directory for your chipset and the mainboard/ directory you created. Typically you won't change the soc/ or cpu/ Kconfig, but you should be aware of what the settings are. Most of your configuration should occur within the Kconfig file in your new mainboard/ directory. Hope this helps. Cheers, T.mike > > I have downloaded the Embedde Firmware Solution eBook to begin with. > > Thanks > > Kory > > This is my debug output > > USB > coreboot-coreboot-unknown Wed Apr 5 15:19:21 UTC 2017 romstage > starting... > Setting up static southbridge registers... done. > Disabling Watchdog reboot... done. > Setting up static northbridge registers... done. > Graphics not supported by this CPU/chipset. > Back from sandybridge_early_initialization() > SMBus controller enabled. > CPU id(206a7): Intel(R) Core(TM) i7-2600 CPU @ 3.40GHz > AES supported, TXT supported, VT supported > PCH type: H61, device id: 1c5c, rev id 5 > Intel ME early init > WARNING: ME has bad firmware > ME: Requested 63MB UMA > Starting native Platform init > CBFS: 'Master Header Locator' located CBFS at [200100:3fffc0) > CBFS: Locating 'mrc.cache' > CBFS: Found @ offset 1fec0 size 10000 > find_current_mrc_cache_local: No valid MRC cache found. > Row addr bits : 15 > Column addr bits : 10 > Number of ranks : 2 > DIMM Capacity : 4096 MB > CAS latencies : 6 7 8 9 10 > tCKmin : 1.500 ns > tAAmin : 13.125 ns > tWRmin : 15.000 ns > tRCDmin : 13.125 ns > tRRDmin : 6.000 ns > tRPmin : 13.125 ns > tRASmin : 36.000 ns > tRCmin : 49.125 ns > tRFCmin : 160.000 ns > tWTRmin : 7.500 ns > tRTPmin : 7.500 ns > tFAWmin : 30.000 ns > channel[1] rankmap = 0x3 > Starting RAM training (0). > PLL busy... done in 10 us > MCU frequency is set at : 666 MHz > Selected DRAM frequency: 666 MHz > Minimum CAS latency : 9T > Selected CAS latency : 9T > Selected CWL latency : 7T > Selected tRCD : 9T > Selected tRP : 9T > Selected tRAS : 24T > Selected tWR : 10T > Selected tFAW : 20T > Selected tRRD : 4T > Selected tRTP : 5T > Selected tWTR : 5T > Selected tRFC : 107T > Done dimm mapping > Update PCI-E configuration space: > PCI(0, 0, 0)[a0] = 0 > PCI(0, 0, 0)[a4] = 1 > PCI(0, 0, 0)[bc] = 8a800000 > PCI(0, 0, 0)[a8] = 71900000 > PCI(0, 0, 0)[ac] = 1 > PCI(0, 0, 0)[b8] = 80000000 > PCI(0, 0, 0)[b0] = 80800000 > PCI(0, 0, 0)[b4] = 80800000 > PCI(0, 0, 0)[7c] = 7f > PCI(0, 0, 0)[70] = fc100000 > PCI(0, 0, 0)[74] = 0 > PCI(0, 0, 0)[78] = fc100c00 > Done memory map > Done io registers > Done jedec reset > Done MRS commands > t123: 1912, 9120, 500 > ME: FW Partition Table : BAD > ME: Bringup Loader Failure : YES > ME: Firmware Init Complete : YES > ME: Manufacturing Mode : YES > ME: Boot Options Present : YES > ME: Update In Progress : YES > ¡8—d$ > ME: Current Operation State : M0 without UMA but with error > ME: Current Operation Mode : Reset > ME: Error Code : <NULL> > ME: Progress Phase : Soft Temporary Disable > ME: Power Management Event : uKernel Phase > ME: Progress Phase State : Unknown 0xff > ME: Wrong mode : 15 > ME: HFS error : 15 > ME: FWS2: 0xffffffff > ME: Bist in progress: 0x1 > ME: ICC Status : 0x3 > ME: Invoke MEBx : 0x1 > ME: CPU replaced : 0x1 > ME: MBP ready : 0x1 > ME: MFS failure : 0x1 > ME: Warm reset req : 0x1 > ME: CPU repl valid : 0x1 > ME: (Reserved) : 0x3 > ME: FW update req : 0x1 > ME: (Reserved) : 0xf > ME: Current state : 0xff > ME: Current PM event: 0xf > ME: Progress code : 0xf > CPU was replaced & warm reset required...

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New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com 07 Apr '17

07 Apr '17

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 298 new defect(s) introduced to coreboot found with Coverity Scan. 12 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 20 of 298 defect(s) ** CID 1370586: (UNINIT) /src/mainboard/asus/kfsn4-dre/romstage.c: 123 in ck804_control() /src/mainboard/asus/kfsn4-dre/romstage.c: 123 in ck804_control() /src/mainboard/asus/kfsn4-dre_k8/romstage.c: 129 in ck804_control() /src/mainboard/asus/kfsn4-dre_k8/romstage.c: 129 in ck804_control() ________________________________________________________________________________________________________ *** CID 1370586: (UNINIT) /src/mainboard/asus/kfsn4-dre/romstage.c: 123 in ck804_control() 117 static const unsigned int ctrl_conf_enable_msi_mapping[] = { 118 RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xe0), ~(0x00000000), 0x00010000, /* Enable MSI mapping on host bridge -- without this Linux cannot use the network device MSI interrupts! */ 119 }; 120 121 static void ck804_control(const unsigned int* values, u32 size, uint8_t bus_unit_id) 122 { >>> CID 1370586: (UNINIT) >>> Declaring variable "io_base" without initializer. 123 unsigned busn[4], io_base[4]; 124 int i, ck804_num = 0; 125 126 for (i = 0; i < 4; i++) { 127 u32 id; 128 pci_devfn_t dev; /src/mainboard/asus/kfsn4-dre/romstage.c: 123 in ck804_control() 117 static const unsigned int ctrl_conf_enable_msi_mapping[] = { 118 RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xe0), ~(0x00000000), 0x00010000, /* Enable MSI mapping on host bridge -- without this Linux cannot use the network device MSI interrupts! */ 119 }; 120 121 static void ck804_control(const unsigned int* values, u32 size, uint8_t bus_unit_id) 122 { >>> CID 1370586: (UNINIT) >>> Declaring variable "io_base" without initializer. 123 unsigned busn[4], io_base[4]; 124 int i, ck804_num = 0; 125 126 for (i = 0; i < 4; i++) { 127 u32 id; 128 pci_devfn_t dev; /src/mainboard/asus/kfsn4-dre_k8/romstage.c: 129 in ck804_control() 123 static const unsigned int ctrl_conf_enable_msi_mapping[] = { 124 RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xe0), ~(0x00000000), 0x00010000, /* Enable MSI mapping on host bridge -- without this Linux cannot use the network device MSI interrupts! */ 125 }; 126 127 static void ck804_control(const unsigned int* values, u32 size, uint8_t bus_unit_id) 128 { >>> CID 1370586: (UNINIT) >>> Declaring variable "io_base" without initializer. 129 unsigned busn[4], io_base[4]; 130 int i, ck804_num = 0; 131 132 for (i = 0; i < 4; i++) { 133 u32 id; 134 pci_devfn_t dev; /src/mainboard/asus/kfsn4-dre_k8/romstage.c: 129 in ck804_control() 123 static const unsigned int ctrl_conf_enable_msi_mapping[] = { 124 RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xe0), ~(0x00000000), 0x00010000, /* Enable MSI mapping on host bridge -- without this Linux cannot use the network device MSI interrupts! */ 125 }; 126 127 static void ck804_control(const unsigned int* values, u32 size, uint8_t bus_unit_id) 128 { >>> CID 1370586: (UNINIT) >>> Declaring variable "io_base" without initializer. 129 unsigned busn[4], io_base[4]; 130 int i, ck804_num = 0; 131 132 for (i = 0; i < 4; i++) { 133 u32 id; 134 pci_devfn_t dev; ** CID 1370583: Uninitialized variables (UNINIT) /src/southbridge/nvidia/ck804/early_setup_car.c: 350 in ck804_early_setup_x() ________________________________________________________________________________________________________ *** CID 1370583: Uninitialized variables (UNINIT) /src/southbridge/nvidia/ck804/early_setup_car.c: 350 in ck804_early_setup_x() 344 busn[ck804_num] = i * 0x40; 345 io_base[ck804_num] = i * 0x4000; 346 ck804_num++; 347 } 348 } 349 >>> CID 1370583: Uninitialized variables (UNINIT) >>> Using uninitialized value "busn[0]" when calling "do_printk". 350 printk(BIOS_DEBUG, "ck804_early_set_port(%d, %d, %d)\n", ck804_num, busn[0], io_base[0]); 351 ck804_early_set_port(ck804_num, busn, io_base); 352 printk(BIOS_DEBUG, "ck804_early_setup(%d, %d, %d)\n", ck804_num, busn[0], io_base[0]); 353 ck804_early_setup(ck804_num, busn, io_base); 354 printk(BIOS_DEBUG, "ck804_early_clear_port(%d, %d, %d)\n", ck804_num, busn[0], io_base[0]); 355 ck804_early_clear_port(ck804_num, busn, io_base); ** CID 1370582: Uninitialized variables (UNINIT) /src/cpu/x86/mtrr/mtrr.c: 347 in commit_fixed_mtrrs() ________________________________________________________________________________________________________ *** CID 1370582: Uninitialized variables (UNINIT) /src/cpu/x86/mtrr/mtrr.c: 347 in commit_fixed_mtrrs() 341 fixed_mtrr_types[type_index++] << 24; 342 msr_num++; 343 } 344 } 345 346 for (i = 0; i < ARRAY_SIZE(fixed_msrs); i++) >>> CID 1370582: Uninitialized variables (UNINIT) >>> Using uninitialized value "msr_index[i]" when calling "do_printk". 347 printk(BIOS_DEBUG, "MTRR: Fixed MSR 0x%lx 0x%08x%08x\n", 348 msr_index[i], fixed_msrs[i].hi, fixed_msrs[i].lo); 349 350 disable_cache(); 351 for (i = 0; i < ARRAY_SIZE(fixed_msrs); i++) 352 wrmsr(msr_index[i], fixed_msrs[i]); ** CID 1370581: Uninitialized variables (UNINIT) /src/southbridge/nvidia/ck804/early_setup_car.c: 350 in ck804_early_setup_x() ________________________________________________________________________________________________________ *** CID 1370581: Uninitialized variables (UNINIT) /src/southbridge/nvidia/ck804/early_setup_car.c: 350 in ck804_early_setup_x() 344 busn[ck804_num] = i * 0x40; 345 io_base[ck804_num] = i * 0x4000; 346 ck804_num++; 347 } 348 } 349 >>> CID 1370581: Uninitialized variables (UNINIT) >>> Using uninitialized value "io_base[0]" when calling "do_printk". 350 printk(BIOS_DEBUG, "ck804_early_set_port(%d, %d, %d)\n", ck804_num, busn[0], io_base[0]); 351 ck804_early_set_port(ck804_num, busn, io_base); 352 printk(BIOS_DEBUG, "ck804_early_setup(%d, %d, %d)\n", ck804_num, busn[0], io_base[0]); 353 ck804_early_setup(ck804_num, busn, io_base); 354 printk(BIOS_DEBUG, "ck804_early_clear_port(%d, %d, %d)\n", ck804_num, busn[0], io_base[0]); 355 ck804_early_clear_port(ck804_num, busn, io_base); ** CID 1370580: Uninitialized variables (UNINIT) /src/northbridge/intel/x4x/raminit_ddr2.c: 1465 in rcven_ddr2() ________________________________________________________________________________________________________ *** CID 1370580: Uninitialized variables (UNINIT) /src/northbridge/intel/x4x/raminit_ddr2.c: 1465 in rcven_ddr2() 1459 MCHBAR8(0x400*ch + 0x560 + (lane*4)) = 1460 (MCHBAR8(0x400*ch + 0x560 + (lane*4)) & ~0xf) | pitap[ch][lane]; 1461 } 1462 MCHBAR32(0x400*ch + 0x248) = (MCHBAR32(0x400*ch + 0x248) & ~0xf0000) | 1463 (coarsectrl[ch] << 16); 1464 MCHBAR16(0x400*ch + 0x5fa) = coarsedelay[ch]; >>> CID 1370580: Uninitialized variables (UNINIT) >>> Using uninitialized value "mediumphase[ch]". 1465 MCHBAR16(0x400*ch + 0x58c) = mediumphase[ch]; 1466 } 1467 printk(BIOS_DEBUG, "End rcven\n"); 1468 } 1469 1470 static void sdram_save_receive_enable(void) ** CID 1370579: Uninitialized variables (UNINIT) /src/northbridge/intel/x4x/raminit_ddr2.c: 1464 in rcven_ddr2() ________________________________________________________________________________________________________ *** CID 1370579: Uninitialized variables (UNINIT) /src/northbridge/intel/x4x/raminit_ddr2.c: 1464 in rcven_ddr2() 1458 for (lane = 0; lane < 8; lane++) { 1459 MCHBAR8(0x400*ch + 0x560 + (lane*4)) = 1460 (MCHBAR8(0x400*ch + 0x560 + (lane*4)) & ~0xf) | pitap[ch][lane]; 1461 } 1462 MCHBAR32(0x400*ch + 0x248) = (MCHBAR32(0x400*ch + 0x248) & ~0xf0000) | 1463 (coarsectrl[ch] << 16); >>> CID 1370579: Uninitialized variables (UNINIT) >>> Using uninitialized value "coarsedelay[ch]". 1464 MCHBAR16(0x400*ch + 0x5fa) = coarsedelay[ch]; 1465 MCHBAR16(0x400*ch + 0x58c) = mediumphase[ch]; 1466 } 1467 printk(BIOS_DEBUG, "End rcven\n"); 1468 } 1469 ** CID 1370578: (UNINIT) /src/mainboard/asus/kfsn4-dre/romstage.c: 123 in ck804_control() /src/mainboard/asus/kfsn4-dre/romstage.c: 123 in ck804_control() /src/mainboard/asus/kfsn4-dre_k8/romstage.c: 129 in ck804_control() /src/mainboard/asus/kfsn4-dre_k8/romstage.c: 129 in ck804_control() ________________________________________________________________________________________________________ *** CID 1370578: (UNINIT) /src/mainboard/asus/kfsn4-dre/romstage.c: 123 in ck804_control() 117 static const unsigned int ctrl_conf_enable_msi_mapping[] = { 118 RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xe0), ~(0x00000000), 0x00010000, /* Enable MSI mapping on host bridge -- without this Linux cannot use the network device MSI interrupts! */ 119 }; 120 121 static void ck804_control(const unsigned int* values, u32 size, uint8_t bus_unit_id) 122 { >>> CID 1370578: (UNINIT) >>> Declaring variable "busn" without initializer. 123 unsigned busn[4], io_base[4]; 124 int i, ck804_num = 0; 125 126 for (i = 0; i < 4; i++) { 127 u32 id; 128 pci_devfn_t dev; /src/mainboard/asus/kfsn4-dre/romstage.c: 123 in ck804_control() 117 static const unsigned int ctrl_conf_enable_msi_mapping[] = { 118 RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xe0), ~(0x00000000), 0x00010000, /* Enable MSI mapping on host bridge -- without this Linux cannot use the network device MSI interrupts! */ 119 }; 120 121 static void ck804_control(const unsigned int* values, u32 size, uint8_t bus_unit_id) 122 { >>> CID 1370578: (UNINIT) >>> Declaring variable "busn" without initializer. 123 unsigned busn[4], io_base[4]; 124 int i, ck804_num = 0; 125 126 for (i = 0; i < 4; i++) { 127 u32 id; 128 pci_devfn_t dev; /src/mainboard/asus/kfsn4-dre_k8/romstage.c: 129 in ck804_control() 123 static const unsigned int ctrl_conf_enable_msi_mapping[] = { 124 RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xe0), ~(0x00000000), 0x00010000, /* Enable MSI mapping on host bridge -- without this Linux cannot use the network device MSI interrupts! */ 125 }; 126 127 static void ck804_control(const unsigned int* values, u32 size, uint8_t bus_unit_id) 128 { >>> CID 1370578: (UNINIT) >>> Declaring variable "busn" without initializer. 129 unsigned busn[4], io_base[4]; 130 int i, ck804_num = 0; 131 132 for (i = 0; i < 4; i++) { 133 u32 id; 134 pci_devfn_t dev; /src/mainboard/asus/kfsn4-dre_k8/romstage.c: 129 in ck804_control() 123 static const unsigned int ctrl_conf_enable_msi_mapping[] = { 124 RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xe0), ~(0x00000000), 0x00010000, /* Enable MSI mapping on host bridge -- without this Linux cannot use the network device MSI interrupts! */ 125 }; 126 127 static void ck804_control(const unsigned int* values, u32 size, uint8_t bus_unit_id) 128 { >>> CID 1370578: (UNINIT) >>> Declaring variable "busn" without initializer. 129 unsigned busn[4], io_base[4]; 130 int i, ck804_num = 0; 131 132 for (i = 0; i < 4; i++) { 133 u32 id; 134 pci_devfn_t dev; ** CID 1370576: Null pointer dereferences (REVERSE_INULL) /src/lib/edid.c: 1144 in decode_edid() ________________________________________________________________________________________________________ *** CID 1370576: Null pointer dereferences (REVERSE_INULL) /src/lib/edid.c: 1144 in decode_edid() 1138 }; 1139 1140 dump_breakdown(edid); 1141 1142 memset(out, 0, sizeof(*out)); 1143 >>> CID 1370576: Null pointer dereferences (REVERSE_INULL) >>> Null-checking "edid" suggests that it may be null, but it has already been dereferenced on all paths leading to the check. 1144 if (!edid || memcmp(edid, "\x00\xFF\xFF\xFF\xFF\xFF\xFF\x00", 8)) { 1145 printk(BIOS_SPEW, "No header found\n"); 1146 return 1; 1147 } 1148 1149 if (manufacturer_name(edid + 0x08)) ** CID 1370574: (DIVIDE_BY_ZERO) /src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/DMI/mfDMI.c: 383 in MemFDMISupport3() /src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/DMI/mfDMI.c: 333 in MemFDMISupport3() /src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/DMI/mfDMI.c: 311 in MemFDMISupport3() /src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/DMI/mfDMI.c: 311 in MemFDMISupport3() /src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/DMI/mfDMI.c: 318 in MemFDMISupport3() ________________________________________________________________________________________________________ *** CID 1370574: (DIVIDE_BY_ZERO) /src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/DMI/mfDMI.c: 383 in MemFDMISupport3() 377 Rank = 3; // 16 bits 378 } else if (((temp >> 3) & 0x07) == 3) { 379 Rank = 4; // 32 bits 380 DmiPhysicalDimmInfoTable->Attributes = 4; // Quad Rank Dimm 381 } 382 >>> CID 1370574: (DIVIDE_BY_ZERO) >>> In expression "Capacity / 8 * BusWidth / Width", division by expression "Width" which may be zero has undefined behavior. 383 DimmSize = (UINT32) (Capacity / 8 * BusWidth / Width * Rank); 384 if (DimmSize < 0x7FFF) { 385 DmiPhysicalDimmInfoTable->MemorySize = (UINT16) DimmSize; 386 } else { 387 DmiPhysicalDimmInfoTable->MemorySize = 0x7FFF; 388 DmiPhysicalDimmInfoTable->ExtSize = DimmSize; /src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/DMI/mfDMI.c: 333 in MemFDMISupport3() 327 Rank = 3; // 16 bits 328 } else if (((temp >> 3) & 0x07) == 3) { 329 Rank = 4; // 32 bits 330 DmiTable[DimmIndex].Attributes = 4; // Quad Rank Dimm 331 } 332 >>> CID 1370574: (DIVIDE_BY_ZERO) >>> In expression "Capacity / 8 * BusWidth / Width", division by expression "Width" which may be zero has undefined behavior. 333 DimmSize = (UINT32) (Capacity / 8 * BusWidth / Width * Rank); 334 if (DimmSize < 0x7FFF) { 335 DmiTable[DimmIndex].MemorySize = (UINT16) DimmSize; 336 } else { 337 DmiTable[DimmIndex].MemorySize = 0x7FFF; 338 DmiTable[DimmIndex].ExtSize = DimmSize; /src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/DMI/mfDMI.c: 311 in MemFDMISupport3() 305 Rank = 3; // 16 bits 306 } else if (((temp >> 3) & 0x07) == 3) { 307 Rank = 4; // 32 bits 308 DmiTable[DimmIndex].Attributes = 4; // Quad Rank Dimm 309 } 310 >>> CID 1370574: (DIVIDE_BY_ZERO) >>> In expression "Capacity / 8 * BusWidth / Width", division by expression "Width" which may be zero has undefined behavior. 311 DmiTable[DimmIndex].MemorySize = (UINT16) (Capacity / 8 * BusWidth / Width * Rank); 312 313 // Form Factor (offset 0Eh) 314 FormFactor = (UINT8) SpdDataStructure[DimmIndex].Data[3]; 315 if ((FormFactor & 0x01) == 0 || (FormFactor & 0x02) == 0) { 316 DmiTable[DimmIndex].FormFactor = 0x09; // RDIMM or UDIMM /src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/DMI/mfDMI.c: 311 in MemFDMISupport3() 305 Rank = 3; // 16 bits 306 } else if (((temp >> 3) & 0x07) == 3) { 307 Rank = 4; // 32 bits 308 DmiTable[DimmIndex].Attributes = 4; // Quad Rank Dimm 309 } 310 >>> CID 1370574: (DIVIDE_BY_ZERO) >>> In expression "Capacity / 8 * BusWidth / Width", division by expression "Width" which may be zero has undefined behavior. 311 DmiTable[DimmIndex].MemorySize = (UINT16) (Capacity / 8 * BusWidth / Width * Rank); 312 313 // Form Factor (offset 0Eh) 314 FormFactor = (UINT8) SpdDataStructure[DimmIndex].Data[3]; 315 if ((FormFactor & 0x01) == 0 || (FormFactor & 0x02) == 0) { 316 DmiTable[DimmIndex].FormFactor = 0x09; // RDIMM or UDIMM /src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/DMI/mfDMI.c: 318 in MemFDMISupport3() 312 Rank = 3; // 16 bits 313 } else if (((temp >> 3) & 0x07) == 3) { 314 Rank = 4; // 32 bits 315 DmiTable[DimmIndex].Attributes = 4; // Quad Rank Dimm 316 } 317 >>> CID 1370574: (DIVIDE_BY_ZERO) >>> In expression "Capacity / 8 * BusWidth / Width", division by expression "Width" which may be zero has undefined behavior. 318 DimmSize = (UINT32) (Capacity / 8 * BusWidth / Width * Rank); 319 if (DimmSize < 0x7FFF) { 320 DmiTable[DimmIndex].MemorySize = (UINT16) DimmSize; 321 } else { 322 DmiTable[DimmIndex].MemorySize = 0x7FFF; 323 DmiTable[DimmIndex].ExtSize = DimmSize; ** CID 1368413: Control flow issues (DEADCODE) /3rdparty/arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/dfs.c: 1236 in gen_rk3399_ctl_params() ________________________________________________________________________________________________________ *** CID 1368413: Control flow issues (DEADCODE) /3rdparty/arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/dfs.c: 1236 in gen_rk3399_ctl_params() 1230 tmp0 |= (1 << 24); 1231 #endif 1232 for (i = 0; i < timing_config->ch_cnt; i++) { 1233 if (tmp0 | tmp1) 1234 mmio_setbits_32(CTL_REG(i, 305), 1 << 16); 1235 if (tmp0) >>> CID 1368413: Control flow issues (DEADCODE) >>> Execution cannot reach this statement: "mmio_setbits_32(4289200128U...". 1236 mmio_setbits_32(CTL_REG(i, 70), tmp0); 1237 if (tmp1) 1238 mmio_setbits_32(CTL_REG(i, 71), tmp1); 1239 } 1240 #endif 1241 } ** CID 1367555: Integer handling issues (INCOMPATIBLE_CAST) ________________________________________________________________________________________________________ *** CID 1367555: Integer handling issues (INCOMPATIBLE_CAST) /dev/cb-build/coreboot-coverity.0/AMD_GARDENIA/agesa/PspBaseLib.c: 326 in UpdataPspDirCheckSum() 320 321 VOID 322 UpdataPspDirCheckSum ( 323 IN OUT PSP_DIRECTORY *PspDir 324 ) 325 { >>> CID 1367555: Integer handling issues (INCOMPATIBLE_CAST) >>> Pointer "&PspDir->Header.TotalEntries" points to an object whose effective type is "unsigned long" (32 bits, unsigned) but is dereferenced as a narrower "unsigned short" (16 bits, unsigned). This may lead to unexpected results depending on machine endianness. 326 PspDir->Header.Checksum = Fletcher32 ((UINT16 *) &PspDir->Header.TotalEntries, \ 327 (sizeof (PSP_DIRECTORY_HEADER) - OFFSET_OF (PSP_DIRECTORY_HEADER, TotalEntries) + PspDir->Header.TotalEntries * sizeof (PSP_DIRECTORY_ENTRY)) / 2); 328 } 329 330 /** 331 Check if PSP device is present ** CID 1366397: Control flow issues (DEADCODE) /src/drivers/spi/spi_flash.c: 312 in __spi_flash_probe() ________________________________________________________________________________________________________ *** CID 1366397: Control flow issues (DEADCODE) /src/drivers/spi/spi_flash.c: 312 in __spi_flash_probe() 306 for (i = 0; i < sizeof(idcode); i++) 307 printk(BIOS_SPEW, "%02x ", idcode[i]); 308 printk(BIOS_SPEW, "\n"); 309 } 310 311 /* count the number of continuation bytes */ >>> CID 1366397: Control flow issues (DEADCODE) >>> Execution cannot reach the expression "*idp == 127" inside this statement: "for ((shift = 0) , (idp = i...". 312 for (shift = 0, idp = idcode; shift < IDCODE_CONT_LEN && *idp == 0x7f; 313 ++shift, ++idp) 314 continue; 315 316 printk(BIOS_INFO, "Manufacturer: %02x\n", *idp); 317 ** CID 1365976: (CONSTANT_EXPRESSION_RESULT) /src/soc/rockchip/rk3399/clock.c: 680 in rkclk_i2c_clock_for_bus() /src/soc/rockchip/rk3399/clock.c: 684 in rkclk_i2c_clock_for_bus() /src/soc/rockchip/rk3399/clock.c: 688 in rkclk_i2c_clock_for_bus() ________________________________________________________________________________________________________ *** CID 1365976: (CONSTANT_EXPRESSION_RESULT) /src/soc/rockchip/rk3399/clock.c: 680 in rkclk_i2c_clock_for_bus() 674 case 4: 675 write32(&pmucru_ptr->pmucru_clksel[3], 676 PMU_I2C_CLK_REG_VALUE(4, src_clk_div)); 677 break; 678 case 5: 679 write32(&cru_ptr->clksel_con[61], >>> CID 1365976: (CONSTANT_EXPRESSION_RESULT) >>> "((65280 /* (I2C_DIV_CON_MASK << CLK_I2C5_DIV_CON_SHIFT) | (CLK_I2C_PLL_SEL_MASK << CLK_I2C5_PLL_SEL_SHIFT) */) | ((src_clk_div - 1 << CLK_I2C5_DIV_CON_SHIFT) | (32768 /* CLK_I2C_PLL_SEL_GPLL << CLK_I2C5_PLL_SEL_SHIFT */))) << 16" is 0xffffffffff000000 regardless of the values of its operands. This occurs as the bitwise first operand of "|". 680 I2C_CLK_REG_VALUE(5, src_clk_div)); 681 break; 682 case 6: 683 write32(&cru_ptr->clksel_con[62], 684 I2C_CLK_REG_VALUE(6, src_clk_div)); 685 break; /src/soc/rockchip/rk3399/clock.c: 684 in rkclk_i2c_clock_for_bus() 678 case 5: 679 write32(&cru_ptr->clksel_con[61], 680 I2C_CLK_REG_VALUE(5, src_clk_div)); 681 break; 682 case 6: 683 write32(&cru_ptr->clksel_con[62], >>> CID 1365976: (CONSTANT_EXPRESSION_RESULT) >>> "((65280 /* (I2C_DIV_CON_MASK << CLK_I2C6_DIV_CON_SHIFT) | (CLK_I2C_PLL_SEL_MASK << CLK_I2C6_PLL_SEL_SHIFT) */) | ((src_clk_div - 1 << CLK_I2C6_DIV_CON_SHIFT) | (32768 /* CLK_I2C_PLL_SEL_GPLL << CLK_I2C6_PLL_SEL_SHIFT */))) << 16" is 0xffffffffff000000 regardless of the values of its operands. This occurs as the bitwise first operand of "|". 684 I2C_CLK_REG_VALUE(6, src_clk_div)); 685 break; 686 case 7: 687 write32(&cru_ptr->clksel_con[63], 688 I2C_CLK_REG_VALUE(7, src_clk_div)); 689 break; /src/soc/rockchip/rk3399/clock.c: 688 in rkclk_i2c_clock_for_bus() 682 case 6: 683 write32(&cru_ptr->clksel_con[62], 684 I2C_CLK_REG_VALUE(6, src_clk_div)); 685 break; 686 case 7: 687 write32(&cru_ptr->clksel_con[63], >>> CID 1365976: (CONSTANT_EXPRESSION_RESULT) >>> "((65280 /* (I2C_DIV_CON_MASK << CLK_I2C7_DIV_CON_SHIFT) | (CLK_I2C_PLL_SEL_MASK << CLK_I2C7_PLL_SEL_SHIFT) */) | ((src_clk_div - 1 << CLK_I2C7_DIV_CON_SHIFT) | (32768 /* CLK_I2C_PLL_SEL_GPLL << CLK_I2C7_PLL_SEL_SHIFT */))) << 16" is 0xffffffffff000000 regardless of the values of its operands. This occurs as the bitwise first operand of "|". 688 I2C_CLK_REG_VALUE(7, src_clk_div)); 689 break; 690 case 8: 691 write32(&pmucru_ptr->pmucru_clksel[2], 692 PMU_I2C_CLK_REG_VALUE(8, src_clk_div)); 693 break; ** CID 1365730: (BUFFER_SIZE) /src/mainboard/google/eve/romstage.c: 41 in mainboard_memory_init_params() /src/mainboard/google/eve/romstage.c: 42 in mainboard_memory_init_params() /src/mainboard/google/poppy/romstage.c: 43 in mainboard_memory_init_params() /src/mainboard/google/poppy/romstage.c: 44 in mainboard_memory_init_params() ________________________________________________________________________________________________________ *** CID 1365730: (BUFFER_SIZE) /src/mainboard/google/eve/romstage.c: 41 in mainboard_memory_init_params() 35 { 1, 0, 5, 4, 2, 3, 7, 6 } }; 36 /* Rcomp resistor */ 37 const u16 rcomp_resistor[] = { 200, 81, 162 }; 38 /* Rcomp target */ 39 const u16 rcomp_target[] = { 100, 40, 40, 23, 40 }; 40 >>> CID 1365730: (BUFFER_SIZE) >>> You might overrun the 12 byte destination string "mem_cfg->DqByteMapCh0" by writing the maximum 24 bytes from "dq_map". 41 memcpy(&mem_cfg->DqByteMapCh0, dq_map, sizeof(dq_map)); 42 memcpy(&mem_cfg->DqsMapCpu2DramCh0, dqs_map, sizeof(dqs_map)); 43 memcpy(&mem_cfg->RcompResistor, rcomp_resistor, sizeof(rcomp_resistor)); 44 memcpy(&mem_cfg->RcompTarget, rcomp_target, sizeof(rcomp_target)); 45 46 mem_cfg->MemorySpdPtr00 = mainboard_get_spd_data(); 47 mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; 48 mem_cfg->MemorySpdDataLen = SPD_LEN; /src/mainboard/google/eve/romstage.c: 42 in mainboard_memory_init_params() 36 /* Rcomp resistor */ 37 const u16 rcomp_resistor[] = { 200, 81, 162 }; 38 /* Rcomp target */ 39 const u16 rcomp_target[] = { 100, 40, 40, 23, 40 }; 40 41 memcpy(&mem_cfg->DqByteMapCh0, dq_map, sizeof(dq_map)); >>> CID 1365730: (BUFFER_SIZE) >>> You might overrun the 8 byte destination string "mem_cfg->DqsMapCpu2DramCh0" by writing the maximum 16 bytes from "dqs_map". 42 memcpy(&mem_cfg->DqsMapCpu2DramCh0, dqs_map, sizeof(dqs_map)); 43 memcpy(&mem_cfg->RcompResistor, rcomp_resistor, sizeof(rcomp_resistor)); 44 memcpy(&mem_cfg->RcompTarget, rcomp_target, sizeof(rcomp_target)); 45 46 mem_cfg->MemorySpdPtr00 = mainboard_get_spd_data(); 47 mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; 48 mem_cfg->MemorySpdDataLen = SPD_LEN; /src/mainboard/google/poppy/romstage.c: 43 in mainboard_memory_init_params() 37 }; 38 /* Rcomp resistor */ 39 const u16 rcomp_resistor[] = { 200, 81, 162 }; 40 /* Rcomp target */ 41 const u16 rcomp_target[] = { 100, 40, 40, 23, 40 }; 42 >>> CID 1365730: (BUFFER_SIZE) >>> You might overrun the 12 byte destination string "mem_cfg->DqByteMapCh0" by writing the maximum 24 bytes from "dq_map". 43 memcpy(&mem_cfg->DqByteMapCh0, dq_map, sizeof(dq_map)); 44 memcpy(&mem_cfg->DqsMapCpu2DramCh0, dqs_map, sizeof(dqs_map)); 45 memcpy(&mem_cfg->RcompResistor, rcomp_resistor, sizeof(rcomp_resistor)); 46 memcpy(&mem_cfg->RcompTarget, rcomp_target, sizeof(rcomp_target)); 47 48 mem_cfg->MemorySpdPtr00 = mainboard_get_spd_data(); 49 mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; 50 mem_cfg->MemorySpdDataLen = SPD_LEN; /src/mainboard/google/poppy/romstage.c: 44 in mainboard_memory_init_params() 38 /* Rcomp resistor */ 39 const u16 rcomp_resistor[] = { 200, 81, 162 }; 40 /* Rcomp target */ 41 const u16 rcomp_target[] = { 100, 40, 40, 23, 40 }; 42 43 memcpy(&mem_cfg->DqByteMapCh0, dq_map, sizeof(dq_map)); >>> CID 1365730: (BUFFER_SIZE) >>> You might overrun the 8 byte destination string "mem_cfg->DqsMapCpu2DramCh0" by writing the maximum 16 bytes from "dqs_map". 44 memcpy(&mem_cfg->DqsMapCpu2DramCh0, dqs_map, sizeof(dqs_map)); 45 memcpy(&mem_cfg->RcompResistor, rcomp_resistor, sizeof(rcomp_resistor)); 46 memcpy(&mem_cfg->RcompTarget, rcomp_target, sizeof(rcomp_target)); 47 48 mem_cfg->MemorySpdPtr00 = mainboard_get_spd_data(); 49 mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; 50 mem_cfg->MemorySpdDataLen = SPD_LEN; ** CID 1365389: (OVERRUN) /src/mainboard/google/eve/romstage.c: 41 in mainboard_memory_init_params() /src/mainboard/google/poppy/romstage.c: 43 in mainboard_memory_init_params() ________________________________________________________________________________________________________ *** CID 1365389: (OVERRUN) /src/mainboard/google/eve/romstage.c: 41 in mainboard_memory_init_params() 35 { 1, 0, 5, 4, 2, 3, 7, 6 } }; 36 /* Rcomp resistor */ 37 const u16 rcomp_resistor[] = { 200, 81, 162 }; 38 /* Rcomp target */ 39 const u16 rcomp_target[] = { 100, 40, 40, 23, 40 }; 40 >>> CID 1365389: (OVERRUN) >>> Overrunning array "mem_cfg->DqByteMapCh0" of 12 bytes by passing it to a function which accesses it at byte offset 23 using argument "24UL". [Note: The source code implementation of the function has been overridden by a builtin model.] 41 memcpy(&mem_cfg->DqByteMapCh0, dq_map, sizeof(dq_map)); 42 memcpy(&mem_cfg->DqsMapCpu2DramCh0, dqs_map, sizeof(dqs_map)); 43 memcpy(&mem_cfg->RcompResistor, rcomp_resistor, sizeof(rcomp_resistor)); 44 memcpy(&mem_cfg->RcompTarget, rcomp_target, sizeof(rcomp_target)); 45 46 mem_cfg->MemorySpdPtr00 = mainboard_get_spd_data(); 47 mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; 48 mem_cfg->MemorySpdDataLen = SPD_LEN; /src/mainboard/google/poppy/romstage.c: 43 in mainboard_memory_init_params() 37 }; 38 /* Rcomp resistor */ 39 const u16 rcomp_resistor[] = { 200, 81, 162 }; 40 /* Rcomp target */ 41 const u16 rcomp_target[] = { 100, 40, 40, 23, 40 }; 42 >>> CID 1365389: (OVERRUN) >>> Overrunning array "mem_cfg->DqByteMapCh0" of 12 bytes by passing it to a function which accesses it at byte offset 23 using argument "24UL". [Note: The source code implementation of the function has been overridden by a builtin model.] 43 memcpy(&mem_cfg->DqByteMapCh0, dq_map, sizeof(dq_map)); 44 memcpy(&mem_cfg->DqsMapCpu2DramCh0, dqs_map, sizeof(dqs_map)); 45 memcpy(&mem_cfg->RcompResistor, rcomp_resistor, sizeof(rcomp_resistor)); 46 memcpy(&mem_cfg->RcompTarget, rcomp_target, sizeof(rcomp_target)); 47 48 mem_cfg->MemorySpdPtr00 = mainboard_get_spd_data(); 49 mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; 50 mem_cfg->MemorySpdDataLen = SPD_LEN; /src/mainboard/intel/kblrvp/romstage.c: 38 in mainboard_memory_init_params() 32 FSP_M_CONFIG *mem_cfg; 33 mem_cfg = &mupd->FspmConfig; 34 u8 spd_index = (get_board_id() >> 5) & 0x7; 35 36 printk(BIOS_INFO, "SPD index %d\n", spd_index); 37 >>> CID 1365389: (OVERRUN) >>> Overrunning array "mem_cfg->DqByteMapCh0" of 12 bytes by passing it to a function which accesses it at byte offset 23. 38 mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0); 39 mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0); 40 mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); 41 mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); 42 43 if (IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP3)) { ** CID 1365388: (OVERRUN) /src/mainboard/google/eve/romstage.c: 42 in mainboard_memory_init_params() /src/mainboard/google/poppy/romstage.c: 44 in mainboard_memory_init_params() ________________________________________________________________________________________________________ *** CID 1365388: (OVERRUN) /src/mainboard/google/eve/romstage.c: 42 in mainboard_memory_init_params() 36 /* Rcomp resistor */ 37 const u16 rcomp_resistor[] = { 200, 81, 162 }; 38 /* Rcomp target */ 39 const u16 rcomp_target[] = { 100, 40, 40, 23, 40 }; 40 41 memcpy(&mem_cfg->DqByteMapCh0, dq_map, sizeof(dq_map)); >>> CID 1365388: (OVERRUN) >>> Overrunning array "mem_cfg->DqsMapCpu2DramCh0" of 8 bytes by passing it to a function which accesses it at byte offset 15 using argument "16UL". [Note: The source code implementation of the function has been overridden by a builtin model.] 42 memcpy(&mem_cfg->DqsMapCpu2DramCh0, dqs_map, sizeof(dqs_map)); 43 memcpy(&mem_cfg->RcompResistor, rcomp_resistor, sizeof(rcomp_resistor)); 44 memcpy(&mem_cfg->RcompTarget, rcomp_target, sizeof(rcomp_target)); 45 46 mem_cfg->MemorySpdPtr00 = mainboard_get_spd_data(); 47 mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; 48 mem_cfg->MemorySpdDataLen = SPD_LEN; /src/mainboard/google/poppy/romstage.c: 44 in mainboard_memory_init_params() 38 /* Rcomp resistor */ 39 const u16 rcomp_resistor[] = { 200, 81, 162 }; 40 /* Rcomp target */ 41 const u16 rcomp_target[] = { 100, 40, 40, 23, 40 }; 42 43 memcpy(&mem_cfg->DqByteMapCh0, dq_map, sizeof(dq_map)); >>> CID 1365388: (OVERRUN) >>> Overrunning array "mem_cfg->DqsMapCpu2DramCh0" of 8 bytes by passing it to a function which accesses it at byte offset 15 using argument "16UL". [Note: The source code implementation of the function has been overridden by a builtin model.] 44 memcpy(&mem_cfg->DqsMapCpu2DramCh0, dqs_map, sizeof(dqs_map)); 45 memcpy(&mem_cfg->RcompResistor, rcomp_resistor, sizeof(rcomp_resistor)); 46 memcpy(&mem_cfg->RcompTarget, rcomp_target, sizeof(rcomp_target)); 47 48 mem_cfg->MemorySpdPtr00 = mainboard_get_spd_data(); 49 mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; 50 mem_cfg->MemorySpdDataLen = SPD_LEN; /src/mainboard/intel/kblrvp/romstage.c: 39 in mainboard_memory_init_params() 33 mem_cfg = &mupd->FspmConfig; 34 u8 spd_index = (get_board_id() >> 5) & 0x7; 35 36 printk(BIOS_INFO, "SPD index %d\n", spd_index); 37 38 mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0); >>> CID 1365388: (OVERRUN) >>> Overrunning array "mem_cfg->DqsMapCpu2DramCh0" of 8 bytes by passing it to a function which accesses it at byte offset 15. 39 mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0); 40 mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); 41 mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); 42 43 if (IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP3)) { 44 struct region_device spd_rdev; ** CID 1365384: Integer handling issues (DIVIDE_BY_ZERO) /3rdparty/chromeec/driver/temp_sensor/thermistor_ncp15wb.c: 150 in thermistor_linear_interpolate() ________________________________________________________________________________________________________ *** CID 1365384: Integer handling issues (DIVIDE_BY_ZERO) /3rdparty/chromeec/driver/temp_sensor/thermistor_ncp15wb.c: 150 in thermistor_linear_interpolate() 144 * 1. mv_per_deg_c = (v_high - v_low) / (t_high - t_low) 145 * 2. num_steps = (v_high - mv) / mv_per_deg_c 146 * 3. result = t_low + num_steps 147 * 148 * Combine #1 and #2 to mitigate precision loss due to integer division. 149 */ >>> CID 1365384: Integer handling issues (DIVIDE_BY_ZERO) >>> In expression "(v_high - mv) * (t_high - t_low) / (v_high - v_low)", division by expression "v_high - v_low" which may be zero has undefined behavior. 150 num_steps = ((v_high - mv) * (t_high - t_low)) / (v_high - v_low); 151 return t_low + num_steps; ** CID 1363355: (SIZEOF_MISMATCH) /src/drivers/intel/fsp2_0/upd_display.c: 37 in fspm_display_arch_params() /src/drivers/intel/fsp2_0/upd_display.c: 40 in fspm_display_arch_params() ________________________________________________________________________________________________________ *** CID 1363355: (SIZEOF_MISMATCH) /src/drivers/intel/fsp2_0/upd_display.c: 37 in fspm_display_arch_params() 31 { 32 /* Display the architectural parameters for MemoryInit */ 33 printk(BIOS_SPEW, "Architectural UPD values for MemoryInit at: 0x%p\n", 34 new); 35 fsp_display_upd_value("Revision", sizeof(old->Revision), 36 old->Revision, new->Revision); >>> CID 1363355: (SIZEOF_MISMATCH) >>> Passing argument "old->NvsBufferPtr" of type "void * const" and argument "4UL /* sizeof (old->NvsBufferPtr) */" to function "fsp_display_upd_value" is suspicious. 37 fsp_display_upd_value("NvsBufferPtr", sizeof(old->NvsBufferPtr), 38 (uintptr_t)old->NvsBufferPtr, 39 (uintptr_t)new->NvsBufferPtr); 40 fsp_display_upd_value("StackBase", sizeof(old->StackBase), 41 (uintptr_t)old->StackBase, 42 (uintptr_t)new->StackBase); /src/drivers/intel/fsp2_0/upd_display.c: 40 in fspm_display_arch_params() 34 new); 35 fsp_display_upd_value("Revision", sizeof(old->Revision), 36 old->Revision, new->Revision); 37 fsp_display_upd_value("NvsBufferPtr", sizeof(old->NvsBufferPtr), 38 (uintptr_t)old->NvsBufferPtr, 39 (uintptr_t)new->NvsBufferPtr); >>> CID 1363355: (SIZEOF_MISMATCH) >>> Passing argument "old->StackBase" of type "void * const" and argument "4UL /* sizeof (old->StackBase) */" to function "fsp_display_upd_value" is suspicious. 40 fsp_display_upd_value("StackBase", sizeof(old->StackBase), 41 (uintptr_t)old->StackBase, 42 (uintptr_t)new->StackBase); 43 fsp_display_upd_value("StackSize", sizeof(old->StackSize), 44 old->StackSize, new->StackSize); 45 fsp_display_upd_value("BootLoaderTolumSize", ** CID 1362811: Resource leaks (RESOURCE_LEAK) /src/southbridge/amd/sr5650/sr5650.c: 804 in add_ivrs_device_entries() ________________________________________________________________________________________________________ *** CID 1362811: Resource leaks (RESOURCE_LEAK) /src/southbridge/amd/sr5650/sr5650.c: 804 in add_ivrs_device_entries() 798 sibling = sibling->sibling) 799 add_ivrs_device_entries(dev, sibling, depth + 1, 800 depth, root_level, current, length); 801 802 if (depth == 0) 803 free(root_level); >>> CID 1362811: Resource leaks (RESOURCE_LEAK) >>> Returning without freeing "root_level" leaks the storage that it points to. 804 } 805 806 unsigned long acpi_fill_mcfg(unsigned long current) 807 { 808 struct resource *res; 809 resource_t mmconf_base = EXT_CONF_BASE_ADDRESS; ** CID 1362592: Null pointer dereferences (NULL_RETURNS) ________________________________________________________________________________________________________ *** CID 1362592: Null pointer dereferences (NULL_RETURNS) /src/drivers/generic/max98357a/max98357a.c: 41 in max98357a_fill_ssdt() 35 struct acpi_dp *dp; 36 37 if (!dev->enabled || !config) 38 return; 39 40 /* Device */ >>> CID 1362592: Null pointer dereferences (NULL_RETURNS) >>> Dereferencing a pointer that might be null "acpi_device_scope(dev)" when calling "acpigen_write_scope". 41 acpigen_write_scope(acpi_device_scope(dev)); 42 acpigen_write_device(acpi_device_name(dev)); 43 acpigen_write_name_string("_HID", MAX98357A_ACPI_HID); 44 acpigen_write_name_integer("_UID", 0); 45 acpigen_write_name_string("_DDN", dev->chip_ops->name); 46 acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u2389337.ct.sendgrid.net/wf/click?upn=08onrYu34A-2BWcWUl-2F-2BfV0V0… To manage Coverity Scan email notifications for "coreboot(a)coreboot.org", click https://u2389337.ct.sendgrid.net/wf/click?upn=08onrYu34A-2BWcWUl-2F-2BfV0V0…

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Not enough MMIO resources for SR-IOV - KGPE-D16
by Taiidan＠gmx.com 06 Apr '17

06 Apr '17

I am trying to enable SR-IOV on my KGPE-D16 with an Intel 82576L PCI-e adapter The base ports report ARIFWD+ in DevCap2, so I think I am good to go with ARI. I receive an error of "not enough MMIO resources for SR-IOV" What could be causing this? sudo modprobe -r igb sudo modprobe igb max_vfs=2 dmesg | tail [ 5408.632331] igb 0000:0a:00.0: Using MSI-X interrupts. 8 rx queue(s), 8 tx queue(s) [ 5408.635908] igb 0000:0a:00.1: Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface. [ 5408.636061] igb 0000:0a:00.1: not enough MMIO resources for SR-IOV [ 5408.641171] igb 0000:0a:00.0 enp10s0f0: renamed from eth0 [ 5408.836149] igb 0000:0a:00.1: added PHC on eth0 [ 5408.836152] igb 0000:0a:00.1: Intel(R) Gigabit Ethernet Network Connection [ 5408.836155] igb 0000:0a:00.1: eth0: (PCIe:2.5Gb/s:Width x4) 00:e0:ed:23:59:29 [ 5408.836158] igb 0000:0a:00.1: eth0: PBA No: Unknown [ 5408.836160] igb 0000:0a:00.1: Using MSI-X interrupts. 8 rx queue(s), 8 tx queue(s) [ 5408.848492] igb 0000:0a:00.1 enp10s0f1: renamed from eth0

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Do you use FILO payload bootloader??
by qma ster 06 Apr '17

06 Apr '17

Here is how FILO 0.6.0 is booting: ahci: Found SATA controller 00:11.00 (1022:7801) <--- this is AMD SATA AHCI controller, built-in inside Bolton A76M FCH Southbridge of Lenovo G505S ahci: ATA drive on port #1. ata: Identified [my 1TB HDD drive model here] ahci: ATAPI drive on port #2. atapi: Identified [my DVD drive model here] ERROR: No such CMOS option (boot_devices) Then it shows FILO screen with " root_dev = unset " message and FILO command line === QUESTION === Please could you give some good examples about how to use FILO ? Do I have to set boot_devices in CMOS through nvramcui payload, or it is possible to choose that root_dev in FILO - if yes, how? I tried some random commands like filo> kernel hda:/vmlinuz but it tells: Disk read error dev=1 drive=0 sector=0 Disk read error dev=1 drive=0 sector=2 Disk read error dev=1 drive=0 sector=2 Disk read error dev=1 drive=0 sector=128 Disk read error dev=1 drive=0 sector=16 Disk read error dev=1 drive=0 sector=64 Disk read error dev=1 drive=0 sector=0 Disk read error dev=1 drive=0 sector=64 Disk read error dev=1 drive=0 sector=0 Disk read error dev=1 drive=0 sector=0 Unknown filesystem type. Error 15: Filo not found. https://www.coreboot.org/FILO is too basic - e.g. does not tell how to check the list of available devices. When I run "probe" command it only tells 6 messages "IDE channel X not found" (with X changing 0,0,1,1,2,2,3,3) - does not show SATA drive, despite I know that it successfully initialized, because it output its model and brand Please give any real world FILO usage examples with a modern Linux, it will help a lot! Best regards, qmastery

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Help on debug, add a new mainboard.
by Kory Maincent 06 Apr '17

06 Apr '17

Hi everyone, I would like to learn how to add a new mainboard to coreboot. I have a Fujitsu D2990-A1, with chipset intel H61, sandybridge and a Superio Nuvoton NCT5571D. I use the autoport tools to generate the files. I know that I have to change them to add new configuration but I don't really know how. Can you help me to get started with the debug part or to give me some advice about it. I have downloaded the Embedde Firmware Solution eBook to begin with. Thanks Kory This is my debug output USB coreboot-coreboot-unknown Wed Apr 5 15:19:21 UTC 2017 romstage starting... Setting up static southbridge registers... done. Disabling Watchdog reboot... done. Setting up static northbridge registers... done. Graphics not supported by this CPU/chipset. Back from sandybridge_early_initialization() SMBus controller enabled. CPU id(206a7): Intel(R) Core(TM) i7-2600 CPU @ 3.40GHz AES supported, TXT supported, VT supported PCH type: H61, device id: 1c5c, rev id 5 Intel ME early init WARNING: ME has bad firmware ME: Requested 63MB UMA Starting native Platform init CBFS: 'Master Header Locator' located CBFS at [200100:3fffc0) CBFS: Locating 'mrc.cache' CBFS: Found @ offset 1fec0 size 10000 find_current_mrc_cache_local: No valid MRC cache found. Row addr bits : 15 Column addr bits : 10 Number of ranks : 2 DIMM Capacity : 4096 MB CAS latencies : 6 7 8 9 10 tCKmin : 1.500 ns tAAmin : 13.125 ns tWRmin : 15.000 ns tRCDmin : 13.125 ns tRRDmin : 6.000 ns tRPmin : 13.125 ns tRASmin : 36.000 ns tRCmin : 49.125 ns tRFCmin : 160.000 ns tWTRmin : 7.500 ns tRTPmin : 7.500 ns tFAWmin : 30.000 ns channel[1] rankmap = 0x3 Starting RAM training (0). PLL busy... done in 10 us MCU frequency is set at : 666 MHz Selected DRAM frequency: 666 MHz Minimum CAS latency : 9T Selected CAS latency : 9T Selected CWL latency : 7T Selected tRCD : 9T Selected tRP : 9T Selected tRAS : 24T Selected tWR : 10T Selected tFAW : 20T Selected tRRD : 4T Selected tRTP : 5T Selected tWTR : 5T Selected tRFC : 107T Done dimm mapping Update PCI-E configuration space: PCI(0, 0, 0)[a0] = 0 PCI(0, 0, 0)[a4] = 1 PCI(0, 0, 0)[bc] = 8a800000 PCI(0, 0, 0)[a8] = 71900000 PCI(0, 0, 0)[ac] = 1 PCI(0, 0, 0)[b8] = 80000000 PCI(0, 0, 0)[b0] = 80800000 PCI(0, 0, 0)[b4] = 80800000 PCI(0, 0, 0)[7c] = 7f PCI(0, 0, 0)[70] = fc100000 PCI(0, 0, 0)[74] = 0 PCI(0, 0, 0)[78] = fc100c00 Done memory map Done io registers Done jedec reset Done MRS commands t123: 1912, 9120, 500 ME: FW Partition Table : BAD ME: Bringup Loader Failure : YES ME: Firmware Init Complete : YES ME: Manufacturing Mode : YES ME: Boot Options Present : YES ME: Update In Progress : YES ¡8—d$ ME: Current Operation State : M0 without UMA but with error ME: Current Operation Mode : Reset ME: Error Code : <NULL> ME: Progress Phase : Soft Temporary Disable ME: Power Management Event : uKernel Phase ME: Progress Phase State : Unknown 0xff ME: Wrong mode : 15 ME: HFS error : 15 ME: FWS2: 0xffffffff ME: Bist in progress: 0x1 ME: ICC Status : 0x3 ME: Invoke MEBx : 0x1 ME: CPU replaced : 0x1 ME: MBP ready : 0x1 ME: MFS failure : 0x1 ME: Warm reset req : 0x1 ME: CPU repl valid : 0x1 ME: (Reserved) : 0x3 ME: FW update req : 0x1 ME: (Reserved) : 0xf ME: Current state : 0xff ME: Current PM event: 0xf ME: Progress code : 0xf CPU was replaced & warm reset required...

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Re: [coreboot] VGA and Graphics
by Nico Huber 05 Apr '17

05 Apr '17

On 05.04.2017 17:03, Zoran Stojsavljevic wrote: > To Coreboot, > > http://www.uefi.org/sites/default/files/resources/UPFS11_P4_UEFI_GOP_AMD.pdf > > Please, read about GOP, and what GOP suppose to be. > > So, GOP actually need to replace vBIOS, VBT, legacy INT 10H, and complete > VBE 3.0 standard. Why (I have no idea what INTEL does with GOP and how it > implements it) it is not done in this fashion...?! At least this is my > impression how this should be done. no, no, no, no. Since VBT is not related to the concept of a Video BIOS or any standard (how many people does it need to convince you? :-), it cannot be replaced by something (GOP) that continues this standards story. Maybe this helps you to untangle this: When the VBT was invented, it might have been named after Intel's Video BIOS because that was its first consumer. However the name is or has become unrelated to its func- tion. If somebody would come up with a name for the VBT, looking at what it is today, he might call it Intel Graphics Driver Configuration Table (IGDT). The acronym IGDT looks much different from VBE, no temptation to see them related. Also, why should GOP replace IGDT and reinvent how Intel develops its graphics drivers? GOP is just about pre-OS environ- ments (cross-vendor), while IGDT is common to all of Intel's graphics drivers. >From another perspective: IGDT contains proprietary settings for Intel silicon, close to register level. VBE is, at its core, about high-level framebuffer (data in RAM) formats. Nico > > I'll continue to investigate. > > Thank you, > Zoran > > On Wed, Apr 5, 2017 at 4:54 PM, Matt DeVillier <matt.devillier(a)gmail.com> > wrote: > >> On Tue, Apr 4, 2017 at 10:12 PM, Zoran Stojsavljevic <zoran. >> stojsavljevic(a)gmail.com> wrote: >> >>> Hello Matt, >>> >>> Pretty sure there is NO Option ROM, vBIOS and INT10H. Why INTEL for GOP >>> uses VBT is point of debate. Probably just reduced functionality up to >>> 1280x1024. So they have VBT to support BIOS phase GOP GFX. Only! >>> >> >> From what I can tell, it's mainly used to provide the output connector >> types/mapping to the GOP driver, as well as level shifting etc. >> >> >>> >>> But I am also 100% sure neither GOP, neither VBT survives post BIOS >>> phase. It is out of mind to use VBT for WUXGA, or 1080p, or 4K displays, >>> don't you agree? The detected GFX I/F are passed to Linux as Run Time info >>> (via HOB). Then Linux brings from scratch GFX, using its own, modern I/Fs. >>> And ports appropriate drivers to existing GFX info from HOB. >>> >> >> The VBT data is used by both the Linux and Windows display drivers (via >> the OpRegion ACPI structure), and the latter will give you a nice black >> screen if your VBT is missing or incorrectly configured. As I noted above, >> it appears to be used more for output/pipe info than display modes (which >> are all generated from EDID, outside of standard VESA/CEA ones) >> >> On Tue, Apr 4, 2017 at 10:12 PM, Zoran Stojsavljevic < >> zoran.stojsavljevic(a)gmail.com> wrote: >> >>> Hello Matt, >>> >>> Pretty sure there is NO Option ROM, vBIOS and INT10H. Why INTEL for GOP >>> uses VBT is point of debate. Probably just reduced functionality up to >>> 1280x1024. So they have VBT to support BIOS phase GOP GFX. Only! >>> >>> But I am also 100% sure neither GOP, neither VBT survives post BIOS >>> phase. It is out of mind to use VBT for WUXGA, or 1080p, or 4K displays, >>> don't you agree? The detected GFX I/F are passed to Linux as Run Time info >>> (via HOB). Then Linux brings from scratch GFX, using its own, modern I/Fs. >>> And ports appropriate drivers to existing GFX info from HOB. >>> >>> Zoran >>> >>> On Tue, Apr 4, 2017 at 11:51 PM, Matt DeVillier <matt.devillier(a)gmail.com >>>> wrote: >>> >>>> >>>> >>>> On Tue, Apr 4, 2017 at 2:23 PM, Zoran Stojsavljevic < >>>> zoran.stojsavljevic(a)gmail.com> wrote: >>>> >>>>> Furthermore, let me tell you all that this is a mechanism to support >>>>> ONLY The Legacy BIOS (UEFI works ONLY with GOP, but this is another >>>>> dimension/discussion), and, to all of your knowledge (which I have no idea >>>>> how deep it is, I doubt), VBT table survives postmortem BIOS. By Linux, it >>>>> will be RELOCATED into much higher (over 1MB) 32bit protected mode memory >>>>> (addresses recalculated), and still use INT10H, using vBIOS (Option ROM, my >>>>> best guess) down there. >>>>> >>>>> >>>> no, the UEFI GOP driver needs the VBT to actually do anything. Look at >>>> any current PC UEFI firmware, or even x86 ChromeOS firmware, and you'll see >>>> they all use/contain a VBT still. >>>> >>> >>> >> > > >

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coreboot April 2017