coreboot May 2016

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Re: [coreboot] bootfail on my Mohon Peak CRB.
by 김유석 17 May '16

17 May '16

Dear Sir. Thank's your advise. I was solved this issue. The cause was "Image size". My spi flash is have a 16MByte size. and coreboot.rom's size is a 2MByte. And I was write from 0x00. But x86 is must write from bottom. I guess. *For example* case 1. coreboot image : 2MByte flash storage : 16MByte You must write start address is 0x00E00000(offset 14MByte) case 2. coreboot image : 8MByte flash storage : 16MByte You must write start address is 0x00800000(offset 8MByte) case 3. coreboot image : 16MByte flash storage : 16MByte You must write start address is 0x00000000(offset 0MByte) This time, coreboot work is very fine. Thank you. 2016-02-04 오후 11:02에 WANG FEI 이(가) 쓴 글: > *RANGELEY_POSTGOLD4_FSP_004_20150924.fd is the FSP binary, you can > rename it to FvFsp.bin and placed it to the path defined in coreboot, > ie, *`../intel/fsp/rangeley/Fv*, to generate coreboot image.* > > On Thu, Feb 4, 2016 at 5:19 AM, 김유석 <poplinux0(a)gmail.com > <mailto:poplinux0@gmail.com>> wrote: > > Dear Martin. > > Thank's your advise. > > I'm use the serial consol port. but can't see any message. > > Thank you. > > 2016-02-02 오후 9:18에 Martin Roth 이(가) 쓴 글: >> You might try a different video card. There's an issue in the >> video bios of the aspeed card that came with the mohon peak. >> >> martin >> On Tue, Feb 2, 2016 at 00:41 김유석 <poplinux0(a)gmail.com >> <mailto:poplinux0@gmail.com>> wrote: >> >> Dear sir. >> >> My ENV is see below. >> >> *EVB : Intel rangeley Mohon Peak CRB* >> >> >> This time, I was download the coreboot from git. >> >> poplinux@raw work $ > git clone >> http://review.coreboot.org/coreboot.git ./ >> poplinux@raw work $ > cd coreboot >> poplinux@raw coreboot $ > git submodule update --init --checkout >> >> Next, *run make menuconfig* and set-up to mohon peak CRB and >> save & exit >> >> *Mainboa**rd* >> Mainboard vendor (*Intel*) ---> >> Mainboard model (*Mohon Peak CRB*) ---> >> [ ] Configure defaults for the Intel FSP package >> ROM chip size (2048 KB (2 MB)) ---> >> (0x00200000) Size of CBFS filesystem in ROM >> () fmap description file in fmd format >> >> Next, I'm try to build core boot. >> >> poplinux@raw coreboot $ > make >> GEN generated/bootblock.ld >> CP bootblock/arch/x86/bootblock.ld >> LINK cbfs/fallback/bootblock.debug >> OBJCOPY cbfs/fallback/bootblock.elf >> OBJCOPY bootblock.raw.bin >> Checking out SeaBIOS revision >> 01a84bea2d28a19d2405c1ecac4bdef17683cc0c >> Switched to branch 'master' >> >> Performing operation on 'COREBOOT' region... >> Name Offset Type Size >> cbfs master header 0x0 cbfs header 32 >> fallback/romstage 0x80 stage 22684 >> cpu_microcode_blob.bin 0x5980 microcode 0 >> config 0x5a00 raw 127 >> revision 0x5ac0 raw 570 >> cmos_layout.bin 0x5d40 cmos_layout 1316 >> fallback/dsdt.aml 0x62c0 raw 7952 >> payload_config 0x8240 raw 1574 >> payload_revision 0x88c0 raw 237 >> (empty) 0x8a00 null 29848 >> mrc.cache 0xfec0 mrc_cache 65536 >> fallback/ramstage 0x1ff00 stage 46922 >> fallback/payload 0x2b6c0 payload 61122 >> (empty) 0x3a5c0 null 1856216 >> bootblock 0x1ff8c0 bootblock 1528 >> >> Finally, I'm got a coreboot image. >> >> >> poplinux@raw build $ > ls build/coreboot.rom >> build/coreboot.rom >> poplinux@raw build $ > ./build/cbfstool build/coreboot.rom >> print >> Performing operation on 'COREBOOT' region... >> Name Offset Type Size >> cbfs master header 0x0 cbfs header 32 >> fallback/romstage 0x80 stage 22684 >> cpu_microcode_blob.bin 0x5980 microcode 0 >> config 0x5a00 raw 127 >> revision 0x5ac0 raw 570 >> cmos_layout.bin 0x5d40 cmos_layout 1316 >> fallback/dsdt.aml 0x62c0 raw 7952 >> payload_config 0x8240 raw 1574 >> payload_revision 0x88c0 raw 237 >> (empty) 0x8a00 null 29848 >> mrc.cache 0xfec0 mrc_cache 65536 >> fallback/ramstage 0x1ff00 stage 46922 >> fallback/payload 0x2b6c0 payload 61122 >> (empty) 0x3a5c0 null 1856216 >> bootblock 0x1ff8c0 bootblock 1528 >> >> >> And I'm write image to my EVB using *ALL-100 Gang-writ**er*. >> spi flash's write *start address is set 0x00000000*. write it >> success. >> >> And I'm attach the flash memory to my EVB. >> >> And power-up the my EVB. But can't see any message on my >> monitor and serial port both. >> >> >> *Why did not display any message? ** >> **A**nd could you support correct configuration file for my EVB?* >> >> Thank you. >> >> >> >> >> >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> <mailto:coreboot@coreboot.org> >> http://www.coreboot.org/mailman/listinfo/coreboot >> > > > -- > coreboot mailing list: coreboot(a)coreboot.org > <mailto:coreboot@coreboot.org> > http://www.coreboot.org/mailman/listinfo/coreboot > >

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Modifying T60 chassis to better get at the boot rom
by David Griffith 17 May '16

17 May '16

I managed to brick my Thinkpad T60 while experimenting with Coreboot, so I had to completely extract the main board to get at the boot ROM. I was pleased to notice that I could easily cut out a small piece of the inner chassis to allow me to de-brick the laptop again without taking it completely apart again. Here are some pictures of the laptop with the keyboard and wrist rest off showing how easily I can get at the ROM now. https://www.flickr.com/photos/32548582@N02/albums/72157668418115386 If it's not already obvious, surgery like this should only be performed when all boards have been removed from the inner chassis. -- David Griffith dave(a)661.org A: Because it fouls the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing in e-mail?

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New custom board (Intel Baytrail FSP based on Valley Island reference design)
by Naveed Ghori 17 May '16

17 May '16

Hi, I am bringing up a new board using coreboot as the bios. Hardware: - Based on Intel Valley Island design (which has TPE) - No TPM Coreboot: - Source coreboot 4.4 release - Using code based on Bayley bay (Intel FSP) - FSP: Gold3 - Using a bios based on Valley Island for the non-coreboot sections The board boots, goes through romstage and then freezes early in the ramstage (before enabling any devices): see output below To me it seems there may be a hardware issue (new board, I am suspecting memory) but I thought I would ask as someone may have seen something similar. 1) Could the non coreboot part of the bios chip cause this. 2) Is there a way to check memory at the rom stage. 3) Is there any information on the memory map of the bios chip. 4) Is there a way to check other devices at the romstage or early ram stage. I have tried skipping the "Enumeratin busses" section but it just crashes at the next stage (I guess I cannot really expect ti to get very far without its busses). Note: I am new to coreboot and bios development in general. Any help, suggestion appreciated. Output Log: -------------------------------------- coreboot-099d78c-dirty Thu May 12 05:41:22 UTC 2016 romstage starting... RTC Init POST: 0x44 POST: 0x47 POST: 0x48 Starting the Intel FSP (early_init) PM1_STS = 0x100 PM1_CNT = 0x0 GEN_PMCON1 = 0x45008 prev_sleep_state = S5 Configure Default UPD Data PcdMrcInitSPDAddr1: 0xa0 (default) PcdMrcInitSPDAddr2: 0xa2 (default) PcdSataMode: 0x01 (set) PcdLpssSioEnablePciMode: 0x01 (default) PcdMrcInitMmioSize: 0x800 (default) PcdIgdDvmt50PreAlloc: 0x02 (default) PcdApertureSize: 0x02 (default) PcdGttSize: 0x02 (default) SerialDebugPortAddress: 0x3f8 (default) SerialDebugPortType: 0x01 (default) PcdMrcDebugMsg: 0x00 (default) PcdSccEnablePciMode: 0x01 (default) IgdRenderStandby: 0x00 (default) TxeUmaEnable: 0x00 (default) PcdOsSelection: 0x04 (default) PcdEMMC45DDR50Enabled: 0x01 (default) PcdEMMC45HS200Enabled: 0x00 (default) PcdEMMC45RetuneTimerValue: 0x08 (default) PcdEnableIgd: 0x00 (default) AutoSelfRefreshEnable: 0x00 (default) APTaskTimeoutCnt: 0x00 (default) GTT Size: 2 MB Tseg Size: 8 MB Aperture Size: 256 MB IGD Memory Size: 64 MB MMIO Size: 2048 MB MIPI/ISP: Disabled Sdio: Enabled Sdcard: Enabled SATA: Enabled SIO Dma 0: Enabled SIO I2C0: Enabled SIO I2C1: Enabled SIO I2C2: Enabled SIO I2C3: Enabled SIO I2C4: Enabled SIO I2C5: Enabled SIO I2C6: Enabled Azalia: Enabled SIO Dma1: Enabled Pwm0: Enabled Pwm1: Enabled Hsuart0: Enabled Hsuart1: Enabled Spi: Enabled Lpe: Disabled eMMC Mode: eMMC 4.5 SATA Mode: AHCI Xhci: Enabled CBFS: 'Master Header Locator' located CBFS at [100:1fffc0) CBFS: Locating 'mrc.cache' CBFS: Found @ offset fec0 size 10000 find_current_mrc_cache_local: No valid fast boot cache found. FSP MRC cache not present. POST: 0x92 POST: 0x4a romstage_main_continue status: 0 hob_list_ptr: 7ae20000 FSP Status: 0x0 PM1_STS = 0x101 PM1_CNT = 0x0 GEN_PMCON1 = 0x1001808 romstage_main_continue: prev_sleep_state = S0 Baytrail Chip Variant: Bay Trail-I (ISG/embedded) MRC v0.100 2 channels of DDR3 @ 1333MHz POST: 0x4b POST: 0x4c POST: 0x4d CBMEM: IMD: root @ 7adff000 254 entries. IMD: root @ 7adfec00 62 entries. POST: 0x4e POST: 0x4f CBFS: 'Master Header Locator' located CBFS at [100:1fffc0) CBFS: Locating 'fallback/ramstage' CBFS: Found @ offset 46380 size d5be coreboot-099d78c-dirty Thu May 12 05:41:22 UTC 2016 ramstage starting... POST: 0x39 Moving GDT to 7adfe9c0...ok POST: 0x80 POST: 0x70 BS: BS_PRE_DEVICE times (us): entry 0 run 1168 exit 0 POST: 0x71 CBFS: 'Master Header Locator' located CBFS at [100:1fffc0) CBFS: Locating 'cpu_microcode_blob.bin' CBFS: Found @ offset 1ff00 size 26400 microcode: sig=0x30679 pf=0x1 revision=0x901 CPUID: 00030679 Cores: 4 Revision ID: 11 Stepping: D0 msr(17) = 0000000090041743 msr(ce) = 0000060000001700 BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 30606 exit 0 POST: 0x72 Enumerating buses... Show all devs... Before device enumeration. Root Dev ---------------------------- Naveed Ghori | Lead Firmware & Driver Engineer DTI Group Ltd | Transit Security & Surveillance 31 Affleck Road, Perth Airport, Western Australia 6105, AU P +61 8 9373 2905,151 | F +61 8 9479 1190 | naveed.ghori(a)dti.com.au Visit our website www.dti.com.au<http://www.dti.com.au> The information contained in this email is confidential. If you receive this email in error, please inform DTI Group Ltd via the above contact details. If you are not the intended recipient, you may not use or disclose the information contained in this email or attachments.

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Re: [coreboot] coreboot with fsp hangs at post code 19 on Bayley Bay
by Zoran Stojsavljevic 17 May '16

17 May '16

Hello Kathappan, Did you try to (using BCT) to enable PCIe x1, at least PCIe0 and PCIe1 (the same size x1)? Does it work now? Thank you, Zoran On Fri, May 13, 2016 at 9:51 PM, Zoran Stojsavljevic < zoran.stojsavljevic(a)gmail.com> wrote: > Hello Kathappan, > > I need to look deeper into this area since I am not expert on FSP, but I > have some ideas what could be wrong. > > Several questions for you: > [1] Which BYT SoC you are using (example BYT-M N2807)? > [2] How many DDR3 channels (1 or 2) are you using in your design, and what > is the size of memory (most likely not a problem)? > [3] PCH. Do you have PCIe channels initialized/set in default soft straps > (you must have some, at least PCIe root port 0, and PCIe root port 1, as I > recalled)? <<==== IMPORTANT? > > Again, I need to think more about this, and I'll try to find some answers, > later... Please, try to see/discover [3] using BCT tool! > > Zoran > _______ > > On Fri, May 13, 2016 at 3:01 PM, Kathappan E < > Kathappan.E(a)lnttechservices.com> wrote: > >> Hi all, >> >> >> >> When I try coreboot on Bayley Bay platform along with fsp >> (BAYTRAIL_FSP_GOLD_004_22-MAY-2015), it is getting hang at post code 19. >> >> >> >> Also I tried with debug version fsp >> (BAYTRAIL_FSP_GOLD_004_22-MAY-2015_DEBUG) , it still at that point and >> below is the debug log. >> >> >> >> *Firmware Image*: Have used the 8 MB vendor bios and flashed the last 2 >> MB region(600000 to 7fffff) with coreboot image. >> >> >> >> *From the debug log*: coreboot gives the control to FSP binary routine( >> *FspInitApi*) and it is getting hang when trying to do PCH initialize( >> *PchMiscInit*) inside FSP part code. >> >> >> >> *POST 19 code info*: *EFI_COMPUTING_UNIT_CHIPSET* | >> *EFI_CU_CLOCK_PEI_INIT_ENTRY* ==> Clock Init PEIM Entry >> >> >> >> I have not seen the clock related setting available when customizing fsp >> binary using BCT. >> >> >> >> I tried to disable south cluster component such as EMMC,HSUART,SATA and >> SIO using BCT , it didn't help me. >> >> >> >> Can anyone please help me provide some inputs such as related below to >> proceed further debugging on it ? >> >> 1. Any other setting we can try out using BCT >> >> 2. About devices configuration to be initialized byPchMiscInit function. >> >> 3. Anything need to be cared/double checked from coreboot side in order >> to giving control to FspInitApi function. >> >> 4. Does pch straps settings may cause this since I am using upper 6 MB >> region flash data which is from vendor bios. >> >> 4. Please suggest anything on it. >> >> >> >> Thanks in advance, >> >> Kathappan >> >> >> >> <<<<<<<<<<<< Debug log Start >> >>>>>>>>>>>>>>> >> >> >> >> coreboot-coreboot-unknown Thu May 12 08:04:42 UTC 2016 romstage >> starting... >> >> RTC Init >> >> POST: 0x44 >> >> POST: 0x47 >> >> POST: 0x48 >> >> Starting the Intel FSP (early_init) >> >> PM1_STS = 0x0 PM1_CNT = 0x0 GEN_PMCON1 = 0x44000 >> >> prev_sleep_state = S5 >> >> Configure Default UPD Data >> >> PcdMrcInitSPDAddr1: 0xa0 (default) >> >> PcdMrcInitSPDAddr2: 0xa2 (default) >> >> PcdSataMode: 0x01 (set) >> >> PcdLpssSioEnablePciMode: 0x01 (default) >> >> PcdMrcInitMmioSize: 0x800 (default) >> >> PcdIgdDvmt50PreAlloc: 0x02 (default) >> >> PcdApertureSize: 0x02 (default) >> >> PcdGttSize: 0x02 (default) >> >> SerialDebugPortAddress: 0x3f8 (default) >> >> SerialDebugPortType: 0x01 (default) >> >> PcdMrcDebugMsg: 0x01 (default) >> >> PcdSccEnablePciMode: 0x01 (default) >> >> IgdRenderStandby: 0x00 (default) >> >> TxeUmaEnable: 0x00 (default) >> >> PcdOsSelection: 0x04 (default) >> >> PcdEMMC45DDR50Enabled: 0x01 (default) >> >> PcdEMMC45HS200Enabled: 0x00 (default) >> >> PcdEMMC45RetuneTimerValue: 0x08 (default) >> >> PcdEnableIgd: 0x01 (default) >> >> AutoSelfRefreshEnable: 0x00 (default) >> >> APTaskTimeoutCnt: 0x00 (default) >> >> GTT Size: 2 MB >> >> Tseg Size: 8 MB >> >> Aperture Size: 256 MB >> >> IGD Memory Size: 64 MB >> >> MMIO Size: 2048 MB >> >> MIPI/ISP: Disabled >> >> Sdio: Enabled >> >> Sdcard: Enabled >> >> SATA: Enabled >> >> SIO Dma 0: Enabled >> >> SIO I2C0: Enabled >> >> SIO I2C1: Enabled >> >> SIO I2C2: Enabled >> >> SIO I2C3: Enabled >> >> SIO I2C4: Enabled >> >> SIO I2C5: Enabled >> >> SIO I2C6: Enabled >> >> Azalia: Enabled >> >> SIO Dma1: Enabled >> >> Pwm0: Enabled >> >> Pwm1: Enabled >> >> Hsuart0: Enabled >> >> Hsuart1: Enabled >> >> Spi: Enabled >> >> Lpe: Disabled >> >> eMMC Mode: eMMC 4.5 >> >> SATA Mode: AHCI >> >> Xhci: Enabled >> >> POST: 0x92 >> >> >> >> >> >> ============= PEIM FSP (VLYVIEW0 0x00000304) ============= >> >> Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE >> >> Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3 >> >> Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A >> >> The 0th FV start address is 0x000FFFE0400, size is 0x00017C00, handle is >> 0x0 >> >> Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39 >> >> Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38 >> >> Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6 >> >> Install PPI: DBE23AA9-A345-4B97-85B6-B226F1617389 >> >> >> >> >> >> Install PPI: 06E81C58-4AD7-44BC-8390-F10265F72480 >> >> Install PPI: 01F34D25-4DE2-23AD-3FF3-36353FF323F1 >> >> >> >> >> >> Install PPI: 49EDB1C1-BF21-4761-BB12-EB0031AABB39 >> >> Notify: PPI Guid: 49EDB1C1-BF21-4761-BB12-EB0031AABB39, Peim notify entry >> point: FFFE0FD4 >> >> The 1th FV start address is 0x000FFFB0000, size is 0x0002F400, handle is >> 0xFFFB0000 >> >> >> >> >> >> Install PPI: A55D6970-1306-440C-8C72-8F51FAFB2926 >> >> PcdMrcInitTsegSize = 8 >> >> PcdMrcInitMmioSize = 800 >> >> PcdMrcInitSPDAddr1 = A0 >> >> PcdMrcInitSPDAddr2 = A2 >> >> Setting BootMode to 0 >> >> Install PPI: 1F4C6F90-B06B-48D8-A201-BAE5F1CD7D56 >> >> Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE >> >> About to call MrcInit(); >> >> BayleyBay Platform Type >> >> RID = 0x11. >> >> Reg_EFF_DualCH_EN = 0x40030040. >> >> CurrentMrcData.BootMode = 4 >> >> C1.D0: SPD not present. >> >> Configuring Memory Start... >> >> START_RMT: >> >> RxDqLeft RxDqRight RxVLow RxVHigh TxDqLeft >> TxDqRight CmdLeft CmdRight >> >> >> ------------------------------------------------------------------------------------------------ >> >> Channel 0 Rank 0 -22 21 -21 19 -25 >> 26 0 0 >> >> STOP_RMT: >> >> CMD module is per channel only and without Rank differentiation >> >> Configuring Memory End >> >> UpperTotalMemory = 0x80000000 >> >> dBMBOUND = 0x80000000 >> >> dBMBOUNDHI = 0x80000000 >> >> dGFXBase = 0x7BE00000 >> >> dTSegBase = 0x7B000000 >> >> Save MRC params. >> >> Current MRC Data DDR Freq 1 >> >> Current MRC Data Core Freq 1 >> >> Current MRC Data Tcl 7 >> >> Current MRC Data WL 6 >> >> Current MRC Data DDRType 1 >> >> Current MRC Data MMIO Size 800 >> >> Current MRC Data TSeg Size 8 >> >> Channel 0 >> >> Enabled 1 >> >> >> >> >> >> Socket 0 >> >> DimmPresent 1 >> >> DimmDataWidth 1 >> >> DimmBusWidth 3 >> >> DimmSize 2 >> >> DimmSides 0 >> >> Channel 1 >> >> Enabled 0 >> >> >> >> >> >> Socket 0 >> >> DimmPresent 0 >> >> DimmDataWidth 0 >> >> DimmBusWidth 0 >> >> DimmSize 0 >> >> DimmSides 0 >> >> Current MRC Timing Data MRC_DATA_TRP 7 >> >> Current MRC Timing Data MRC_DATA_TRCD 7 >> >> Current MRC Timing Data MRC_DATA_TRAS 13 >> >> Current MRC Timing Data MRC_DATA_TWR 8 >> >> Current MRC Timing Data MRC_DATA_TWTR 4 >> >> Current MRC Timing Data MRC_DATA_TRRD 4 >> >> Current MRC Timing Data MRC_DATA_TRTP 4 >> >> Current MRC Timing Data MRC_DATA_TFAW 1B >> >> PeiInstallPeiMemory MemoryBegin 0x7AE00000, MemoryLength 0x200000 >> >> Old Stack size 24576, New stack size 131072 >> >> Heap Offset = 0x0 Stack Offset = 0x840F0000 >> >> Stack Hob: BaseAddress=0x7AE00000 Length=0x20000 >> >> >> >> >> >> Reinstall PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3 >> >> Reinstall PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A >> >> Reinstall PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6 >> >> Install PPI: F894643D-C449-42D1-8EA8-85BDD8C65BDE >> >> Notify: PPI Guid: F894643D-C449-42D1-8EA8-85BDD8C65BDE, Peim notify entry >> point: FFFC1281 >> >> >> >> >> >> Install PPI: 0AE8CE5D-E448-4437-A8D7-EBF5F194F731 >> >> Install PPI: 1A36E4E7-FAB6-476A-8E75-695A0576FDD7 >> >> >> >> >> >> Install PPI: EF398D58-9DFD-4103-BF94-78C6F4FE712F >> >> >> >> >> >> InstallVlvInitPpi() - Start >> >> Register PPI Notify: 7D84B2C2-22A1-4372-B12C-EBB232D3A6A3 >> >> InstallVlvInitPpi() - End >> >> >> >> >> >> InstallPchInitPpi() - Start >> >> PmcBase needs to be programmed and enabled before here. >> >> ProgramGpioSCForSDCardWA Done.... >> >> Register PPI Notify: 15344673-D365-4BE2-8513-1497CC07611D >> >> Register PPI Notify: 00B710BA-8CD6-4BF3-AB7A-9A24F54CC334 >> >> Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE >> >> Notify: PPI Guid: F894643D-C449-42D1-8EA8-85BDD8C65BDE, Peim notify entry >> point: 7AFCB3C4 >> >> PchModPhyProgramming() - Start >> >> SOC B0 and later ModPhy Table programming >> >> PchModPhyProgramming() - End >> >> PchSataInit() - Start >> >> PchSataInit() - End >> >> InstallPchInitPpi() - End >> >> >> >> >> >> Register PPI Notify: 5BAB88BA-E0E2-4674-B6AD-B812F6881CD6 >> >> >> >> >> >> Register PPI Notify: 4B0165A9-61D6-4E23-A0B5-3EC79C2E30D5 >> >> Register PPI Notify: 30CFE3E7-3DE1-4586-BE20-DEABA1B3B793 >> >> Register PPI Notify: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B >> >> >> >> >> >> >> >> >> >> Install PPI: DD29124D-7819-4F15-BB07-351E7451D71C >> >> >> >> >> >> Install PPI: 7D84B2C2-22A1-4372-B12C-EBB232D3A6A3 >> >> Notify: PPI Guid: 7D84B2C2-22A1-4372-B12C-EBB232D3A6A3, Peim notify entry >> point: 7AFDE2E9 >> >> VlvInitPeiEntryPoint start.... >> >> >> >> >> >> ------------------------ VLV SSA Platform Policy dump Begin >> --------------- >> >> Graphics Configuration: >> >> GttSize : 2 MB >> >> IgdDvmt50PreAlloc : 2 >> >> PrimaryDisplay : 0 >> >> ApertureSize : 2 >> >> Turbo Enable : 1 >> >> >> >> >> >> ------------------------ VLV SSA Platform Policy dump END >> ----------------- >> >> ProgramEcBase Done.... >> >> SSASafeConfiguration Done.... >> >> Clear Dbuff to all zero before read 0xFFFFFFFF >> >> PUNIT_ISPSSPM0 value is 0x3000003 >> >> ISP Device is enabled by fuse >> >> Skip ISPConfig >> >> InitThermalRegisters Done.... >> >> IGD enabled. >> >> IGD Turbo Enable. >> >> PUNIT_BIOS_CONFIG11 = 0x400301C0. >> >> PUNIT_BIOS_CONFIG22 = 0x40030140. >> >> TotalMmioLength: 0x10400000 bytes >> >> GraphicsInit Done.... >> >> Install PPI: 09EA8911-BE0D-4230-A003-EDC693B48E11 >> >> Install mVlvPeiInitPpi Done.... >> >> Install PPI: 15344673-D365-4BE2-8513-1497CC07611D >> >> Notify: PPI Guid: 15344673-D365-4BE2-8513-1497CC07611D, Peim notify entry >> point: 7AFCBB94 >> >> PchInitialize() - Start >> >> PchMiscInit() - Start >> >> >> >> <<<<<<<<<<<<<<<<<< Debug log Start >> end >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> >> >> *L&T Technology Services Ltd* >> >> www.LntTechservices.com <http://www.lnttechservices.com/> >> >> This Email may contain confidential or privileged information for the >> intended recipient (s). If you are not the intended recipient, please do >> not use or disseminate the information, notify the sender and delete it >> from your system. >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> https://www.coreboot.org/mailman/listinfo/coreboot >> > >

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Re: [coreboot] [baytrail_FSP] question about lpss device with ACPI mode in win8
by Zoran Stojsavljevic 17 May '16

17 May '16

Hello Cheng, I am afraid, I have no ideas anymore what could be wrong. But I have for you one suggestion (path to resolution, maybe). No idea what you are using. In the sense BYT-FSP (MR5) -> Coreboot -> (payload???). You either use SeaBIOS (CSM ON), or Tiano Core/EK2 (CSM OFF). I would suggest the following: since it depends what payload you use because you would like to reuse your old HDD with WIN 8.1, to make test very short (no need to install other HDD with WIN 8.1). Please, take real UEFI BIOS (for BYT-M N2807 it is Client Group 64bit A093.R42 or later), and install it on some INTEL CRB (BayleyBay or BakerSport) where you already have N2807. Then, in relations what payload you are using, you need to set CSM ON or CSM OFF, to make work/reuse your original HDD with WIN 8.1. Please, after you are able to bring your INTEL BYT-M CRB to WIN 8.1, reboot, and again enter BIOS CMOS. There, under system setup/advanced settings, you should be able to find southbridge setup, where one of the options is LPSS. Please, experiment, with settings within LPSS mode (PCI and ACPI), and, please, report here do you have the same as with BYT-FSP MR5 settings as you use "pcdlpsssioenablepcimode" to "LPSS_PCI_MODE_DISABLE" and "ENABLE/DEFAULT" (do you see the same behavior in WIN 8.1 device manager)? Thank you, Zoran On Mon, May 16, 2016 at 2:06 PM, cheng yichen <blessyichen(a)gmail.com> wrote: > Hi Zoran > > Base on the version Baytrail_coreboot_MR5_Dec-21-2015(coreboot) that is > released by Intel. > In the coreboot(Intel released and defautle is acpi mode) I can install > driver and device is workable in win8. > I can see hs-uart controller in device manage and no yellow mark. > > In last coreboot source code. after I modify "pcdlpsssioenablepcimode" to > "LPSS_PCI_MODE_DISABLE". Then the lpss device will be confgured to ACPI > mode. > but the hs-uart controller and I2C controller will shown yellow mark in > win8 device manager. > Because the main controller is not workable in win8. I don't check the > sub-device device. > > > > > > 2016-05-16 17:16 GMT+08:00 Zoran Stojsavljevic < > zoran.stojsavljevic(a)gmail.com>: > >> Hello Cheng, >> >> Again, I'll repeat my questions: >> [1] Are you talking about BIOS, where you are enabling in LPSS ACPI >> (disabling automatically PCI) mode? >> [2] I need better explanation of your use case... Are you using BYT MR4, >> then MR5, or instead MR4 BIOS, or...? >> [3] For WIN8.1 you need to have the following: >> For BIOS to work (and get rid off these yellow triangles with >> question marks): >> [A] ACPI mode in BIOS: South Cluster Configuration -> LPSS & SCC >> Configuration -> LPSS LPSS & SCC >> Devices Mode -> Select "ACPI Mode"; >> [B] The GPIO controller driver is/should be prerequisite for >> HS-UART driver. There is a document named: >> Intel_Processor_Win8_IO_Drivers_Gold_MR1. You should ask for >> it from INTEL support. If installed >> correctly, you should see HS-UART Controller device under >> System Devices in Device Manager. Also >> new unknown devices should appear: ACPI\BCM2E1A and >> ACPI\BCM4752. These devices are for >> HS-UART Sub Device Driver; >> [C] You should compile the UART Sub Device Driver (by 1.2.1 of >> Intel Atom E3800 Win8.1 HS-UART Sub >> Device Driver Sample Code Guide_1.0), and install after >> building them. After that you should see Ports in >> Device Manager. >> >> Zoran >> >> On Fri, May 13, 2016 at 5:43 AM, cheng yichen <blessyichen(a)gmail.com> >> wrote: >> >>> >>> HI all >>> >>> I try to enable Lpss device(i2c hs-uart) with ACPI mdoe. >>> i2c and hs-uart will show yellow mark in device manager with win8.1. >>> but I can't find the same issue in intel coreboot(versrion MR5). >>> Do you have any idea for the issue? Thank you >>> >>> -- >>> coreboot mailing list: coreboot(a)coreboot.org >>> https://www.coreboot.org/mailman/listinfo/coreboot >>> >> >> >

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Re: [coreboot] Say hi to avatars on review.coreboot.org
by ron minnich 17 May '16

17 May '16

oh. wait. is that me? ron On Mon, May 16, 2016 at 4:39 PM ron minnich <rminnich(a)gmail.com> wrote: > There's no way this can work. > > > > On Mon, May 16, 2016 at 4:32 PM Stefan Reinauer < > stefan.reinauer(a)coreboot.org> wrote: > >> Hello coreboot folks, >> >> I've played around with gerrit's avatar feature this weekend and as >> a little gimmick, I have turned on avatars for our gerrit instance at >> https://review.coreboot.org/ >> >> In a never-ending effort to make it harder for everybody in the >> community to be mad at each other, you will now have the priceless >> opportunity to stare at each other's friendly faces while doing >> code reviews. >> >> NOTE: This feature is not using the gravatar service (and as such is >> not forwarding any personal information to another site), but only shows >> pictures locally stored on photos.coreboot.org. >> So if you're not showing up with a photo, I didn't have >> a good, publicly available photo of you. Right now the image store is >> completely manual, so if you want to have your own avatar show up in >> gerrit.coreboot.org, please feel free to send me a picture, preferrably >> in JPG format, square, at least 128x128. >> >> Stefan >> >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> https://www.coreboot.org/mailman/listinfo/coreboot >> >

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Say hi to avatars on review.coreboot.org
by Stefan Reinauer 17 May '16

17 May '16

Hello coreboot folks, I've played around with gerrit's avatar feature this weekend and as a little gimmick, I have turned on avatars for our gerrit instance at https://review.coreboot.org/ In a never-ending effort to make it harder for everybody in the community to be mad at each other, you will now have the priceless opportunity to stare at each other's friendly faces while doing code reviews. NOTE: This feature is not using the gravatar service (and as such is not forwarding any personal information to another site), but only shows pictures locally stored on photos.coreboot.org. So if you're not showing up with a photo, I didn't have a good, publicly available photo of you. Right now the image store is completely manual, so if you want to have your own avatar show up in gerrit.coreboot.org, please feel free to send me a picture, preferrably in JPG format, square, at least 128x128. Stefan

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ASRock E350M1: MSR 0x00000175 SYSENTER_ESP has 1 inconsistent values across 2 CPUs
by Paul Menzel 16 May '16

16 May '16

Dear coreboot folks, running fwts V16.03.00 [1] on the ASRock E350M1, the following test fails. ``` FAILED [MEDIUM] MSRCPUsInconsistent: Test 1, MSR 0x00000175 SYSENTER_ESP has 1 inconsistent values across 2 CPUs (shift: 0 mask: 0xffffffffffffffff). MSR CPU 0 -> 0xf77d0ab0 vs CPU 1 -> 0xf77e2ab0 ``` The same problem with different values is reported when running the vendor firmware. ``` FAILED [MEDIUM] MSRCPUsInconsistent: Test 1, MSR 0x00000175 SYSENTER_ESP has 1 inconsistent values across 2 CPUs (shift: 0 mask: 0xffffffffffffffff). MSR CPU 0 -> 0xf79d076c vs CPU 1 -> 0xf79e276c ``` I wonder if it’s an AGESA problem, or if it’s a false positive. Have you ever seen this? Thanks, Paul [1] https://wiki.ubuntu.com/FirmwareTestSuite Firmware Test Suite (fwts)

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[GSOC 2016] Coreboot panic room
by Antonello Dettori 16 May '16

16 May '16

Hello everyone, I am currently a computing student at the University of Abertay in Scotland and I would like to take part in this year GSOC. The proposal that I want to submit concerns the coreboot panic room idea since it looks like something that could really benefit the project as a whole and also because it seems like a really interesting technical challenge. I already digged through the blog and the mail exchanges of the previous developer working on this, Tadas Slotkus, and took a look at the patches that he wrote so I already have a general understanding of their aim. I would like to concentrate most of my efforts towards improving and upstreaming the previous efforts, implementing a way to easily access the recovery mode when needed and further the integration between coreboot, serialICE and flashrom for this use-case. Regarding the existing patches I would like to know if they would need to stay romc-compatible or should the scope be limited to CAR boards? Any suggestions on how to tackle this project or GSOC in general? Thanks in advance.

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Re: [coreboot] Upstream coreboot/SeaBIOS on google/ninja -- no emmc, video
by Matt DeVillier 16 May '16

16 May '16

Hi Zoran, appreciate the offer, and I'll try to clarify things: On 5/16/2016 5:07 AM, Zoran Stojsavljevic wrote: > Hello Matt, > > I'll try to help you... Please, do understand that I did not get well > what really you are trying to do. Let us do one step at the time. I'm trying to get the board google/ninja (a Baytrail-based Chromebox) working with upstream coreboot. Original google source here: https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/firmwar… I've already upstreamed several other google boards so I'm familiar with the process :) > > This step: 2) video output works properly for SeaBIOS and > grub/syslinux, but output is disabled once the OS / kernel driver loads. > _______ > > What I am getting from this email is the following (correct me if I am > wrong): BYT-FSP -> Coreboot -> (payload) SeaBIOS -> grub (2.0???) -> > Linux kernel 3/4.x.y (?). I'm not using FSP, using soc/intel/baytrail (not fsp_baytrail) since the board was not originally set up to do so, and would require a bit of reworking (without any obvious benefit). So coreboot->SeaBIOS (running vbios)->grub/syslinux->linux kernel 3/4.x > > Now. If you use as payload SeaBIOS, my best understanding is that > you'll use CSM (Compatibility Support Mode). So, in other words, > you'll use (if you will?) in Coreboot vBIOS (not GOP driver). Now, > furthermore, you MUST use vBIOS, since you are using SeaBIOS. And > Linux will use vBIOS (not GOP driver), since you'll pass INT > 0x15 mechanisms for Linux GFX (using mandatory vBIOS passed from > Coreboot), enforced from SeaBIOS - CSM?! CSM mode is only needed when Tianocore is the primary payload, since SeaBIOS is primary it is simply set up as a coreboot payload. I plan to use Tiancore + SeaBIOS/CSM eventually, but wanted SeaBIOS alone working first (since that's all my firmware releases to date have been). coreboot isn't running the vbios, just SeaBIOS (though I tried it both ways, with coreboot running the vbios first; there was no change). > > The question here is the following: why, for the change, you do not > use as payload TianoCore? This one is UEFI compatible, and very well > suits UEFI compliant Linux? In other words, you will use Linux as UEFI > compliant/compatible OS. Compliant to Tiano Core, which brings to you > UEFI features (initialized by default with Linux). Simply and plain... > And see what will happen? I actually did try Tianocore as the primary payload and had the exact same issues, so I went back to SeaBIOS since I know that works in conjunction with the factory firmware. > > Final line: I suspect, you did not built-in in Coreboot vBIOS package > and vBIOS init (just serial output), which is, using SeaBIOS payload > (CSM mechanism), I guess, mandatory (for Linux to overtake/inherit > legacy, to work with GFX). > > Thank you, > Zoran I'm not quite sure what you're saying here. If you mean that I did not have coreboot perform the video init, then I did try it both ways. On all the other boxes (ie, no built-in display) I've upstreamed, it's not been necessary to have coreboot run the vbios, only SeaBIOS. thanks, Matt > > On Sun, May 15, 2016 at 12:19 AM, Matt DeVillier > <matt.devillier(a)gmail.com <mailto:matt.devillier@gmail.com>> wrote: > > Greetings all! Currently I'm working on getting upstream coreboot > + SeaBIOS working on a Baytrail-based ChromeOS device (NINJA / > AOpen Chromebox commerical). After resolving some config issues > which prevented the board from booting, I'm left with two issues > on which I'm stuck: > > 1) the internal emmc / sdhci controller fails to initialize, and > is unavailable for boot or OS installation > 2) video output works properly for SeaBIOS and grub/syslinux, but > output is disabled once the OS / kernel driver loads > > For the emmc, cbmem shows that the sdhci controller is timing out > after setting the initial frequency, somewhere after line 410 of > seabios/src/hw/sdcard.c. Since the same exact SeaBIOS payload > works properly with the stock ChromeOS firmware (in both the > RW_LEGACY and BOOT_STUB slots), I suspect that the issue is with > coreboot, but the SoC init is pretty much identical between > upstream and NINJA's CrOS branch (save for a few base addresses > and offset calculations), so not sure where to start looking. > I've also tried putting the sdhci controller back into PCI mode > (vs ACPI) which had no effect. > > For the video output, the same vgabios file is being used as stock > CrOS, and same SeaBIOS payload. The i915 kernel driver reports > that no displays are connected, and there are some errors in the > drm module just prior. I tested with a few different flavors of > linux as well as Windows 10, to be certain it wasn't driver-related. > > Attached are the cbmem and kernel logs from both working (stock > CroS firmware + upstream SeaBIOS/BOOT_STUB) and non-working > (upstream coreboot+SeaBIOS) cases. > > As the board hasn't been officially upstreamed yet (something I > will do once these issues are resolved), source can be found in my > github repo here (it's just 3 commits on top of the current master > branch): https://github.com/MattDevo/coreboot/tree/ninja_upstream > > Hopefully someone can point me in the right direction here :) > > cheers, > Matt > > -- > coreboot mailing list: coreboot(a)coreboot.org > <mailto:coreboot@coreboot.org> > https://www.coreboot.org/mailman/listinfo/coreboot > >

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coreboot May 2016