coreboot May 2016

coreboot@coreboot.org

65 participants
149 discussions

Re: [coreboot] How to build coreboot with alternate toolchain?
by Paul Menzel 13 May '16

13 May '16

Dear David, Am Freitag, den 13.05.2016, 13:26 -0700 schrieb David Hendricks: > Do you have multiple versions of GCC installed? Yes, I do have several versions installed. The packages `gcc-4.9`, `gcc-5`, and `gcc-6`. > You might need to use "update-alternatives" to manage them. I haven't > done so with Debian, but this page seems to have a pretty good > explanation: > http://lektiondestages.blogspot.com/2013/05/installing-and-switching-gccg-v… Thank you for that suggestion, which Stefan Tauner also brought up in # coreboot(a)freenode.net. In Debian `cc` is not really managed by update- alternatives. ``` $ LANG=C sudo update-alternatives --config cc[sudo] password for paul: There is only one alternative in link group cc (providing /usr/bin/cc): /usr/bin/gcc Nothing to configure. $ LANG=C sudo update-alternatives --config gcc update-alternatives: error: no alternatives for gcc ``` As this is not required in other projects, like SeaBIOS, would it be useful to be able to pass variables in, so that the command below would work? ``` $ make HOSTCC=gcc-6 CC=gcc-6 ``` Thanks, Paul

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How to build coreboot with alternate toolchain?
by Paul Menzel 13 May '16

13 May '16

Dear coreboot folks, GCC 6 is in Debian Sid/unstable [1] in parallel to the default GCC 5.3. The binary is `/usr/bin/gcc-6`. I’d like to quickly test this with coreboot to see if everything still builds and runs fine. Running `make HOSTCC=gcc-6 CC=gcc-6` partially works. GCC 6 is used for the utilities, but not for building coreboot. ``` $ gcc --version gcc (Debian 5.3.1-19) 5.3.1 20160509 […] $ gcc-6 --version gcc-6 (Debian 6.1.1-3) 6.1.1 20160511 […] $ make HOSTCC=gcc-6 CC=gcc-6 CC ramstage/console/post.o gcc -MMD -Isrc -Isrc/include -Isrc/commonlib/include -Ibuild -Isrc/device/oprom/include -I3rdparty/vboot/firmware/include -include src/include/kconfig.h -I3rdparty -Isrc/arch/x86/include -Isrc/mainboard/asrock/e350m1 -Isrc/vendorcode/amd/agesa/f14 -Isrc/vendorcode/amd/agesa/f14/../common -Isrc/vendorcode/amd/agesa/f14/Include -Isrc/vendorcode/amd/agesa/f14/Lib -Isrc/vendorcode/amd/agesa/f14/Legacy -Isrc/vendorcode/amd/agesa/f14/Proc/Common -Isrc/vendorcode/amd/agesa/f14/Proc/CPU -Isrc/vendorcode/amd/agesa/f14/Proc/CPU/Family -Isrc/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14 -Isrc/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON -Isrc/vendorcode/amd/agesa/f14/Proc/CPU/Feature -Isrc/vendorcode/amd/agesa/f14/Proc/GNB -Isrc/vendorcode/amd/agesa/f14/Proc/GNB/Common -Isrc/vendorcode/amd/agesa/f14/Proc/GNB/Gfx -Isrc/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/Family -Isrc/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib -Isrc/vendorcode/amd/agesa/f14/Proc/GNB/Nb -Isrc/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family -Isrc/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14 -Isrc/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Feature -Isrc/vendorcode/amd/agesa/f14/Proc/GNB/PCIe -Isrc/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family -Isrc/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14 -Isrc/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Feature -Isrc/vendorcode/amd/agesa/f14/Proc/HT -Isrc/vendorcode/amd/agesa/f14/Proc/IDS -Isrc/vendorcode/amd/agesa/f14/Proc/Mem -Isrc/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON -Isrc/vendorcode/amd/agesa/f14/Proc/Recovery/GNB -Isrc/vendorcode/amd/agesa/f14/Proc/Recovery/CPU -Isrc/vendorcode/amd/agesa/f14/Proc/Recovery/Mem -Isrc/mainboard/asrock/e350m1 -Isrc/southbridge/amd/cimx/sb800 -Isrc/include/cpu/amd/common -Isrc/vendorcode/amd/cimx/sb800 -D__ARCH_x86_32__ -pipe -g -nostdinc -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wstrict-aliasing -Wshadow -Wdate-time -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer -ffunction-sections -fdata-sections -Wno-unused-but-set-variable -Werror -Os -m32 -fuse-ld=bfd -fno-stack-protector -Wl,--build-id=none -march=i686 -mno-mmx -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing -MT build/ramstage/console/post.o -D__RAMSTAGE__ -c -o build/ramstage/console/post.o src/console/post.c […] HOSTCC cbfstool/rmodtool (link) gcc-6 -o build/util/cbfstool/rmodtool build/util/cbfstool/rmodtool.o build/util/cbfstool/rmodule.o build/util/cbfstool/common.o build/util/cbfstool/elfheaders.o build/util/cbfstool/xdr.o cp build/util/cbfstool/rmodtool build/rmodtool printf "\nBuilt %s (%s)\n" "asrock/e350m1" \ ``` What variable do I need to set, so that GCC 6 is used for everything? Thanks, Paul PS: I am well aware, that only the coreboot toolchain is officially supported, but I have good experiences with the Debian toolchain on the ASRock E350M1 and Lenovo X60, and it really saves me the time of building the toolchain myself, which takes quite some time on the ASRock E350M1 and Lenovo X60.

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coreboot with fsp hangs at post code 19 on Bayley Bay
by Kathappan E 13 May '16

13 May '16

Hi all, When I try coreboot on Bayley Bay platform along with fsp (BAYTRAIL_FSP_GOLD_004_22-MAY-2015), it is getting hang at post code 19. Also I tried with debug version fsp (BAYTRAIL_FSP_GOLD_004_22-MAY-2015_DEBUG) , it still at that point and below is the debug log. Firmware Image: Have used the 8 MB vendor bios and flashed the last 2 MB region(600000 to 7fffff) with coreboot image. >From the debug log: coreboot gives the control to FSP binary routine(FspInitApi) and it is getting hang when trying to do PCH initialize(PchMiscInit) inside FSP part code. POST 19 code info: EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_CLOCK_PEI_INIT_ENTRY ==> Clock Init PEIM Entry I have not seen the clock related setting available when customizing fsp binary using BCT. I tried to disable south cluster component such as EMMC,HSUART,SATA and SIO using BCT , it didn't help me. Can anyone please help me provide some inputs such as related below to proceed further debugging on it ? 1. Any other setting we can try out using BCT 2. About devices configuration to be initialized byPchMiscInit function. 3. Anything need to be cared/double checked from coreboot side in order to giving control to FspInitApi function. 4. Does pch straps settings may cause this since I am using upper 6 MB region flash data which is from vendor bios. 4. Please suggest anything on it. Thanks in advance, Kathappan <<<<<<<<<<<< Debug log Start >>>>>>>>>>>>>>> coreboot-coreboot-unknown Thu May 12 08:04:42 UTC 2016 romstage starting... RTC Init POST: 0x44 POST: 0x47 POST: 0x48 Starting the Intel FSP (early_init) PM1_STS = 0x0 PM1_CNT = 0x0 GEN_PMCON1 = 0x44000 prev_sleep_state = S5 Configure Default UPD Data PcdMrcInitSPDAddr1: 0xa0 (default) PcdMrcInitSPDAddr2: 0xa2 (default) PcdSataMode: 0x01 (set) PcdLpssSioEnablePciMode: 0x01 (default) PcdMrcInitMmioSize: 0x800 (default) PcdIgdDvmt50PreAlloc: 0x02 (default) PcdApertureSize: 0x02 (default) PcdGttSize: 0x02 (default) SerialDebugPortAddress: 0x3f8 (default) SerialDebugPortType: 0x01 (default) PcdMrcDebugMsg: 0x01 (default) PcdSccEnablePciMode: 0x01 (default) IgdRenderStandby: 0x00 (default) TxeUmaEnable: 0x00 (default) PcdOsSelection: 0x04 (default) PcdEMMC45DDR50Enabled: 0x01 (default) PcdEMMC45HS200Enabled: 0x00 (default) PcdEMMC45RetuneTimerValue: 0x08 (default) PcdEnableIgd: 0x01 (default) AutoSelfRefreshEnable: 0x00 (default) APTaskTimeoutCnt: 0x00 (default) GTT Size: 2 MB Tseg Size: 8 MB Aperture Size: 256 MB IGD Memory Size: 64 MB MMIO Size: 2048 MB MIPI/ISP: Disabled Sdio: Enabled Sdcard: Enabled SATA: Enabled SIO Dma 0: Enabled SIO I2C0: Enabled SIO I2C1: Enabled SIO I2C2: Enabled SIO I2C3: Enabled SIO I2C4: Enabled SIO I2C5: Enabled SIO I2C6: Enabled Azalia: Enabled SIO Dma1: Enabled Pwm0: Enabled Pwm1: Enabled Hsuart0: Enabled Hsuart1: Enabled Spi: Enabled Lpe: Disabled eMMC Mode: eMMC 4.5 SATA Mode: AHCI Xhci: Enabled POST: 0x92 ============= PEIM FSP (VLYVIEW0 0x00000304) ============= Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3 Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A The 0th FV start address is 0x000FFFE0400, size is 0x00017C00, handle is 0x0 Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39 Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38 Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6 Install PPI: DBE23AA9-A345-4B97-85B6-B226F1617389 Install PPI: 06E81C58-4AD7-44BC-8390-F10265F72480 Install PPI: 01F34D25-4DE2-23AD-3FF3-36353FF323F1 Install PPI: 49EDB1C1-BF21-4761-BB12-EB0031AABB39 Notify: PPI Guid: 49EDB1C1-BF21-4761-BB12-EB0031AABB39, Peim notify entry point: FFFE0FD4 The 1th FV start address is 0x000FFFB0000, size is 0x0002F400, handle is 0xFFFB0000 Install PPI: A55D6970-1306-440C-8C72-8F51FAFB2926 PcdMrcInitTsegSize = 8 PcdMrcInitMmioSize = 800 PcdMrcInitSPDAddr1 = A0 PcdMrcInitSPDAddr2 = A2 Setting BootMode to 0 Install PPI: 1F4C6F90-B06B-48D8-A201-BAE5F1CD7D56 Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE About to call MrcInit(); BayleyBay Platform Type RID = 0x11. Reg_EFF_DualCH_EN = 0x40030040. CurrentMrcData.BootMode = 4 C1.D0: SPD not present. Configuring Memory Start... START_RMT: RxDqLeft RxDqRight RxVLow RxVHigh TxDqLeft TxDqRight CmdLeft CmdRight ------------------------------------------------------------------------------------------------ Channel 0 Rank 0 -22 21 -21 19 -25 26 0 0 STOP_RMT: CMD module is per channel only and without Rank differentiation Configuring Memory End UpperTotalMemory = 0x80000000 dBMBOUND = 0x80000000 dBMBOUNDHI = 0x80000000 dGFXBase = 0x7BE00000 dTSegBase = 0x7B000000 Save MRC params. Current MRC Data DDR Freq 1 Current MRC Data Core Freq 1 Current MRC Data Tcl 7 Current MRC Data WL 6 Current MRC Data DDRType 1 Current MRC Data MMIO Size 800 Current MRC Data TSeg Size 8 Channel 0 Enabled 1 Socket 0 DimmPresent 1 DimmDataWidth 1 DimmBusWidth 3 DimmSize 2 DimmSides 0 Channel 1 Enabled 0 Socket 0 DimmPresent 0 DimmDataWidth 0 DimmBusWidth 0 DimmSize 0 DimmSides 0 Current MRC Timing Data MRC_DATA_TRP 7 Current MRC Timing Data MRC_DATA_TRCD 7 Current MRC Timing Data MRC_DATA_TRAS 13 Current MRC Timing Data MRC_DATA_TWR 8 Current MRC Timing Data MRC_DATA_TWTR 4 Current MRC Timing Data MRC_DATA_TRRD 4 Current MRC Timing Data MRC_DATA_TRTP 4 Current MRC Timing Data MRC_DATA_TFAW 1B PeiInstallPeiMemory MemoryBegin 0x7AE00000, MemoryLength 0x200000 Old Stack size 24576, New stack size 131072 Heap Offset = 0x0 Stack Offset = 0x840F0000 Stack Hob: BaseAddress=0x7AE00000 Length=0x20000 Reinstall PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3 Reinstall PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A Reinstall PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6 Install PPI: F894643D-C449-42D1-8EA8-85BDD8C65BDE Notify: PPI Guid: F894643D-C449-42D1-8EA8-85BDD8C65BDE, Peim notify entry point: FFFC1281 Install PPI: 0AE8CE5D-E448-4437-A8D7-EBF5F194F731 Install PPI: 1A36E4E7-FAB6-476A-8E75-695A0576FDD7 Install PPI: EF398D58-9DFD-4103-BF94-78C6F4FE712F InstallVlvInitPpi() - Start Register PPI Notify: 7D84B2C2-22A1-4372-B12C-EBB232D3A6A3 InstallVlvInitPpi() - End InstallPchInitPpi() - Start PmcBase needs to be programmed and enabled before here. ProgramGpioSCForSDCardWA Done.... Register PPI Notify: 15344673-D365-4BE2-8513-1497CC07611D Register PPI Notify: 00B710BA-8CD6-4BF3-AB7A-9A24F54CC334 Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE Notify: PPI Guid: F894643D-C449-42D1-8EA8-85BDD8C65BDE, Peim notify entry point: 7AFCB3C4 PchModPhyProgramming() - Start SOC B0 and later ModPhy Table programming PchModPhyProgramming() - End PchSataInit() - Start PchSataInit() - End InstallPchInitPpi() - End Register PPI Notify: 5BAB88BA-E0E2-4674-B6AD-B812F6881CD6 Register PPI Notify: 4B0165A9-61D6-4E23-A0B5-3EC79C2E30D5 Register PPI Notify: 30CFE3E7-3DE1-4586-BE20-DEABA1B3B793 Register PPI Notify: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B Install PPI: DD29124D-7819-4F15-BB07-351E7451D71C Install PPI: 7D84B2C2-22A1-4372-B12C-EBB232D3A6A3 Notify: PPI Guid: 7D84B2C2-22A1-4372-B12C-EBB232D3A6A3, Peim notify entry point: 7AFDE2E9 VlvInitPeiEntryPoint start.... ------------------------ VLV SSA Platform Policy dump Begin --------------- Graphics Configuration: GttSize : 2 MB IgdDvmt50PreAlloc : 2 PrimaryDisplay : 0 ApertureSize : 2 Turbo Enable : 1 ------------------------ VLV SSA Platform Policy dump END ----------------- ProgramEcBase Done.... SSASafeConfiguration Done.... Clear Dbuff to all zero before read 0xFFFFFFFF PUNIT_ISPSSPM0 value is 0x3000003 ISP Device is enabled by fuse Skip ISPConfig InitThermalRegisters Done.... IGD enabled. IGD Turbo Enable. PUNIT_BIOS_CONFIG11 = 0x400301C0. PUNIT_BIOS_CONFIG22 = 0x40030140. TotalMmioLength: 0x10400000 bytes GraphicsInit Done.... Install PPI: 09EA8911-BE0D-4230-A003-EDC693B48E11 Install mVlvPeiInitPpi Done.... Install PPI: 15344673-D365-4BE2-8513-1497CC07611D Notify: PPI Guid: 15344673-D365-4BE2-8513-1497CC07611D, Peim notify entry point: 7AFCBB94 PchInitialize() - Start PchMiscInit() - Start <<<<<<<<<<<<<<<<<< Debug log Start end >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> L&T Technology Services Ltd www.LntTechservices.com<http://www.lnttechservices.com/> This Email may contain confidential or privileged information for the intended recipient (s). If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system.

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ASUS KFSN4-DRE (K8) Automated Test Failure [master]
by Raptor Engineering Automated Coreboot Test Stand 13 May '16

13 May '16

The ASUS KFSN4-DRE (K8) fails verification for branch master as of commit 572f07497104e1f9c4e1ed0fd01850a9e2a4803f The following tests failed: BOOT_FAILURE Commits since last successful test: 572f074 inteltool: update documentation See attached log for details This message was automatically generated from Raptor Engineering's ASUS KFSN4-DRE (K8) test stand Want to test on your own equipment? Check out https://www.raptorengineeringinc.com/content/REACTS/intro.html Raptor Engineering also offers coreboot consulting services! Please visit https://www.raptorengineeringinc.com for more information Please contact Timothy Pearson at Raptor Engineering <tpearson(a)raptorengineeringinc.com> regarding any issues stemming from this notification

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Fwd: [baytrail_FSP] question about lpss device with ACPI mode in win8
by cheng yichen 13 May '16

13 May '16

1. PcdLpssSioEnablePciMode setting is LPSS_PCI_MODE_DISABLE and I am sure lpss is in acpi mode, because I can't find any lpss device in pci list. 2. The cpu type is N2807.

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Re: [coreboot] [baytrail_FSP] question about lpss device with ACPI mode in win8
by Zoran Stojsavljevic 13 May '16

13 May '16

Hello Chen, Few questions about your post, may I? [1] You are talking about CMOS settings in BYT BIOS (LPSS in ACPI mode), correct? [2] What kind of BYT SoC you are using (BYT M/D/I or T)? What are the numbers (example: BYT-I 3827)? Thank you, Zoran On Fri, May 13, 2016 at 5:43 AM, cheng yichen <blessyichen(a)gmail.com> wrote: > > HI all > > I try to enable Lpss device(i2c hs-uart) with ACPI mdoe. > i2c and hs-uart will show yellow mark in device manager with win8.1. > but I can't find the same issue in intel coreboot(versrion MR5). > Do you have any idea for the issue? Thank you > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot >

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[baytrail_FSP] question about lpss device with ACPI mode in win8
by cheng yichen 13 May '16

13 May '16

HI all I try to enable Lpss device(i2c hs-uart) with ACPI mdoe. i2c and hs-uart will show yellow mark in device manager with win8.1. but I can't find the same issue in intel coreboot(versrion MR5). Do you have any idea for the issue? Thank you

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Regarding CONFIG_CBFS_LOCATION corruption of sea bios using coreboot
by rajashaker Goud 13 May '16

13 May '16

Hi All, I am using coreboot with seabios payload to boot to Win7. But sometimes Seabios is not able to find its own CBFS partition in the coreboot image and causes the exception and does not boot OS. Below is source code which throws exception: In SeaBIOS config value, the default value of CONFIG_CBFS_LOCATION is set to Zero. struct cbfs_header *hdr = *(void ****)(CONFIG_CBFS_LOCATION - 4); if ((u32)hdr & 0x03) { dprintf(1, "Invalid CBFS pointer %p\n", hdr); return; } Here CBFS header pointer *hdr points to valid address 0xfffffc10 ( that is being calculated from (CONFIG_CBFS_LOCATION – 4)) but sometimes CBFS header pointer *hdr is invalid and points to 0xffffffff, thus SeaBIOS does not execute further ROM code e.g. VGA option ROM. As we know the address of seabios CBFS hdr pointer so either we can hard code the config Variable CONFIG_CBFS_LOCATION to value 0xfffffc14 OR we can assign *hdr to address 0xfffffc10 in source code. struct cbfs_header *hdr = *(void ****)(CONFIG_CBFS_LOCATION - 4); if ((u32)hdr & 0x03) { dprintf(1, "Invalid CBFS pointer %p\n", hdr); hdr=0xfffffc10; } Please let me know if any information. -- Thanks, Rajashaker Goud Ranga

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Trouble with T60p (whine and trackpoint dead)
by David Griffith 12 May '16

12 May '16

I'm trying out Coreboot on a Thinkpad T60p. I followed the instructions at https://github.com/bibanon/Coreboot-ThinkPads/wiki/ThinkPad-T60p until I got the flashing part. There it wasn't clear where the lenovobios_firstflash and lenovobios_secondflash scripts were to be found. On IRC, someone pointed me to https://github.com/rabcyr/libreboot/blob/master/lenovobios_firstflash. I used that and got what seems like a failure[1]. A few minutes after this, the laptop decided to go to sleep and I couldn't wake it. I rebooted and evidently somehow Coreboot and SeaBIOS took. Now I suppose I'm at the stage where I do the second flashing. In the meantime, the trackpoint stick and buttons won't work anymore and there's an intermittent high-pitched whine from the left side of the keyboard. Did I actually succeed in flashing my T60p? Did I do anything wrong? How do I fix the trackpoint and get rid of the whine? [1] $ sudo ./lenovobios_firstflash ~/coreboot/build/coreboot.rom if [[ $EUID -ne 0 ]]; then echo "This script must be run as root" exit 1 fi if (( $# != 1 )); then echo "Usage: ./lenovobios_firstflash yourrom.rom" echo "usage: ./lenovobios_firstflash path/to/yourrom.rom" echo "You need to specify exactly 1 file" exit 1 fi Usage: ./lenovobios_firstflash yourrom.rom usage: ./lenovobios_firstflash path/to/yourrom.rom You need to specify exactly 1 file dave@osiris:~/libreboot_util$ sudo ./lenovobios_firstflash ~/coreboot/build/coreboot.rom if [[ $EUID -ne 0 ]]; then echo "This script must be run as root" exit 1 fi if (( $# != 1 )); then echo "Usage: ./lenovobios_firstflash yourrom.rom" echo "usage: ./lenovobios_firstflash path/to/yourrom.rom" echo "You need to specify exactly 1 file" exit 1 fi if [ ! -f $1 ]; then echo "File not found!" exit 1 fi bucts="unknown" flashromsst="unknown" flashrommacronix="unknown" if [ -f "DEBLOB" ]; then bucts="./bucts/bucts" flashromsst="./flashrom/flashrom_lenovobios_sst" flashrommacronix="./flashrom/flashrom_lenovobios_macronix" elif [ $(uname -i) = "i686" ] || [ $(uname -m) = "i686" ]; then bucts="./bucts/i686/bucts" flashromsst="./flashrom/i686/flashrom_lenovobios_sst" flashrommacronix="./flashrom/i686/flashrom_lenovobios_macronix" elif [ $(uname -i) = "x86_64" ] || [ $(uname -m) = "x86_64" ]; then bucts="./bucts/x86_64/bucts" flashromsst="./flashrom/x86_64/flashrom_lenovobios_sst" flashrommacronix="./flashrom/x86_64/flashrom_lenovobios_macronix" else echo "This script must be run on an i686 or x86_64 host. x86_64 is recommended." exit 1 fi uname -i) uname -i uname -m) uname -m # Set bucts # this means we are working in src if [ ! -f "$bucts" ]; then echo "BUCTS failed. Make sure BUC.TS is 1, or else you will brick your machine. ABORTING so as to protect against bricking the machine." exit 1 fi $(echo $bucts) 1 echo $bucts) echo $bucts bucts utility version 'withoutgit' Using LPC bridge 8086:27b9 at 0000:1f.00 Current BUC.TS=0 - 128kb address range 0xFFFE0000-0xFFFFFFFF is untranslated Updated BUC.TS=1 - 64kb address ranges at 0xFFFE0000 and 0xFFFF0000 are swapped $(echo $flashromsst) -p internal -w $1 echo $flashromsst) echo $flashromsst flashrom v0.9.8-unknown on Linux 3.2.0-4-686-pae (i686) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found chipset "Intel ICH7M". Enabling flash write... WARNING: SPI Configuration Lockdown activated. OK. Found SST flash chip "SST25VF016B" (2048 kB, SPI) mapped at physical address 0xffe00000. Reading old flash chip contents... done. Erasing and writing flash chip... spi_block_erase_20 failed during command execution at address 0x0 Reading current flash chip contents... done. Looking for another erase function. spi_block_erase_52 failed during command execution at address 0x0 Reading current flash chip contents... done. Looking for another erase function. Transaction error! spi_block_erase_d8 failed during command execution at address 0x1f0000 Reading current flash chip contents... done. Looking for another erase function. spi_chip_erase_60 failed during command execution Reading current flash chip contents... done. Looking for another erase function. spi_chip_erase_c7 failed during command execution Looking for another erase function. No usable erase functions left. FAILED! Uh oh. Erase/write failed. Checking if anything has changed. Reading current flash chip contents... done. Apparently at least some data has changed. Your flash chip is in an unknown state. Get help on IRC at chat.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org with the subject "FAILED: <your board name>"! ------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF! $(echo $flashrommacronix) -p internal -w $1 echo $flashrommacronix) echo $flashrommacronix flashrom v0.9.8-unknown on Linux 3.2.0-4-686-pae (i686) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found chipset "Intel ICH7M". Enabling flash write... WARNING: SPI Configuration Lockdown activated. OK. No EEPROM/flash device found. Note: flashrom can never write if the flash chip isn't found automatically. -- David Griffith dave(a)661.org A: Because it fouls the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing in e-mail?

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I want to use Coreboot for booting an Allwinner A13 computer..
by madscientist 12 May '16

12 May '16

First of all, i want to thank the administrator of the list for giving me a place on this. I have an A13 based board, wich i wish to be able to start some sort of gnu/linux with lxde distro from an usb hard drive, but a real hard drive and not just an usb pen or flash card. I also wish it to be able to boot a livecd from a usb cd/dvd unit, more or less like a PC would do. I have little experience in the ARM field, i had read the A13 datasheet and i have an idea of how does it work and interact with hardware, but yet i'm afraid i'm not able enought to change it's behaviour. In consequence, i wish to ask if an image of coreboot for this kind of s.o.c could be avaiable for download and install into a flash ram, or, in negative case, how could one be built, being ready to look for usb mass storage trough an usb hub connected to the usb pins of the A13. I actually wish to have it permanently on a small flash ram and have the working software booting from a usb hard drive and or usb cd/dvd unit. Thank you for your support.

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coreboot May 2016