coreboot May 2016

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Re: [coreboot] Coreboot image and seabios payload with debug symbols
by Mayuri Tendulkar 12 May '16

12 May '16

Hi Zoran I am having Intel system studio trial version and also XDP3 connector. Regards Mayuri From: Zoran Stojsavljevic [mailto:zoran.stojsavljevic@gmail.com] Sent: 12 May 2016 17:31 To: Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com>; coreboot(a)coreboot.org Subject: Re: [coreboot] Coreboot image and seabios payload with debug symbols Hello Mayuri, [3] The other way how to use ITP BlueBox XDP3 is to use ISS (INTEL System Studio). I guess, there is 30 day free trial for ISS (on the intel.com<http://intel.com> public web, there is an ISS download somewhere), but if you would like to have ISS activated, you need to contact ISS INTEL support. Hope this helps, Zoran On Thu, May 12, 2016 at 9:38 AM, Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com<mailto:mayuri.tendulkar@aricent.com>> wrote: Thanks. I will check that. But I didn’t get 3rd point completely. From: Zoran Stojsavljevic [mailto:zoran.stojsavljevic@gmail.com<mailto:zoran.stojsavljevic@gmail.com>] Sent: 12 May 2016 12:18 To: Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com<mailto:mayuri.tendulkar@aricent.com>>; coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> Subject: Re: [coreboot] Coreboot image and seabios payload with debug symbols Hello Mayuri, Sorry, I am busy with some other things (trying to perfect my Deutsch Sprache, and this goes too slow, and too pejorative)... :-( I did not look thru the second document, but here is what I'll advise here: [1] Go to https://gcc.gnu.org/onlinedocs/gcc-4.8.0/gcc/Debugging-Options.html and find how to compile Coreboot with debug and maximum warnings. Not sure, -D is for debug, -O for the warnings. [2] From www.intel.com/fsp<http://www.intel.com/fsp>, use the following Debug FSP, included in the package from: Intel® Atom™ processor E3800 product family (formerly Bay Trail, Compliant with FSP v1.0 Specification) [3] You do need to use DAL/PDT ITP2 package for your XDP3 (60 pin connector), since for BYT family only ITP2 SW is available (legacy ITP disconnected). Later... Zoran On Thu, May 12, 2016 at 7:44 AM, Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com<mailto:mayuri.tendulkar@aricent.com>> wrote: Hi Zoran Can you please update on this? Can we build using debug FSP and gdb enabling? Regards Mayuri From: Mayuri Tendulkar Sent: 11 May 2016 10:02 To: 'Zoran Stojsavljevic' <zoran.stojsavljevic(a)gmail.com<mailto:zoran.stojsavljevic@gmail.com>> Cc: coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> Subject: RE: [coreboot] Coreboot image and seabios payload with debug symbols Hi Zoran Please find responses: [1] When you do refer to "Intel system debugger", do you refer to INTEL ITP2 debugger, with Blue Box XDP 60 pin HW connector (http://m.eet.com/media/1073715/JTAG_101_fig5.jpg)? This is Intel® ITP-XDP3. https://software.intel.com/sites/default/files/managed/45/19/10-jtag-debugg… [2] For which CPU/SoC/platform you would like to use [1]? – This I am currently using for Minnowboard Turbot (E3826 dual core) [3] Seems that you did copy some debug excerpt from some INTEL document... I guess, this one is public one. Could you, please, attach this (if?) public document to this @ thread for our review, or either pass to us www pointer to this document? This can be found from Intel system debugger use guide. https://software.intel.com/en-us/node/592929- check section debugging basics Regards Mayuri From: Zoran Stojsavljevic [mailto:zoran.stojsavljevic@gmail.com] Sent: 10 May 2016 23:15 To: Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com<mailto:mayuri.tendulkar@aricent.com>> Cc: coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> Subject: Re: [coreboot] Coreboot image and seabios payload with debug symbols Hello Mayuri, Few questions, may I? [1] When you do refer to "Intel system debugger", do you refer to INTEL ITP2 debugger, with Blue Box XDP 60 pin HW connector (http://m.eet.com/media/1073715/JTAG_101_fig5.jpg)? [2] For which CPU/SoC/platform you would like to use [1]? [3] Seems that you did copy some debug excerpt from some INTEL document... I guess, this one is public one. Could you, please, attach this (if?) public document to this @ thread for our review, or either pass to us www pointer to this document? Thank you, Zoran [https://ssl.gstatic.com/ui/v1/icons/mail/images/cleardot.gif] On Tue, May 10, 2016 at 8:22 AM, Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com<mailto:mayuri.tendulkar@aricent.com>> wrote: Hi I want to use Intel system debugger to do coreboot source level debugging. So I need below. Can you please help me in this? To debug your software using source code you need to load debug information that is used to map the program in target memory to the original source files. To do this the debugger needs the following: * A program loaded in target memory that has been compiled with debug information * The load address of the program in target memory * The program binary file (executable file) * Debug information file for the program binary (also referred to as "symbols") * Original program source code Regards Mayuri "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." -- coreboot mailing list: coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> https://www.coreboot.org/mailman/listinfo/coreboot "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus."

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Re: [coreboot] Coreboot image and seabios payload with debug symbols
by Zoran Stojsavljevic 12 May '16

12 May '16

Hello Mayuri, [3] The other way how to use ITP BlueBox XDP3 is to use ISS (INTEL System Studio). I guess, there is 30 day free trial for ISS (on the intel.com public web, there is an ISS download somewhere), but if you would like to have ISS activated, you need to contact ISS INTEL support. Hope this helps, Zoran On Thu, May 12, 2016 at 9:38 AM, Mayuri Tendulkar < mayuri.tendulkar(a)aricent.com> wrote: > Thanks. I will check that. > > But I didn’t get 3rd point completely. > > > > *From:* Zoran Stojsavljevic [mailto:zoran.stojsavljevic@gmail.com] > *Sent:* 12 May 2016 12:18 > *To:* Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com>; > coreboot(a)coreboot.org > > *Subject:* Re: [coreboot] Coreboot image and seabios payload with debug > symbols > > > > Hello Mayuri, > > > > Sorry, I am busy with some other things (trying to perfect my Deutsch > Sprache, and this goes too slow, and too pejorative)... :-( > > > > I did not look thru the second document, but here is what I'll advise > here: > > [1] Go to > https://gcc.gnu.org/onlinedocs/gcc-4.8.0/gcc/Debugging-Options.html and > find how to compile Coreboot with debug and maximum warnings. Not sure, -D > is for debug, -O for the warnings. > > [2] From www.intel.com/fsp, use the following Debug FSP, included in the > package from: *Intel® Atom™ processor E3800 product family *(formerly Bay > Trail, Compliant with FSP v1.0 Specification) > > [3] You do need to use DAL/PDT ITP2 package for your XDP3 (60 pin > connector), since for BYT family only ITP2 SW is available (legacy ITP > disconnected). > > > > Later... > > > > Zoran > > > > > > On Thu, May 12, 2016 at 7:44 AM, Mayuri Tendulkar < > mayuri.tendulkar(a)aricent.com> wrote: > > Hi Zoran > > > > Can you please update on this? > > > > Can we build using debug FSP and gdb enabling? > > > > Regards > > Mayuri > > > > *From:* Mayuri Tendulkar > *Sent:* 11 May 2016 10:02 > *To:* 'Zoran Stojsavljevic' <zoran.stojsavljevic(a)gmail.com> > *Cc:* coreboot(a)coreboot.org > *Subject:* Re: [coreboot] Coreboot image and seabios payload with debug > symbols > > > > Hi Zoran > > > > Please find responses: > > > > [1] When you do refer to *"**Intel system debugger",* do you refer to > INTEL ITP2 debugger, with Blue Box XDP 60 pin HW connector ( > http://m.eet.com/media/1073715/JTAG_101_fig5.jpg)? > > > > This is Intel® ITP-XDP3. > https://software.intel.com/sites/default/files/managed/45/19/10-jtag-debugg… > > > > > > [2] For which CPU/SoC/platform you would like to use [1]? – This I am > currently using for Minnowboard Turbot (E3826 dual core) > > > > [3] Seems that you did copy some debug excerpt from some INTEL document... > I guess, this one is public one. Could you, please, attach this (if?) > public document to this @ thread for our review, or either pass to us www > pointer to this document? > > > > This can be found from Intel system debugger use guide. > > https://software.intel.com/en-us/node/592929- check section debugging > basics > > > > Regards > > Mayuri > > > > > > *From:* Zoran Stojsavljevic [mailto:zoran.stojsavljevic@gmail.com > <zoran.stojsavljevic(a)gmail.com>] > *Sent:* 10 May 2016 23:15 > *To:* Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com> > *Cc:* coreboot(a)coreboot.org > *Subject:* Re: [coreboot] Coreboot image and seabios payload with debug > symbols > > > > Hello Mayuri, > > > > Few questions, may I? > > > > [1] When you do refer to *"**Intel system debugger",* do you refer to > INTEL ITP2 debugger, with Blue Box XDP 60 pin HW connector ( > http://m.eet.com/media/1073715/JTAG_101_fig5.jpg)? > > > > [2] For which CPU/SoC/platform you would like to use [1]? > > > > [3] Seems that you did copy some debug excerpt from some INTEL document... > I guess, this one is public one. Could you, please, attach this (if?) > public document to this @ thread for our review, or either pass to us www > pointer to this document? > > > > Thank you, > > Zoran > > > > On Tue, May 10, 2016 at 8:22 AM, Mayuri Tendulkar < > mayuri.tendulkar(a)aricent.com> wrote: > > Hi > > > > I want to use Intel system debugger to do coreboot source level debugging. > > > > So I need below. Can you please help me in this? > > To debug your software using source code you need to load debug > information that is used to map the program in target memory to the > original source files. To do this the debugger needs the following: > > - A program loaded in target memory that has been compiled with debug > information > - The load address of the program in target memory > - The program binary file (executable file) > - Debug information file for the program binary (also referred to as > "symbols") > - Original program source code > > Regards > > Mayuri > > "DISCLAIMER: This message is proprietary to Aricent and is intended solely > for the use of the individual to whom it is addressed. It may contain > privileged or confidential information and should not be circulated or used > for any purpose other than for what it is intended. If you have received > this message in error, please notify the originator immediately. If you are > not the intended recipient, you are notified that you are strictly > prohibited from using, copying, altering, or disclosing the contents of > this message. Aricent accepts no responsibility for loss or damage arising > from the use of the information transmitted by this email including damage > from virus." > > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot > > > > "DISCLAIMER: This message is proprietary to Aricent and is intended solely > for the use of the individual to whom it is addressed. It may contain > privileged or confidential information and should not be circulated or used > for any purpose other than for what it is intended. If you have received > this message in error, please notify the originator immediately. If you are > not the intended recipient, you are notified that you are strictly > prohibited from using, copying, altering, or disclosing the contents of > this message. Aricent accepts no responsibility for loss or damage arising > from the use of the information transmitted by this email including damage > from virus." > > > "DISCLAIMER: This message is proprietary to Aricent and is intended solely > for the use of the individual to whom it is addressed. It may contain > privileged or confidential information and should not be circulated or used > for any purpose other than for what it is intended. If you have received > this message in error, please notify the originator immediately. If you are > not the intended recipient, you are notified that you are strictly > prohibited from using, copying, altering, or disclosing the contents of > this message. Aricent accepts no responsibility for loss or damage arising > from the use of the information transmitted by this email including damage > from virus." >

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Re: [coreboot] Coreboot image and seabios payload with debug symbols
by Zoran Stojsavljevic 12 May '16

12 May '16

Hello Mayuri, Sorry, I am busy with some other things (trying to perfect my Deutsch Sprache, and this goes too slow, and too pejorative)... :-( I did not look thru the second document, but here is what I'll advise here: [1] Go to https://gcc.gnu.org/onlinedocs/gcc-4.8.0/gcc/Debugging-Options.html and find how to compile Coreboot with debug and maximum warnings. Not sure, -D is for debug, -O for the warnings. [2] From www.intel.com/fsp, use the following Debug FSP, included in the package from: *Intel® Atom™ processor E3800 product family *(formerly Bay Trail, Compliant with FSP v1.0 Specification) [3] You do need to use DAL/PDT ITP2 package for your XDP3 (60 pin connector), since for BYT family only ITP2 SW is available (legacy ITP disconnected). Later... Zoran On Thu, May 12, 2016 at 7:44 AM, Mayuri Tendulkar < mayuri.tendulkar(a)aricent.com> wrote: > Hi Zoran > > > > Can you please update on this? > > > > Can we build using debug FSP and gdb enabling? > > > > Regards > > Mayuri > > > > *From:* Mayuri Tendulkar > *Sent:* 11 May 2016 10:02 > *To:* 'Zoran Stojsavljevic' <zoran.stojsavljevic(a)gmail.com> > *Cc:* coreboot(a)coreboot.org > *Subject:* Re: [coreboot] Coreboot image and seabios payload with debug > symbols > > > > Hi Zoran > > > > Please find responses: > > > > [1] When you do refer to *"**Intel system debugger",* do you refer to > INTEL ITP2 debugger, with Blue Box XDP 60 pin HW connector ( > http://m.eet.com/media/1073715/JTAG_101_fig5.jpg)? > > > > This is Intel® ITP-XDP3. > https://software.intel.com/sites/default/files/managed/45/19/10-jtag-debugg… > > > > > > [2] For which CPU/SoC/platform you would like to use [1]? – This I am > currently using for Minnowboard Turbot (E3826 dual core) > > > > [3] Seems that you did copy some debug excerpt from some INTEL document... > I guess, this one is public one. Could you, please, attach this (if?) > public document to this @ thread for our review, or either pass to us www > pointer to this document? > > > > This can be found from Intel system debugger use guide. > > https://software.intel.com/en-us/node/592929- check section debugging > basics > > > > Regards > > Mayuri > > > > > > *From:* Zoran Stojsavljevic [mailto:zoran.stojsavljevic@gmail.com > <zoran.stojsavljevic(a)gmail.com>] > *Sent:* 10 May 2016 23:15 > *To:* Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com> > *Cc:* coreboot(a)coreboot.org > *Subject:* Re: [coreboot] Coreboot image and seabios payload with debug > symbols > > > > Hello Mayuri, > > > > Few questions, may I? > > > > [1] When you do refer to *"**Intel system debugger",* do you refer to > INTEL ITP2 debugger, with Blue Box XDP 60 pin HW connector ( > http://m.eet.com/media/1073715/JTAG_101_fig5.jpg)? > > > > [2] For which CPU/SoC/platform you would like to use [1]? > > > > [3] Seems that you did copy some debug excerpt from some INTEL document... > I guess, this one is public one. Could you, please, attach this (if?) > public document to this @ thread for our review, or either pass to us www > pointer to this document? > > > > Thank you, > > Zoran > > > > On Tue, May 10, 2016 at 8:22 AM, Mayuri Tendulkar < > mayuri.tendulkar(a)aricent.com> wrote: > > Hi > > > > I want to use Intel system debugger to do coreboot source level debugging. > > > > So I need below. Can you please help me in this? > > To debug your software using source code you need to load debug > information that is used to map the program in target memory to the > original source files. To do this the debugger needs the following: > > - A program loaded in target memory that has been compiled with debug > information > - The load address of the program in target memory > - The program binary file (executable file) > - Debug information file for the program binary (also referred to as > "symbols") > - Original program source code > > Regards > > Mayuri > > "DISCLAIMER: This message is proprietary to Aricent and is intended solely > for the use of the individual to whom it is addressed. It may contain > privileged or confidential information and should not be circulated or used > for any purpose other than for what it is intended. If you have received > this message in error, please notify the originator immediately. If you are > not the intended recipient, you are notified that you are strictly > prohibited from using, copying, altering, or disclosing the contents of > this message. Aricent accepts no responsibility for loss or damage arising > from the use of the information transmitted by this email including damage > from virus." > > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot > > > "DISCLAIMER: This message is proprietary to Aricent and is intended solely > for the use of the individual to whom it is addressed. It may contain > privileged or confidential information and should not be circulated or used > for any purpose other than for what it is intended. If you have received > this message in error, please notify the originator immediately. If you are > not the intended recipient, you are notified that you are strictly > prohibited from using, copying, altering, or disclosing the contents of > this message. Aricent accepts no responsibility for loss or damage arising > from the use of the information transmitted by this email including damage > from virus." >

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Re: [coreboot] Coreboot image and seabios payload with debug symbols
by Mayuri Tendulkar 12 May '16

12 May '16

Hi Zoran Can you please update on this? Can we build using debug FSP and gdb enabling? Regards Mayuri From: Mayuri Tendulkar Sent: 11 May 2016 10:02 To: 'Zoran Stojsavljevic' <zoran.stojsavljevic(a)gmail.com> Cc: coreboot(a)coreboot.org Subject: RE: [coreboot] Coreboot image and seabios payload with debug symbols Hi Zoran Please find responses: [1] When you do refer to "Intel system debugger", do you refer to INTEL ITP2 debugger, with Blue Box XDP 60 pin HW connector (http://m.eet.com/media/1073715/JTAG_101_fig5.jpg)? This is Intel® ITP-XDP3. https://software.intel.com/sites/default/files/managed/45/19/10-jtag-debugg… [2] For which CPU/SoC/platform you would like to use [1]? – This I am currently using for Minnowboard Turbot (E3826 dual core) [3] Seems that you did copy some debug excerpt from some INTEL document... I guess, this one is public one. Could you, please, attach this (if?) public document to this @ thread for our review, or either pass to us www pointer to this document? This can be found from Intel system debugger use guide. https://software.intel.com/en-us/node/592929- check section debugging basics Regards Mayuri From: Zoran Stojsavljevic [mailto:zoran.stojsavljevic@gmail.com] Sent: 10 May 2016 23:15 To: Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com<mailto:mayuri.tendulkar@aricent.com>> Cc: coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> Subject: Re: [coreboot] Coreboot image and seabios payload with debug symbols Hello Mayuri, Few questions, may I? [1] When you do refer to "Intel system debugger", do you refer to INTEL ITP2 debugger, with Blue Box XDP 60 pin HW connector (http://m.eet.com/media/1073715/JTAG_101_fig5.jpg)? [2] For which CPU/SoC/platform you would like to use [1]? [3] Seems that you did copy some debug excerpt from some INTEL document... I guess, this one is public one. Could you, please, attach this (if?) public document to this @ thread for our review, or either pass to us www pointer to this document? Thank you, Zoran [https://ssl.gstatic.com/ui/v1/icons/mail/images/cleardot.gif] On Tue, May 10, 2016 at 8:22 AM, Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com<mailto:mayuri.tendulkar@aricent.com>> wrote: Hi I want to use Intel system debugger to do coreboot source level debugging. So I need below. Can you please help me in this? To debug your software using source code you need to load debug information that is used to map the program in target memory to the original source files. To do this the debugger needs the following: * A program loaded in target memory that has been compiled with debug information * The load address of the program in target memory * The program binary file (executable file) * Debug information file for the program binary (also referred to as "symbols") * Original program source code Regards Mayuri "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." -- coreboot mailing list: coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> https://www.coreboot.org/mailman/listinfo/coreboot "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus."

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coreboot clock drift
by Jacob Mattfield 11 May '16

11 May '16

Hi there, I'm very new to coreboot and I'm having an issue with our system clock drifting. We are working with both vanilla Coreboot and Sage's BSP version of Coreboot. The system clock tends to run about 15% slow. I searched through your archives and was able to find a fix for the southbridge/amd/sb700 but I'm using the southbridge/amd/agesa. A colleague of mine attempted to solve this issue a couple years ago but was unable to find a solution, I'm hoping that somewhere down the line a solution has been found. I'm working on the asrock-imb-a180 machine, and I'm wondering if anyone here has worked with agesa or is familiar with this issue. Best Regards, Jake Mattfield References: https://www.coreboot.org/pipermail/coreboot-gerrit/2015-November/036461.html https://www.coreboot.org/pipermail/coreboot/2014-November/078881.html

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Re: [coreboot] Coreboot image and seabios payload with debug symbols
by Mayuri Tendulkar 11 May '16

11 May '16

Hi Zoran Please find responses: [1] When you do refer to "Intel system debugger", do you refer to INTEL ITP2 debugger, with Blue Box XDP 60 pin HW connector (http://m.eet.com/media/1073715/JTAG_101_fig5.jpg)? This is Intel® ITP-XDP3. https://software.intel.com/sites/default/files/managed/45/19/10-jtag-debugg… [2] For which CPU/SoC/platform you would like to use [1]? – This I am currently using for Minnowboard Turbot (E3826 dual core) [3] Seems that you did copy some debug excerpt from some INTEL document... I guess, this one is public one. Could you, please, attach this (if?) public document to this @ thread for our review, or either pass to us www pointer to this document? This can be found from Intel system debugger use guide. https://software.intel.com/en-us/node/592929- check section debugging basics Regards Mayuri From: Zoran Stojsavljevic [mailto:zoran.stojsavljevic@gmail.com] Sent: 10 May 2016 23:15 To: Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com> Cc: coreboot(a)coreboot.org Subject: Re: [coreboot] Coreboot image and seabios payload with debug symbols Hello Mayuri, Few questions, may I? [1] When you do refer to "Intel system debugger", do you refer to INTEL ITP2 debugger, with Blue Box XDP 60 pin HW connector (http://m.eet.com/media/1073715/JTAG_101_fig5.jpg)? [2] For which CPU/SoC/platform you would like to use [1]? [3] Seems that you did copy some debug excerpt from some INTEL document... I guess, this one is public one. Could you, please, attach this (if?) public document to this @ thread for our review, or either pass to us www pointer to this document? Thank you, Zoran [https://ssl.gstatic.com/ui/v1/icons/mail/images/cleardot.gif] On Tue, May 10, 2016 at 8:22 AM, Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com<mailto:mayuri.tendulkar@aricent.com>> wrote: Hi I want to use Intel system debugger to do coreboot source level debugging. So I need below. Can you please help me in this? To debug your software using source code you need to load debug information that is used to map the program in target memory to the original source files. To do this the debugger needs the following: * A program loaded in target memory that has been compiled with debug information * The load address of the program in target memory * The program binary file (executable file) * Debug information file for the program binary (also referred to as "symbols") * Original program source code Regards Mayuri "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." -- coreboot mailing list: coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> https://www.coreboot.org/mailman/listinfo/coreboot "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus."

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ASUS KFSN4-DRE (K8) Automated Test Failure [master]
by Raptor Engineering Automated Coreboot Test Stand 11 May '16

11 May '16

The ASUS KFSN4-DRE (K8) fails verification for branch master as of commit a486af46b2a5d49b05bfc89a876b5c800eadbe69 The following tests failed: BOOT_FAILURE Commits since last successful test: a486af4 soc/qualcomm/ipq40xx: Add coreboot Table entry for serial console 4df1e0a google/gale: Enable Giga Device SPI flash support 8ce14a7 soc/qualcomm/ipq40xx: Return NULL for cbmem_top if DRAM is not initialized 9f1e0c5 google/gale: set the correct GPIOs for recovery and dev. 10c3749 soc/qualcomm/ipq40xx: Update memory map to align to ipq40xx <1 commits skipped> fa92768 soc/qualcomm/ipq40xx: Add config option for SBL utils path 3bbd901 google/gale: Initial commit for Gale board support dc17d2d soc/qualcomm/ipq40xx: Update the list of MBNs needed for this SoC a6935c2 soc/qualcomm/ipq40xx: Initial commit for IPQ40xx SoC support c84e2fe 3rdparty/blobs: add more Qualcomm stubs See attached log for details This message was automatically generated from Raptor Engineering's ASUS KFSN4-DRE (K8) test stand Want to test on your own equipment? Check out https://www.raptorengineeringinc.com/content/REACTS/intro.html Raptor Engineering also offers coreboot consulting services! Please visit https://www.raptorengineeringinc.com for more information Please contact Timothy Pearson at Raptor Engineering <tpearson(a)raptorengineeringinc.com> regarding any issues stemming from this notification

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Re: [coreboot] Coreboot image and seabios payload with debug symbols
by Zoran Stojsavljevic 10 May '16

10 May '16

Hello Mayuri, Few questions, may I? [1] When you do refer to *"**Intel system debugger",* do you refer to INTEL ITP2 debugger, with Blue Box XDP 60 pin HW connector ( http://m.eet.com/media/1073715/JTAG_101_fig5.jpg)? [2] For which CPU/SoC/platform you would like to use [1]? [3] Seems that you did copy some debug excerpt from some INTEL document... I guess, this one is public one. Could you, please, attach this (if?) public document to this @ thread for our review, or either pass to us www pointer to this document? Thank you, Zoran On Tue, May 10, 2016 at 8:22 AM, Mayuri Tendulkar < mayuri.tendulkar(a)aricent.com> wrote: > Hi > > > > I want to use Intel system debugger to do coreboot source level debugging. > > > > So I need below. Can you please help me in this? > > To debug your software using source code you need to load debug > information that is used to map the program in target memory to the > original source files. To do this the debugger needs the following: > > - A program loaded in target memory that has been compiled with debug > information > - The load address of the program in target memory > - The program binary file (executable file) > - Debug information file for the program binary (also referred to as > "symbols") > - Original program source code > > Regards > > Mayuri > "DISCLAIMER: This message is proprietary to Aricent and is intended solely > for the use of the individual to whom it is addressed. It may contain > privileged or confidential information and should not be circulated or used > for any purpose other than for what it is intended. If you have received > this message in error, please notify the originator immediately. If you are > not the intended recipient, you are notified that you are strictly > prohibited from using, copying, altering, or disclosing the contents of > this message. Aricent accepts no responsibility for loss or damage arising > from the use of the information transmitted by this email including damage > from virus." > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot >

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New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com 10 May '16

10 May '16

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 10 new defect(s) introduced to coreboot found with Coverity Scan. 120 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 10 of 10 defect(s) ** CID 1355175: Control flow issues (STRAY_SEMICOLON) /src/soc/intel/apollolake/lpc.c: 61 in lpc_init() ________________________________________________________________________________________________________ *** CID 1355175: Control flow issues (STRAY_SEMICOLON) /src/soc/intel/apollolake/lpc.c: 61 in lpc_init() 55 } 56 57 scnt = pci_read_config8(dev, REG_SERIRQ_CTL); 58 scnt &= ~(SCNT_EN | SCNT_MODE); 59 if (cfg->serirq_mode == SERIRQ_QUIET) 60 scnt |= SCNT_EN; >>> CID 1355175: Control flow issues (STRAY_SEMICOLON) >>> An "if" statement with no "then" or "else" is suspicious. 61 else if (cfg->serirq_mode == SERIRQ_CONTINUOUS); 62 scnt |= SCNT_EN | SCNT_MODE; 63 pci_write_config8(dev, REG_SERIRQ_CTL, scnt); 64 } 65 66 static void soc_lpc_add_io_resources(device_t dev) ** CID 1355174: Memory - corruptions (OVERRUN) /3rdparty/arm-trusted-firmware/plat/rockchip/rk3399/drivers/pmu/pmu.c: 184 in cores_pwr_domain_on() ________________________________________________________________________________________________________ *** CID 1355174: Memory - corruptions (OVERRUN) /3rdparty/arm-trusted-firmware/plat/rockchip/rk3399/drivers/pmu/pmu.c: 184 in cores_pwr_domain_on() 178 cpus_power_domain_off(cpu, core_pwr_pd); 179 } 180 } 181 182 static int cores_pwr_domain_on(unsigned long mpidr, uint64_t entrypoint) 183 { >>> CID 1355174: Memory - corruptions (OVERRUN) >>> Assigning: "cpu_id" = "plat_core_pos_by_mpidr(mpidr)". The value of "cpu_id" is now -1. 184 uint32_t cpu_id = plat_core_pos_by_mpidr(mpidr); 185 186 assert(cpuson_flags[cpu_id] == 0); 187 cpuson_flags[cpu_id] = PMU_CPU_HOTPLUG; 188 cpuson_entry_point[cpu_id] = entrypoint; 189 dsb(); ** CID 1355173: Memory - illegal accesses (OVERRUN) /3rdparty/arm-trusted-firmware/plat/rockchip/rk3399/drivers/pmu/pmu.c: 186 in cores_pwr_domain_on() ________________________________________________________________________________________________________ *** CID 1355173: Memory - illegal accesses (OVERRUN) /3rdparty/arm-trusted-firmware/plat/rockchip/rk3399/drivers/pmu/pmu.c: 186 in cores_pwr_domain_on() 180 } 181 182 static int cores_pwr_domain_on(unsigned long mpidr, uint64_t entrypoint) 183 { 184 uint32_t cpu_id = plat_core_pos_by_mpidr(mpidr); 185 >>> CID 1355173: Memory - illegal accesses (OVERRUN) >>> Overrunning array "cpuson_flags" of 6 4-byte elements at element index 4294967295 (byte offset 17179869180) using index "cpu_id" (which evaluates to 4294967295). 186 assert(cpuson_flags[cpu_id] == 0); 187 cpuson_flags[cpu_id] = PMU_CPU_HOTPLUG; 188 cpuson_entry_point[cpu_id] = entrypoint; 189 dsb(); 190 191 cpus_power_domain_on(cpu_id); ** CID 1355172: Memory - corruptions (OVERRUN) /3rdparty/arm-trusted-firmware/plat/rockchip/rk3399/drivers/pmu/pmu.c: 188 in cores_pwr_domain_on() ________________________________________________________________________________________________________ *** CID 1355172: Memory - corruptions (OVERRUN) /3rdparty/arm-trusted-firmware/plat/rockchip/rk3399/drivers/pmu/pmu.c: 188 in cores_pwr_domain_on() 182 static int cores_pwr_domain_on(unsigned long mpidr, uint64_t entrypoint) 183 { 184 uint32_t cpu_id = plat_core_pos_by_mpidr(mpidr); 185 186 assert(cpuson_flags[cpu_id] == 0); 187 cpuson_flags[cpu_id] = PMU_CPU_HOTPLUG; >>> CID 1355172: Memory - corruptions (OVERRUN) >>> Overrunning array "cpuson_entry_point" of 6 8-byte elements at element index 4294967295 (byte offset 34359738360) using index "cpu_id" (which evaluates to 4294967295). 188 cpuson_entry_point[cpu_id] = entrypoint; 189 dsb(); 190 191 cpus_power_domain_on(cpu_id); 192 193 return 0; ** CID 1355171: Integer handling issues (NO_EFFECT) /src/soc/rockchip/common/spi.c: 126 in rockchip_spi_init() ________________________________________________________________________________________________________ *** CID 1355171: Integer handling issues (NO_EFFECT) /src/soc/rockchip/common/spi.c: 126 in rockchip_spi_init() 120 assert(clk_div * hz == SPI_SRCCLK_HZ && !(clk_div & 1)); 121 write32(&regs->baudr, clk_div); 122 } 123 124 void rockchip_spi_init(unsigned int bus, unsigned int speed_hz) 125 { >>> CID 1355171: Integer handling issues (NO_EFFECT) >>> This greater-than-or-equal-to-zero comparison of an unsigned value is always true. "bus >= 0U". 126 assert(bus >= 0 && bus < ARRAY_SIZE(rockchip_spi_slaves)); 127 struct rockchip_spi *regs = rockchip_spi_slaves[bus].regs; 128 unsigned int ctrlr0 = 0; 129 130 rkclk_configure_spi(bus, SPI_SRCCLK_HZ); 131 rockchip_spi_enable_chip(regs, 0); ** CID 1355170: Memory - illegal accesses (NEGATIVE_RETURNS) /3rdparty/arm-trusted-firmware/plat/rockchip/rk3399/drivers/pmu/pmu.c: 186 in cores_pwr_domain_on() ________________________________________________________________________________________________________ *** CID 1355170: Memory - illegal accesses (NEGATIVE_RETURNS) /3rdparty/arm-trusted-firmware/plat/rockchip/rk3399/drivers/pmu/pmu.c: 186 in cores_pwr_domain_on() 180 } 181 182 static int cores_pwr_domain_on(unsigned long mpidr, uint64_t entrypoint) 183 { 184 uint32_t cpu_id = plat_core_pos_by_mpidr(mpidr); 185 >>> CID 1355170: Memory - illegal accesses (NEGATIVE_RETURNS) >>> Using variable "cpu_id" as an index to array "cpuson_flags". 186 assert(cpuson_flags[cpu_id] == 0); 187 cpuson_flags[cpu_id] = PMU_CPU_HOTPLUG; 188 cpuson_entry_point[cpu_id] = entrypoint; 189 dsb(); 190 191 cpus_power_domain_on(cpu_id); ** CID 1355169: Incorrect expression (COPY_PASTE_ERROR) /src/soc/rockchip/rk3399/clock.c: 371 in rkclk_init() ________________________________________________________________________________________________________ *** CID 1355169: Incorrect expression (COPY_PASTE_ERROR) /src/soc/rockchip/rk3399/clock.c: 371 in rkclk_init() 365 /* perilp1 hclk select gpll as source */ 366 hclk_div = GPLL_HZ / PERILP1_HCLK_HZ - 1; 367 assert((hclk_div + 1) * PERILP1_HCLK_HZ == 368 GPLL_HZ && (hclk_div < 0x1f)); 369 370 pclk_div = PERILP1_HCLK_HZ / PERILP1_HCLK_HZ - 1; >>> CID 1355169: Incorrect expression (COPY_PASTE_ERROR) >>> "pclk_div" in "pclk_div + 1U" looks like a copy-paste error. 371 assert((pclk_div + 1) * PERILP1_HCLK_HZ == 372 PERILP1_HCLK_HZ && (hclk_div < 0x7)); 373 374 write32(&cru_ptr->clksel_con[25], 375 RK_CLRSETBITS(PCLK_PERILP1_DIV_CON_MASK << 376 PCLK_PERILP1_DIV_CON_SHIFT | ** CID 1355168: (CONSTANT_EXPRESSION_RESULT) /src/soc/rockchip/rk3399/clock.c: 483 in rkclk_configure_spi() /src/soc/rockchip/rk3399/clock.c: 498 in rkclk_configure_spi() /src/soc/rockchip/rk3399/clock.c: 502 in rkclk_configure_spi() ________________________________________________________________________________________________________ *** CID 1355168: (CONSTANT_EXPRESSION_RESULT) /src/soc/rockchip/rk3399/clock.c: 483 in rkclk_configure_spi() 477 case 0: 478 write32(&cru_ptr->clksel_con[59], 479 SPI_CLK_REG_VALUE(0, src_clk_div)); 480 break; 481 case 1: 482 write32(&cru_ptr->clksel_con[59], >>> CID 1355168: (CONSTANT_EXPRESSION_RESULT) >>> "((65280 /* (CLK_SPI_PLL_SEL_MASK << CLK_SPI1_PLL_SEL_SHIFT) | (CLK_SPI_PLL_DIV_CON_MASK << CLK_SPI1_PLL_DIV_CON_SHIFT) */) | ((32768 /* CLK_SPI_PLL_SEL_GPLL << CLK_SPI1_PLL_SEL_SHIFT */) | (src_clk_div - 1 << CLK_SPI1_PLL_DIV_CON_SHIFT))) << 16" is 0xffffffffff000000 regardless of the values of its operands. This occurs as the bitwise first operand of '|'. 483 SPI_CLK_REG_VALUE(1, src_clk_div)); 484 break; 485 case 2: 486 write32(&cru_ptr->clksel_con[60], 487 SPI_CLK_REG_VALUE(2, src_clk_div)); 488 break; /src/soc/rockchip/rk3399/clock.c: 498 in rkclk_configure_spi() 492 SPI3_DIV_CON_MASK << SPI3_DIV_CON_SHIFT, 493 SPI3_PLL_SEL_PPLL << SPI3_PLL_SEL_SHIFT | 494 (src_clk_div - 1) << SPI3_DIV_CON_SHIFT)); 495 break; 496 case 4: 497 write32(&cru_ptr->clksel_con[60], >>> CID 1355168: (CONSTANT_EXPRESSION_RESULT) >>> "((65280 /* (CLK_SPI_PLL_SEL_MASK << CLK_SPI4_PLL_SEL_SHIFT) | (CLK_SPI_PLL_DIV_CON_MASK << CLK_SPI4_PLL_DIV_CON_SHIFT) */) | ((32768 /* CLK_SPI_PLL_SEL_GPLL << CLK_SPI4_PLL_SEL_SHIFT */) | (src_clk_div - 1 << CLK_SPI4_PLL_DIV_CON_SHIFT))) << 16" is 0xffffffffff000000 regardless of the values of its operands. This occurs as the bitwise first operand of '|'. 498 SPI_CLK_REG_VALUE(4, src_clk_div)); 499 break; 500 case 5: 501 write32(&cru_ptr->clksel_con[58], 502 SPI_CLK_REG_VALUE(5, src_clk_div)); 503 break; /src/soc/rockchip/rk3399/clock.c: 502 in rkclk_configure_spi() 496 case 4: 497 write32(&cru_ptr->clksel_con[60], 498 SPI_CLK_REG_VALUE(4, src_clk_div)); 499 break; 500 case 5: 501 write32(&cru_ptr->clksel_con[58], >>> CID 1355168: (CONSTANT_EXPRESSION_RESULT) >>> "((65280 /* (CLK_SPI_PLL_SEL_MASK << CLK_SPI5_PLL_SEL_SHIFT) | (CLK_SPI_PLL_DIV_CON_MASK << CLK_SPI5_PLL_DIV_CON_SHIFT) */) | ((32768 /* CLK_SPI_PLL_SEL_GPLL << CLK_SPI5_PLL_SEL_SHIFT */) | (src_clk_div - 1 << CLK_SPI5_PLL_DIV_CON_SHIFT))) << 16" is 0xffffffffff000000 regardless of the values of its operands. This occurs as the bitwise first operand of '|'. 502 SPI_CLK_REG_VALUE(5, src_clk_div)); 503 break; 504 default: 505 printk(BIOS_ERR, "do not support this spi bus\n"); 506 } 507 } ** CID 1355167: (CONSTANT_EXPRESSION_RESULT) /src/soc/rockchip/rk3399/clock.c: 555 in rkclk_configure_i2c() /src/soc/rockchip/rk3399/clock.c: 559 in rkclk_configure_i2c() /src/soc/rockchip/rk3399/clock.c: 563 in rkclk_configure_i2c() ________________________________________________________________________________________________________ *** CID 1355167: (CONSTANT_EXPRESSION_RESULT) /src/soc/rockchip/rk3399/clock.c: 555 in rkclk_configure_i2c() 549 case 4: 550 write32(&pmucru_ptr->pmucru_clksel[3], 551 PMU_I2C_CLK_REG_VALUE(4, src_clk_div)); 552 break; 553 case 5: 554 write32(&cru_ptr->clksel_con[61], >>> CID 1355167: (CONSTANT_EXPRESSION_RESULT) >>> "((65280 /* (I2C_DIV_CON_MASK << CLK_I2C5_DIV_CON_SHIFT) | (CLK_I2C_PLL_SEL_MASK << CLK_I2C5_PLL_SEL_SHIFT) */) | ((src_clk_div - 1 << CLK_I2C5_DIV_CON_SHIFT) | (32768 /* CLK_I2C_PLL_SEL_GPLL << CLK_I2C5_PLL_SEL_SHIFT */))) << 16" is 0xffffffffff000000 regardless of the values of its operands. This occurs as the bitwise first operand of '|'. 555 I2C_CLK_REG_VALUE(5, src_clk_div)); 556 break; 557 case 6: 558 write32(&cru_ptr->clksel_con[62], 559 I2C_CLK_REG_VALUE(6, src_clk_div)); 560 break; /src/soc/rockchip/rk3399/clock.c: 559 in rkclk_configure_i2c() 553 case 5: 554 write32(&cru_ptr->clksel_con[61], 555 I2C_CLK_REG_VALUE(5, src_clk_div)); 556 break; 557 case 6: 558 write32(&cru_ptr->clksel_con[62], >>> CID 1355167: (CONSTANT_EXPRESSION_RESULT) >>> "((65280 /* (I2C_DIV_CON_MASK << CLK_I2C6_DIV_CON_SHIFT) | (CLK_I2C_PLL_SEL_MASK << CLK_I2C6_PLL_SEL_SHIFT) */) | ((src_clk_div - 1 << CLK_I2C6_DIV_CON_SHIFT) | (32768 /* CLK_I2C_PLL_SEL_GPLL << CLK_I2C6_PLL_SEL_SHIFT */))) << 16" is 0xffffffffff000000 regardless of the values of its operands. This occurs as the bitwise first operand of '|'. 559 I2C_CLK_REG_VALUE(6, src_clk_div)); 560 break; 561 case 7: 562 write32(&cru_ptr->clksel_con[63], 563 I2C_CLK_REG_VALUE(7, src_clk_div)); 564 break; /src/soc/rockchip/rk3399/clock.c: 563 in rkclk_configure_i2c() 557 case 6: 558 write32(&cru_ptr->clksel_con[62], 559 I2C_CLK_REG_VALUE(6, src_clk_div)); 560 break; 561 case 7: 562 write32(&cru_ptr->clksel_con[63], >>> CID 1355167: (CONSTANT_EXPRESSION_RESULT) >>> "((65280 /* (I2C_DIV_CON_MASK << CLK_I2C7_DIV_CON_SHIFT) | (CLK_I2C_PLL_SEL_MASK << CLK_I2C7_PLL_SEL_SHIFT) */) | ((src_clk_div - 1 << CLK_I2C7_DIV_CON_SHIFT) | (32768 /* CLK_I2C_PLL_SEL_GPLL << CLK_I2C7_PLL_SEL_SHIFT */))) << 16" is 0xffffffffff000000 regardless of the values of its operands. This occurs as the bitwise first operand of '|'. 563 I2C_CLK_REG_VALUE(7, src_clk_div)); 564 break; 565 case 8: 566 write32(&pmucru_ptr->pmucru_clksel[2], 567 PMU_I2C_CLK_REG_VALUE(8, src_clk_div)); 568 break; ** CID 1355166: Integer handling issues (CONSTANT_EXPRESSION_RESULT) /src/soc/rockchip/rk3399/clock.c: 592 in rkclk_configure_saradc() ________________________________________________________________________________________________________ *** CID 1355166: Integer handling issues (CONSTANT_EXPRESSION_RESULT) /src/soc/rockchip/rk3399/clock.c: 592 in rkclk_configure_saradc() 586 587 /* saradc src clk from 24MHz */ 588 src_clk_div = 24 * MHz / hz; 589 assert((src_clk_div - 1 < 255) && (src_clk_div * hz == 24 * MHz)); 590 591 write32(&cru_ptr->clksel_con[26], >>> CID 1355166: Integer handling issues (CONSTANT_EXPRESSION_RESULT) >>> "((65280 /* CLK_SARADC_DIV_CON_MASK << CLK_SARADC_DIV_CON_SHIFT */) | (src_clk_div - 1 << CLK_SARADC_DIV_CON_SHIFT)) << 16" is 0xffffffffff000000 regardless of the values of its operands. This occurs as the bitwise first operand of '|'. 592 RK_CLRSETBITS(CLK_SARADC_DIV_CON_MASK << 593 CLK_SARADC_DIV_CON_SHIFT, 594 (src_clk_div - 1) << CLK_SARADC_DIV_CON_SHIFT)); ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://scan.coverity.com/projects/coreboot?tab=overview To manage Coverity Scan email notifications for "coreboot(a)coreboot.org", click https://scan.coverity.com/subscriptions/edit?email=coreboot%40coreboot.org&…

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Coreboot image and seabios payload with debug symbols
by Mayuri Tendulkar 10 May '16

10 May '16

Hi I want to use Intel system debugger to do coreboot source level debugging. So I need below. Can you please help me in this? To debug your software using source code you need to load debug information that is used to map the program in target memory to the original source files. To do this the debugger needs the following: * A program loaded in target memory that has been compiled with debug information * The load address of the program in target memory * The program binary file (executable file) * Debug information file for the program binary (also referred to as "symbols") * Original program source code Regards Mayuri "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus."

1 0

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coreboot May 2016