coreboot May 2016

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149 discussions

Re: [coreboot] Lenovo X200 running Coreboot drains 3-4W more power than with Vendor BIOS
by Daniel Kulesz 10 May '16

10 May '16

On Sat, 7 May 2016 15:53:47 +0200 Zoran Stojsavljevic <zoran.stojsavljevic(a)gmail.com> wrote: > > @Zoran: I also have an X220 (2nd gen Core I5) on which I did not > undertake any Coreboot experiments yet. But I > > suppose you are rather asking for much newer CPUs from the 6th and 7th > generation? > > > > Cheers, Daniel > > Hello Daniel, > > Second generation CORE is SNB. CPUID something like 0x20xyz. CORE 2nd gen. > was released Y2011. > Third generation CORE is IVB. CPUID something like 0x30xyz. Core 3rd gen. > was released Y2012. > > What I am talking/pointing ot about is the following: > *Fourth generation CORE is HSW. CPUID something like 0x40651 (i5 4300U) - > HP 840 G1 - one of my laptops. Released Y2013.* > *Sixth generation CORE is SKL. CPUID something like 0x606E3 (i5 6200U) - HP > 450 G3 - another of my laptops. Released Y2015.* > > 4th (HSW-U) and 6th (SKL-U) generations of CPUs in laptops: these are ones > I am talking about/pointing to (don't think CORE 5th gen. is important). > > Sorry I am late with Re:. Hi Zoran, You are welcome! But I don't have any of these newer laptops and afaik Coreboot does not support many of them, either. Especially the newer Thinkpads (T/X240+) are not supported. But sure, if anybody has one of these machines doing similar experiments would really make sense. I still wonder why I didn't read or hear about any complaints about running Libreboot/Coreboot on a X200 since the difference of the missing C4 mode (by default at least) is so striking. Cheers, Daniel

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Re: [coreboot] Question about Intel's documentation notations
by Rafael Machado 09 May '16

09 May '16

Thanks Wang! Em seg, 9 de mai de 2016 às 13:59, WANG FEI <wangfei.jimei(a)gmail.com> escreveu: > xxH - xx means these two numbers could be a hex number from 00 - FF, which > is depend on the SoC/processors. > > On Mon, May 9, 2016 at 4:25 PM, Rafael Machado < > rafaelrodrigues.machado(a)gmail.com> wrote: > >> Make sense. Now I saw the notes. Stupid question, sorry. >> >> That about the *xx*H ? >> >> Thanks for the fast response. >> Rafael >> >> Em seg, 9 de mai de 2016 às 12:23, ron minnich <rminnich(a)gmail.com> >> escreveu: >> >>> H means hex, they do that instead of 0x. >>> 2 is footnote 2. >>> >>> The whole H thing goes back 45 years or so and was a failure of vision, >>> AH is a register name and a constant. As are bc, ch, and dh. oops. >>> >>> ron >>> On Mon, May 9, 2016 at 8:19 AM Rafael Machado < >>> rafaelrodrigues.machado(a)gmail.com> wrote: >>> >>>> Hi everyone >>>> >>>> I'm taking a look at the Intel developers guide and there is a notation >>>> there that I didn't understand. >>>> >>>> [image: pasted1] >>>> >>>> Since there are several guys with more experience here, probably >>>> someone can help me. This is the table with the default values of the >>>> registers after a system reset, from Intel Developers Guide, page 2285. >>>> >>>> That does the "H2" means at the attached picture ? >>>> And what toes the xxH3 means too ? >>>> >>>> Thanks and Regards >>>> Rafael R. Machado >>>> >>>> >>>> -- >>>> coreboot mailing list: coreboot(a)coreboot.org >>>> https://www.coreboot.org/mailman/listinfo/coreboot >>> >>> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> https://www.coreboot.org/mailman/listinfo/coreboot >> > >

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Re: [coreboot] Question about Intel's documentation notations
by WANG FEI 09 May '16

09 May '16

xxH - xx means these two numbers could be a hex number from 00 - FF, which is depend on the SoC/processors. On Mon, May 9, 2016 at 4:25 PM, Rafael Machado < rafaelrodrigues.machado(a)gmail.com> wrote: > Make sense. Now I saw the notes. Stupid question, sorry. > > That about the *xx*H ? > > Thanks for the fast response. > Rafael > > Em seg, 9 de mai de 2016 às 12:23, ron minnich <rminnich(a)gmail.com> > escreveu: > >> H means hex, they do that instead of 0x. >> 2 is footnote 2. >> >> The whole H thing goes back 45 years or so and was a failure of vision, >> AH is a register name and a constant. As are bc, ch, and dh. oops. >> >> ron >> On Mon, May 9, 2016 at 8:19 AM Rafael Machado < >> rafaelrodrigues.machado(a)gmail.com> wrote: >> >>> Hi everyone >>> >>> I'm taking a look at the Intel developers guide and there is a notation >>> there that I didn't understand. >>> >>> [image: pasted1] >>> >>> Since there are several guys with more experience here, probably someone >>> can help me. This is the table with the default values of the registers >>> after a system reset, from Intel Developers Guide, page 2285. >>> >>> That does the "H2" means at the attached picture ? >>> And what toes the xxH3 means too ? >>> >>> Thanks and Regards >>> Rafael R. Machado >>> >>> >>> -- >>> coreboot mailing list: coreboot(a)coreboot.org >>> https://www.coreboot.org/mailman/listinfo/coreboot >> >> > -- > coreboot mailing list: coreboot(a)coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot >

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Re: [coreboot] Question about Intel's documentation notations
by Rafael Machado 09 May '16

09 May '16

Make sense. Now I saw the notes. Stupid question, sorry. That about the *xx*H ? Thanks for the fast response. Rafael Em seg, 9 de mai de 2016 às 12:23, ron minnich <rminnich(a)gmail.com> escreveu: > H means hex, they do that instead of 0x. > 2 is footnote 2. > > The whole H thing goes back 45 years or so and was a failure of vision, AH > is a register name and a constant. As are bc, ch, and dh. oops. > > ron > On Mon, May 9, 2016 at 8:19 AM Rafael Machado < > rafaelrodrigues.machado(a)gmail.com> wrote: > >> Hi everyone >> >> I'm taking a look at the Intel developers guide and there is a notation >> there that I didn't understand. >> >> [image: pasted1] >> >> Since there are several guys with more experience here, probably someone >> can help me. This is the table with the default values of the registers >> after a system reset, from Intel Developers Guide, page 2285. >> >> That does the "H2" means at the attached picture ? >> And what toes the xxH3 means too ? >> >> Thanks and Regards >> Rafael R. Machado >> >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> https://www.coreboot.org/mailman/listinfo/coreboot > >

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Re: [coreboot] Question about Intel's documentation notations
by ron minnich 09 May '16

09 May '16

H means hex, they do that instead of 0x. 2 is footnote 2. The whole H thing goes back 45 years or so and was a failure of vision, AH is a register name and a constant. As are bc, ch, and dh. oops. ron On Mon, May 9, 2016 at 8:19 AM Rafael Machado < rafaelrodrigues.machado(a)gmail.com> wrote: > Hi everyone > > I'm taking a look at the Intel developers guide and there is a notation > there that I didn't understand. > > [image: pasted1] > > Since there are several guys with more experience here, probably someone > can help me. This is the table with the default values of the registers > after a system reset, from Intel Developers Guide, page 2285. > > That does the "H2" means at the attached picture ? > And what toes the xxH3 means too ? > > Thanks and Regards > Rafael R. Machado > > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot

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Re: [coreboot] Question about Intel's documentation notations
by Duncan Laurie 09 May '16

09 May '16

Those typically indicate there is a note at the bottom of the table with additional information, corresponding to the superscript number. So you should find a (2) and (3) entry at the bottom of the table explaining that value in more detail. Hopefully. -duncan On Mon, May 9, 2016 at 8:18 AM, Rafael Machado < rafaelrodrigues.machado(a)gmail.com> wrote: > Hi everyone > > I'm taking a look at the Intel developers guide and there is a notation > there that I didn't understand. > > [image: pasted1] > > Since there are several guys with more experience here, probably someone > can help me. This is the table with the default values of the registers > after a system reset, from Intel Developers Guide, page 2285. > > That does the "H2" means at the attached picture ? > And what toes the xxH3 means too ? > > Thanks and Regards > Rafael R. Machado > > > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot >

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Re: [coreboot] Community Meeting
by Rafael Machado 09 May '16

09 May '16

Hi everyone. Thanks David for the tip. I didn't know that. And thanks David for adding the timezone to the calendar I'll try to start a coreboot community here in Brazil. The biggest problem I have for doing this is the lack of material in Portuguese. Is there any place at the website were we can add some translated material at the wiki ? Thanks Rafael Machado Em sáb, 7 de mai de 2016 às 18:27, David Hendricks < david.hendricks(a)gmail.com> escreveu: > If you use Google Calendar, you can click on the "+Google Calendar" button > in the lower right corner to overlay the coreboot calendar events on your > calendar. This can also be used as a way to show events in your timezone. > > On Sat, May 7, 2016 at 11:56 AM, Rafael Machado < > rafaelrodrigues.machado(a)gmail.com> wrote: > >> Hi Zaolin >> >> Would it be possible to add at this calendar the Brazilian timezone ? >> (UTC-3 São Paulo) >> Probably I'm the only one here :), but maybe this can help me to get more >> guys here involved. >> >> Thanks guys >> >> Em qui, 5 de mai de 2016 às 00:52, Kus <kushaldeveloper(a)gmail.com> >> escreveu: >> >>> -----BEGIN PGP SIGNED MESSAGE----- >>> Hash: SHA512 >>> >>> Very nice. Thank you! >>> -----BEGIN PGP SIGNATURE----- >>> Version: APG v1.1.1 >>> >>> iQJRBAEBCgA7BQJXKsM3NBxLdXNoYWwgSGFkYSAoZGV2ZWxvcGVyKSA8a3VzaGFs >>> ZGV2ZWxvcGVyQGdtYWlsLmNvbT4ACgkQJsInd2b1xmO/kg//dJdd19LoXNtZWy0M >>> 1Fzb1h6dVr7Y8+j+wLbLD83lpZm5tKJhljhXgsj6TPP2e6dvgYbeflxH6etMN+th >>> gjOp7vYMmhvrHKc9WKSAOHqqbfNjknX/lBRUkqF/K4uVoYvRZrcwBDhChEpOv/w1 >>> S3vhw7yF9arWJDvzK8bKTInd1rj3+Upqv3f6ESGf1rPOUeqie9I4VDv+3s0eC5H8 >>> 4wKIBZqoqFKh+ZYe42ZXIsmmyq6Fc6i4TLPB7NrAOLW1s4MytJnrMwd+of9J2mQi >>> Urm9IWCaOXsla5Y81bEIj2Zrycu+WcjSkZJs/gXPVo7uQkUpixYDKLaZYeIS8q9r >>> OVMLVmNcj45v56ZdWNm7b2z0suvR6FJInI5V+Snypchg2/NsafCXLQPLmXUOOuKN >>> NNb3bc+9zxi3SNMRsG7sYMWeT5kLPivNorgaD0hy10R+YQqVh3d5j8T5IbqVPIFn >>> qEp7egk2xB3Wowwh7Y0ioXSleuTXd5FKKjoSYItVjwLsr5y3nmveXNi/xpg3w638 >>> eyCSvuv2sbzMM0aRkV9nQWgxXmLZCmabIJLvqjxdSzRtC7P6AYZ3jBd+ARE3vxel >>> UMhZDC/DCx5c3Yzy8dmPi8N+MNZi7ABVzEG898bEUpfUrj8GAtDb/w7H5+TLRHrv >>> DzHnXEzhl8IjtCuZBmgzlvy3A7A= >>> =IU4I >>> -----END PGP SIGNATURE----- >>> >>> >>> -- >>> coreboot mailing list: coreboot(a)coreboot.org >>> https://www.coreboot.org/mailman/listinfo/coreboot >>> >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> https://www.coreboot.org/mailman/listinfo/coreboot >> > >

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Question about Intel's documentation notations
by Rafael Machado 09 May '16

09 May '16

Hi everyone I'm taking a look at the Intel developers guide and there is a notation there that I didn't understand. [image: pasted1] Since there are several guys with more experience here, probably someone can help me. This is the table with the default values of the registers after a system reset, from Intel Developers Guide, page 2285. That does the "H2" means at the attached picture ? And what toes the xxH3 means too ? Thanks and Regards Rafael R. Machado

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Re: [coreboot] Unable to build coreboot with Intel FSP debug binary on BayleyBay
by Kathappan E 09 May '16

09 May '16

Here is final Coreboot image info with debug FSP. Performing operation on 'COREBOOT' region... Name Offset Type Size cbfs master header 0x0 cbfs header 32 fallback/romstage 0x80 stage 29996 config 0x7640 raw 515 revision 0x7880 raw 570 cmos_layout.bin 0x7b00 cmos_layout 1096 fallback/dsdt.aml 0x7f80 raw 12465 payload_config 0xb080 raw 1563 payload_revision 0xb700 raw 267 (empty) 0xb880 null 17944 mrc.cache 0xfec0 mrc_cache 65536 cpu_microcode_blob.bin 0x1ff00 microcode 208896 fallback/ramstage 0x52f80 stage 54702 fallback/payload 0x60580 payload 63348 pci8086,0f31.rom 0x6fd40 optionrom 65536 (empty) 0x7fdc0 null 1245400 fsp.bin 0x1afec0 fsp 294912 (empty) 0x1f7f00 null 31064 bootblock 0x1ff880 bootblock 1560 Built intel/bayleybay_fsp (Bayley Bay CRB (FSP)) Thanks, Kathappan From: Kathappan E Sent: 09 May 2016 12:35 To: 'Aaron Durbin' <adurbin(a)google.com>; 'Zoran Stojsavljevic' <zoran.stojsavljevic(a)gmail.com> Cc: coreboot(a)coreboot.org Subject: RE: [coreboot] Unable to build coreboot with Intel FSP debug binary on BayleyBay Hi Aaron/Zoran, Thank you for your inputs. After adjusting FSP_LOC Kconfig (Intel FSP Binary location in CBFS in menuconfig) variable as it is configured in FSP binary, coreboot is getting build with debug FSP binary. I see the base location of FSP binary using BCT tool as below. Release FSP Binary (BAYTRAIL_FSP_GOLD_004_22-MAY-2015.fd) ==> 0xFFFC0000 Debug FSP Binary (BAYTRAIL_FSP_GOLD_004_22-MAY-2015_DEBUG.fd) ==> 0xFFFB0000 Thanks, Kathappan -----Original Message----- From: Aaron Durbin [mailto:adurbin@google.com] Sent: 06 May 2016 19:47 To: Kathappan E <Kathappan.E(a)LntTechservices.com<mailto:Kathappan.E@LntTechservices.com>> Cc: coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> Subject: Re: [coreboot] Unable to build coreboot with Intel FSP debug binary on BayleyBay On Fri, May 6, 2016 at 12:39 AM, Kathappan E <Kathappan.E(a)lnttechservices.com<mailto:Kathappan.E@lnttechservices.com>> wrote: > Hi all, > > > > I am able to build Coreboot with FSP Baytrail release > binary(BAYTRAIL_FSP_GOLD_004_22-MAY-2015.fd). > > > > But I am unable to build with FSP Baytrail debug binary > (BAYTRAIL_FSP_GOLD_004_22-MAY-2015_DEBUG.fd) and it throws the below > error says that binary size is large and fails to add into image. > > > > The sections containing CBFSes are: COREBOOT > > Performing operation on 'COREBOOT' region... > > Created CBFS (capacity = 2096856 bytes) > > Performing operation on 'COREBOOT' region... > > Performing operation on 'COREBOOT' region... > > CBFS fsp.bin > > Performing operation on 'COREBOOT' region... > > E: Not enough space for content. > > E: Could not add [fsp, 294912 bytes (288 KB)@0x1bff00]; too big? > > E: Failed to add '../intel/fsp/baytrail/BAYTRAIL_FSP_D.fd' into ROM image. > > E: Failed while operating on 'COREBOOT' region! > > E: The image will be left unmodified. > > make: *** [build/coreboot.pre] Error 1 > > > > Can you please anyone help me on this? > You likely need to adjust the FSP_LOC kconfig variable to match the debug FSP binary. Most likely the debug binary is large and not linked at the same address which in this case breaks building because there's not enough flash space. > > > Thanks in advance, > > Kathappan > > L&T Technology Services Ltd > > www.LntTechservices.com<http://www.LntTechservices.com> > > This Email may contain confidential or privileged information for the > intended recipient (s). If you are not the intended recipient, please > do not use or disseminate the information, notify the sender and > delete it from your system. > > > -- > coreboot mailing list: coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> > https://www.coreboot.org/mailman/listinfo/coreboot L&T Technology Services Ltd www.LntTechservices.com<http://www.lnttechservices.com/> This Email may contain confidential or privileged information for the intended recipient (s). If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system.

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Re: [coreboot] Unable to build coreboot with Intel FSP debug binary on BayleyBay
by Kathappan E 09 May '16

09 May '16

Hi Aaron/Zoran, Thank you for your inputs. After adjusting FSP_LOC Kconfig (Intel FSP Binary location in CBFS in menuconfig) variable as it is configured in FSP binary, coreboot is getting build with debug FSP binary. I see the base location of FSP binary using BCT tool as below. Release FSP Binary (BAYTRAIL_FSP_GOLD_004_22-MAY-2015.fd) ==> 0xFFFC0000 Debug FSP Binary (BAYTRAIL_FSP_GOLD_004_22-MAY-2015_DEBUG.fd) ==> 0xFFFB0000 Thanks, Kathappan -----Original Message----- From: Aaron Durbin [mailto:adurbin@google.com] Sent: 06 May 2016 19:47 To: Kathappan E <Kathappan.E(a)LntTechservices.com> Cc: coreboot(a)coreboot.org Subject: Re: [coreboot] Unable to build coreboot with Intel FSP debug binary on BayleyBay On Fri, May 6, 2016 at 12:39 AM, Kathappan E <Kathappan.E(a)lnttechservices.com<mailto:Kathappan.E@lnttechservices.com>> wrote: > Hi all, > > > > I am able to build Coreboot with FSP Baytrail release > binary(BAYTRAIL_FSP_GOLD_004_22-MAY-2015.fd). > > > > But I am unable to build with FSP Baytrail debug binary > (BAYTRAIL_FSP_GOLD_004_22-MAY-2015_DEBUG.fd) and it throws the below > error says that binary size is large and fails to add into image. > > > > The sections containing CBFSes are: COREBOOT > > Performing operation on 'COREBOOT' region... > > Created CBFS (capacity = 2096856 bytes) > > Performing operation on 'COREBOOT' region... > > Performing operation on 'COREBOOT' region... > > CBFS fsp.bin > > Performing operation on 'COREBOOT' region... > > E: Not enough space for content. > > E: Could not add [fsp, 294912 bytes (288 KB)@0x1bff00]; too big? > > E: Failed to add '../intel/fsp/baytrail/BAYTRAIL_FSP_D.fd' into ROM image. > > E: Failed while operating on 'COREBOOT' region! > > E: The image will be left unmodified. > > make: *** [build/coreboot.pre] Error 1 > > > > Can you please anyone help me on this? > You likely need to adjust the FSP_LOC kconfig variable to match the debug FSP binary. Most likely the debug binary is large and not linked at the same address which in this case breaks building because there's not enough flash space. > > > Thanks in advance, > > Kathappan > > L&T Technology Services Ltd > > www.LntTechservices.com<http://www.LntTechservices.com> > > This Email may contain confidential or privileged information for the > intended recipient (s). If you are not the intended recipient, please > do not use or disseminate the information, notify the sender and > delete it from your system. > > > -- > coreboot mailing list: coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> > https://www.coreboot.org/mailman/listinfo/coreboot L&T Technology Services Ltd www.LntTechservices.com<http://www.lnttechservices.com/> This Email may contain confidential or privileged information for the intended recipient (s). If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system.

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coreboot May 2016