May 2016 - coreboot - mail.coreboot.org

autoport segfault on ibexpeak
by Stefan Tauner May 5, 2016

May 5, 2016

Hi, since the rebase of the existing t410s patch to current master was non-trivial (for me anyway) so I gave autoport a shot without knowing that it currently does not support ibexpeak (5 series). This became quite obvious from the output... but that's not the main reason why I am writing (although I'd be interested regrading support for earlier chipsets to autoport) but... 1) autoport segfaults on the t410s with vendor bios and that should definitely be fixed IMHO. 2) about a dozen or so seconds after running autoport my laptop completely locks up. Any ideas why this might happen? Stdio/err is log attached. FWIW autoport also wrote the following log files: -rw-r--r-- 1 root root 329204 May 3 23:24 acpidump.log -rw-r--r-- 1 root root 9464 May 3 23:24 codec#0 -rw-r--r-- 1 root root 3598 May 3 23:24 codec#3 -rw-r--r-- 1 root root 3444 May 3 23:24 cpuinfo.log -rw-r--r-- 1 root root 15925 May 3 23:24 dmidecode.log -rw-r--r-- 1 root root 0 May 3 23:24 ectool.log -rw-r--r-- 1 root root 75 May 3 23:24 input_bustypes.log -rw-r--r-- 1 root root 825285 May 3 23:24 inteltool.log -rw-r--r-- 1 root root 1136 May 3 23:24 ioports.log -rw-r--r-- 1 root root 150333 May 3 23:24 lspci.log -rw-r--r-- 1 root root 160 May 3 23:24 pin_hwC0D0 -rw-r--r-- 1 root root 48 May 3 23:24 pin_hwC0D3 -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Serial prints not coming on Minnowboard Turbot
by Mayuri Tendulkar May 5, 2016

May 5, 2016

Hi I have built coreboot using Minnowmax config file in coreboot with seabios payload. I don't see any serial console prints. Can you please confirm what could be the issue? If I flash Minnowboard Max file given on intel site, everything works fine and I see UEFI shell prompt. Regards Mayuri "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus."

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Community Meeting
by Zaolin May 5, 2016

May 5, 2016

Hi folks, sorry for the late email. I forgot to send out the invitation for Monday CCM. So we will do it on Thursday evening. Normally the meeting will be announced 3-4 days before the next via coreboot ml so that you have time to do your planning. The meeting room is provided by discordapp (the next solution), you need to use chrome/chromium or install a desktop app. The channel can be accessed via link: https://discord.gg/0vhZlDE5b2njfGK7 Every meeting will be documented by a report. The report is published after the meeting via a link the coreboot wiki. More information can be found under the following link: https://www.coreboot.org/Coreboot_community_meeting The only rule in this meeting is to be kind to each other. ### So no flamewar, offence or individual criticism ! ### 3rd Coreboot Community Meeting ==================================================== Date: 05.05.2016 San Francisco time: Begin at 09.00 a.m. Berlin time: Begin at 18.00 p.m. Meeting time: Max. 1 hour. Who is invited: Everyone who is or intends to become developer ! Agenda: ----------- 1) Introduction -> Everyone introduces themselves (Only for new developers). Every developer gives a short overview what he did the last two weeks and what he want to do the next two weeks. (max. 5 min. per person, daily scrum like). 2) News -> Developers with interesting news keep the other up-to-date but no discussion. 3) Maintainer Orga -> Issues -> Requests 4) Project Orga -> Gather topics which need to be discussed or improve the project itself. -> Find tasks and developer which a responsible for a task. 5) Admin Orga -> Access requests -> Questions -> Issues 6) GSoC Orga 7) Other topics which are not on the agenda. 99) Developer Topics / Split Up / Have fun to discuss your idea -> Gather developer topics which seem to be important and interesting to solve. -> Gather groups of developers who are interested in the same topic. -> For deeper information exchange split up in different jitsi meet channels and close meeting. 100) End ===================================================== Best Regards Zaolin

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Re: [coreboot] autoport segfault on ibexpeak
by siro＠das-labor.org May 5, 2016

May 5, 2016

Hello Stefan, As far as I know autoport only supports sandybridge and Ivybridge compatible boards. You are welcome to add support for ibexpeak. You are right it shouldn't segfault or lockup. Kind Regards, Patrick Originalnachricht Von: Stefan Tauner Gesendet: Donnerstag, 5. Mai 2016 00:15 An: coreboot(a)coreboot.org Antwort an: coreboot(a)coreboot.org Betreff: [coreboot] autoport segfault on ibexpeak Hi, since the rebase of the existing t410s patch to current master was non-trivial (for me anyway) so I gave autoport a shot without knowing that it currently does not support ibexpeak (5 series). This became quite obvious from the output... but that's not the main reason why I am writing (although I'd be interested regrading support for earlier chipsets to autoport) but... 1) autoport segfaults on the t410s with vendor bios and that should definitely be fixed IMHO. 2) about a dozen or so seconds after running autoport my laptop completely locks up. Any ideas why this might happen? Stdio/err is log attached. FWIW autoport also wrote the following log files: -rw-r--r-- 1 root root 329204 May 3 23:24 acpidump.log -rw-r--r-- 1 root root 9464 May 3 23:24 codec#0 -rw-r--r-- 1 root root 3598 May 3 23:24 codec#3 -rw-r--r-- 1 root root 3444 May 3 23:24 cpuinfo.log -rw-r--r-- 1 root root 15925 May 3 23:24 dmidecode.log -rw-r--r-- 1 root root 0 May 3 23:24 ectool.log -rw-r--r-- 1 root root 75 May 3 23:24 input_bustypes.log -rw-r--r-- 1 root root 825285 May 3 23:24 inteltool.log -rw-r--r-- 1 root root 1136 May 3 23:24 ioports.log -rw-r--r-- 1 root root 150333 May 3 23:24 lspci.log -rw-r--r-- 1 root root 160 May 3 23:24 pin_hwC0D0 -rw-r--r-- 1 root root 48 May 3 23:24 pin_hwC0D3 -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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New on blogs.coreboot.org: Announcing coreboot 4.4
by WordPress May 2, 2016

May 2, 2016

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Re: [coreboot] Microcode problem with Braswell CPU
by Alexander Böcken May 2, 2016

May 2, 2016

Hello Zoran, I really appreciate your help. I was able to resolve the problem on late Friday. I cannot exactly tell what the reason was, however, I set up a fresh install of coreboot, just using my old .config and microcode. Then I saw that the board gets past the microcode update. I must have introduced a bug somewhere... sorry, for the noise... Now the board stops at TempRamInit in FSP. I'm already using the FSP for Braswell from the Intel link you referenced. The function does not return, but the board shows me post code 0x52. I'm pretty sure the post code comes from FSP because I temporarily redirected all post codes to port 0x84 in the coreboot configuration. From src/drivers/intel/fsp1_1/cache_as_ram.inc I see that TempRamInit gets a pointer to CAR_init_params which is generated from .config. Those values seem okay. #define CONFIG_CPU_MICROCODE_CBFS_LOC 0xFFE68400 #define CONFIG_CPU_MICROCODE_CBFS_LEN 0x10C00 #define CONFIG_ROM_SIZE 0x200000 Has anyone any experiences with FSP post codes? I can't find any documentation about that. Thank you, Alex

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Re: [coreboot] coreboot 4.4 release coming soon
by Paul Kocialkowski May 1, 2016

May 1, 2016

Here is a status report for the chromebooks I'm using: * veyron_speedy Boots fine with today's HEAD on a standard use case. However, my particular use case requires https://review.coreboot.org/#/c/14472/ which is trivial. * nyan_big Building with CHROMEOS requires https://review.coreboot.org/#/c/14474/ otherwise it hangs at bootblock. Merging the libpayload config before the release would also be nice: https://rev iew.coreboot.org/#/c/14472/ With those patches applied, the display is mangled on depthcharge as seen on: ht tp://download.paulk.fr/coreboot/nyan_big/nyan_big-display.jpg A boot log is attached to this email. It would be useful if someone else could try and let me know whether they can duplicate the issue. I'm unsure the issue comes from coreboot, depthcharge or my modifications to depthcharge and vboot. The repositories I'm using are: http://git.code.paulk.fr/gitweb/?p=coreboot.git;a=summary http://git.code.paulk.fr/gitweb/?p=depthcharge.git;a=summary http://git.code.paulk.fr/gitweb/?p=vboot.git;a=summary with branch libreboot-next Cheers, -- Paul Kocialkowski, low-level free software developer on embedded devices Website: https://www.paulk.fr/ Coding blog: https://code.paulk.fr/ Git repositories: https://git.paulk.fr/ https://git.code.paulk.fr/

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Lenovo X200 running Coreboot drains 3-4W more power than with Vendor BIOS
by Daniel Kulesz May 1, 2016

May 1, 2016

Hi, I was wondering why my Lenovo X200 had such a short battery lifetime when running Libreboot/Coreboot, so I did a few measurements using the following hardware configuration: X200 with P8700 CPU 8GB RAM LED Display (yes, one of the rare ones) OCZ Trion SSD (unused, just idling) Wifi and WWAN removed Battery removed Ubuntu MATE 16.04 Live running from an USB thumb drive No tweaking with powertop or such I kept this configuration unchanged except for the BIOS and waited 5 minutes after booting, so the system could settle. Then I measured power consumption both at full brightness and at minimum brightness using a conventional power meter (EKM 365) which was plugged between the AC adapter and the power socket in the wall. I obtained the following numbers: Vendor BIOS: 7,5W (lowest) to 10W (highest) Libreboot 20150518 (using the precompiled binary binary): 13,3W (lowest) to 16,1W (highest) Latest Coreboot, config attached (80a3df260767a6d9ad34b61572d483579c21476c): 10,4W (lowest) to 13,4W (highest) While Libreboot performs much worse than Coreboot, Coreboot still eats around 3W extra when compared with the vendor BIOS. In other words: Coreboot consumes around 30-40% more juice than the vendor BIOS which is a very sad result for an ultraportable notebook. Is this a known issue? Has someone else tried the same and obtained different numbers? Cheers, Daniel

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Re: [coreboot] Lenovo X200 running Coreboot drains 3-4W more power than with Vendor BIOS
by Alexander Couzens May 1, 2016

May 1, 2016

Hey, I guess the vendor bios activate pci clock power save and similiar options. Some are supported by coreboot, but not activated by default. I can only guess, but the native vga init might also miss some power management features. best, lynxis -- Alexander Couzens mail: lynxis(a)fe80.eu jabber: lynxis(a)fe80.eu mobile: +4915123277221 gpg: 390D CF78 8BF9 AA50 4F8F F1E2 C29E 9DA6 A0DF 8604

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