Hello Zoran,
I really appreciate your help. I was able to resolve the problem on late Friday. I cannot exactly tell what the reason was, however, I set up a fresh install of coreboot, just using my old .config and microcode. Then I saw that the board gets past the microcode update. I must have introduced a bug somewhere... sorry, for the noise...
Now the board stops at TempRamInit in FSP. I'm already using the FSP for Braswell from the Intel link you referenced. The function does not return, but the board shows me post code 0x52. I'm pretty sure the post code comes from FSP because I temporarily redirected all post codes to port 0x84 in the coreboot configuration.
From src/drivers/intel/fsp1_1/cache_as_ram.inc I see that TempRamInit gets a pointer to CAR_init_params which is generated from .config. Those values seem okay.
#define CONFIG_CPU_MICROCODE_CBFS_LOC 0xFFE68400 #define CONFIG_CPU_MICROCODE_CBFS_LEN 0x10C00 #define CONFIG_ROM_SIZE 0x200000
Has anyone any experiences with FSP post codes? I can't find any documentation about that.
Thank you, Alex
Hello Alex,
Glad if you solved at least initial problem. Glad if I helped at least a pinch. :-)
Now... As much as I know, FSP is initial part of the BIOS itself, or BIOS elements. Namely, SEC and PEI phases. My best guess is that* INTEL retained POST codes to be the same as while in (UEFI) BIOS*. UEFI in parenthesis, since these two phases are common/default ones, they belong to legacy as well as to UEFI BIOSes. DXE is the phase legacy and UEFI start to diverge (my best guess).
York can help you more with the POST codes, York should know (much) more than me, considering FSP. Yang, could you, please, come with the FSP POST code table, it will be very beneficial to this community?
Now, assuming that my initial cludge (in *RED*) is correct, you can find the meanings of POST 0x52: http://www.congatec.com/fileadmin/user_upload/Documents/Others/AMI_Aptio_4.x...
PEI Error Codes: 0x50 Memory initialization error. Invalid memory type or incompatible memory speed. 0x51 Memory initialization error. SPD reading has failed. *0x52 Memory initialization error. Invalid memory size or memory modules do not match.* 0x53 Memory initialization error. No usable memory detected. 0x54 Unspecified memory initialization error. 0x55 Memory not installed. 0x56 Invalid CPU type or Speed.
*Error Code*
*Port 0x80 Code*
*Description*
PEI_MEMORY_INVALID_TYPE
0x50
Memory Type Invalid
PEI_MEMORY_INVALID_SPEED
0x50
Memory Speed Invalid
PEI_MEMORY_SPD_FAIL
0x51
Memory SPD failure
*PEI_MEMORY_INVALID_SIZE*
*0x52*
*Memory Size Invalid*
*PEI_MEMORY_MISMATCH*
*0x52*
*Memory Mismatch*
PEI_MEMORY_NOT_DETECTED
0x53
Memory not detected
PEI_MEMORY_NONE_USEFUL
0x53
None of the Memory installed valid
PEI_MEMORY_ERROR
0x54
Memory Error
PEI_MEMORY_NOT_INSTALLED
0x55
Memory not installed
PEI_CPU_INVALID_TYPE
0x56
CPU type invalid
What I am reading from POST error codes is that you did not define your DRAM memory size (probably in Coreboot .config file) correctly.
(and, yes, I am also learning from this conversation ;-) )
Zoran _______
On Mon, May 2, 2016 at 8:28 AM, Alexander Böcken < Alexander.Boecken@junger-audio.com> wrote:
Hello Zoran,
I really appreciate your help. I was able to resolve the problem on late Friday. I cannot exactly tell what the reason was, however, I set up a fresh install of coreboot, just using my old .config and microcode. Then I saw that the board gets past the microcode update. I must have introduced a bug somewhere... sorry, for the noise...
Now the board stops at TempRamInit in FSP. I'm already using the FSP for Braswell from the Intel link you referenced. The function does not return, but the board shows me post code 0x52. I'm pretty sure the post code comes from FSP because I temporarily redirected all post codes to port 0x84 in the coreboot configuration.
From src/drivers/intel/fsp1_1/cache_as_ram.inc I see that TempRamInit gets a pointer to CAR_init_params which is generated from .config. Those values seem okay.
#define CONFIG_CPU_MICROCODE_CBFS_LOC 0xFFE68400 #define CONFIG_CPU_MICROCODE_CBFS_LEN 0x10C00 #define CONFIG_ROM_SIZE 0x200000
Has anyone any experiences with FSP post codes? I can't find any documentation about that.
Thank you, Alex
-
Alexander Böcken -
Zoran Stojsavljevic