coreboot May 2016

coreboot@coreboot.org

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149 discussions

Coreboot, supporting this Dell laptop motherboard?
by thejapanscout . 21 May '16

21 May '16

I want to see if coreboot could support an old Latitude D510 I have from late 2005. It's suitable for low-end operations such as running Firefox and computations, and I'm currently running Lubuntu on this thing. Vendor: Dell Motherboard ID: 3TZKF91, according to dmidecode -s system-seriel-number CPU: Pentium M, Type 0, Family 6, Model 13, Stepping 8 Northbridge/Southbridge: likely 82915GM(?), ICH6/M Southbridge lspci -tvnn output: -[0000:00]-+-00.0 Intel Corporation Mobile 915GM/PM/GMS/910GML Express Processor to DRAM Controller [8086:2590] +-02.0 Intel Corporation Mobile 915GM/GMS/910GML Express Graphics Controller [8086:2592] +-02.1 Intel Corporation Mobile 915GM/GMS/910GML Express Graphics Controller [8086:2792] +-1d.0 Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #1 [8086:2658] +-1d.1 Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #2 [8086:2659] +-1d.2 Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #3 [8086:265a] +-1d.3 Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #4 [8086:265b] +-1d.7 Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB2 EHCI Controller [8086:265c] +-1e.0-[02-06]--+-00.0 Broadcom Corporation BCM4401-B0 100Base-TX [14e4:170c] | +-01.0 Texas Instruments PCI6515 Cardbus Controller [104c:8036] | +-01.2 Texas Instruments Device [104c:8037] | \-03.0 Broadcom Corporation BCM4318 [AirForce One 54g] 802.11g Wireless LAN Controller [14e4:4318] +-1e.2 Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) AC'97 Audio Controller [8086:266e] +-1e.3 Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) AC'97 Modem Controller [8086:266d] +-1f.0 Intel Corporation 82801FBM (ICH6M) LPC Interface Bridge [8086:2641] \-1f.2 Intel Corporation 82801FBM (ICH6M) SATA Controller [8086:2653] There is no Super I/O chip on the mainboard, nor one can be detected by superiotool. Sadly, this is where my venture ends here as flashrom refuses to identify the motherboard because it halts if it finds an unsupported laptop, so I can't identify the flash chip. SPI, maybe?

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Re: [coreboot] [baytrail_FSP] question about lpss device with ACPI mode in win8
by Zoran Stojsavljevic 21 May '16

21 May '16

Hello Cheng, There is some grief/catch 22 introduced while INTEL ported BYT FSP + Coreboot upstream patches into real Coreboot (Coreboot 4.4 inherited these patches from older Coreboot tree, my best guess). You should contact INTEL FSP team (namely York), and ask him to redo and again inspect the patches deltas. Best Regards, Zoran On Fri, May 20, 2016 at 2:36 PM, cheng yichen <blessyichen(a)gmail.com> wrote: > Hi Zoran > > Intel coreboot code + FSP + seabios1.91 in win8.1: All device is workable > and no yellow mark in device manager. > > All lpss device is workable and no yellow mark in AMI UEFI BIOS. > > coreboot4.4 + FSP+seabios1.91 in win8.1: lpss device is shown yellow mark > in device manager. > > Thank you > > 2016-05-20 15:49 GMT+08:00 Zoran Stojsavljevic < > zoran.stojsavljevic(a)gmail.com>: > >> Hello Chang, >> >> Just replace these info in my latest email (regarding BYT FSP and >> Coreboot). The later use case and questions remain the same. >> >> Thank you, >> Zoran >> >> >> On Fri, May 20, 2016 at 9:16 AM, cheng yichen <blessyichen(a)gmail.com> >> wrote: >> >>> Hi Zoran >>> >>> Sorry for the information is not clear. The MR5 that I mean is intel >>> release coreboot source code and FSP in intel web side. In the debug >>> message I find the version is coreboot4.0. >>> >>> in my previous mail, the MR5 is included intel coreboot source code and >>> FSP package. >>> >>> Thank you >>> >>> 2016-05-17 11:36 GMT+08:00 Zoran Stojsavljevic < >>> zoran.stojsavljevic(a)gmail.com>: >>> >>>> Hello Cheng, >>>> >>>> I am afraid, I have no ideas anymore what could be wrong. But I have >>>> for you one suggestion (path to resolution, maybe). >>>> >>>> No idea what you are using. In the sense BYT-FSP (MR5) -> Coreboot -> >>>> (payload???). You either use SeaBIOS (CSM ON), or Tiano Core/EK2 (CSM OFF). >>>> >>>> I would suggest the following: since it depends what payload you use >>>> because you would like to reuse your old HDD with WIN 8.1, to make test >>>> very short (no need to install other HDD with WIN 8.1). >>>> >>>> Please, take real UEFI BIOS (for BYT-M N2807 it is Client Group 64bit >>>> A093.R42 or later), and install it on some INTEL CRB (BayleyBay or >>>> BakerSport) where you already have N2807. Then, in relations what payload >>>> you are using, you need to set CSM ON or CSM OFF, to make work/reuse your >>>> original HDD with WIN 8.1. >>>> >>>> Please, after you are able to bring your INTEL BYT-M CRB to WIN 8.1, >>>> reboot, and again enter BIOS CMOS. There, under system setup/advanced >>>> settings, you should be able to find southbridge setup, where one of the >>>> options is LPSS. >>>> >>>> Please, experiment, with settings within LPSS mode (PCI and ACPI), and, >>>> please, report here do you have the same as with BYT-FSP MR5 settings as >>>> you use "pcdlpsssioenablepcimode" to "LPSS_PCI_MODE_DISABLE" and >>>> "ENABLE/DEFAULT" (do you see the same behavior in WIN 8.1 device manager)? >>>> >>>> Thank you, >>>> Zoran >>>> >>>> On Mon, May 16, 2016 at 2:06 PM, cheng yichen <blessyichen(a)gmail.com> >>>> wrote: >>>> >>>>> Hi Zoran >>>>> >>>>> Base on the version Baytrail_coreboot_MR5_Dec-21-2015(coreboot) that >>>>> is released by Intel. >>>>> In the coreboot(Intel released and defautle is acpi mode) I can >>>>> install driver and device is workable in win8. >>>>> I can see hs-uart controller in device manage and no yellow mark. >>>>> >>>>> In last coreboot source code. after I modify "pcdlpsssioenablepcimode" >>>>> to "LPSS_PCI_MODE_DISABLE". Then the lpss device will be confgured to ACPI >>>>> mode. >>>>> but the hs-uart controller and I2C controller will shown yellow mark >>>>> in win8 device manager. >>>>> Because the main controller is not workable in win8. I don't check the >>>>> sub-device device. >>>>> >>>>> >>>>> >>>>> >>>>> >>>>> 2016-05-16 17:16 GMT+08:00 Zoran Stojsavljevic < >>>>> zoran.stojsavljevic(a)gmail.com>: >>>>> >>>>>> Hello Cheng, >>>>>> >>>>>> Again, I'll repeat my questions: >>>>>> [1] Are you talking about BIOS, where you are enabling in LPSS ACPI >>>>>> (disabling automatically PCI) mode? >>>>>> [2] I need better explanation of your use case... Are you using BYT >>>>>> MR4, then MR5, or instead MR4 BIOS, or...? >>>>>> [3] For WIN8.1 you need to have the following: >>>>>> For BIOS to work (and get rid off these yellow triangles with >>>>>> question marks): >>>>>> [A] ACPI mode in BIOS: South Cluster Configuration -> LPSS & >>>>>> SCC Configuration -> LPSS LPSS & SCC >>>>>> Devices Mode -> Select "ACPI Mode"; >>>>>> [B] The GPIO controller driver is/should be prerequisite for >>>>>> HS-UART driver. There is a document named: >>>>>> Intel_Processor_Win8_IO_Drivers_Gold_MR1. You should ask >>>>>> for it from INTEL support. If installed >>>>>> correctly, you should see HS-UART Controller device under >>>>>> System Devices in Device Manager. Also >>>>>> new unknown devices should appear: ACPI\BCM2E1A and >>>>>> ACPI\BCM4752. These devices are for >>>>>> HS-UART Sub Device Driver; >>>>>> [C] You should compile the UART Sub Device Driver (by 1.2.1 of >>>>>> Intel Atom E3800 Win8.1 HS-UART Sub >>>>>> Device Driver Sample Code Guide_1.0), and install after >>>>>> building them. After that you should see Ports in >>>>>> Device Manager. >>>>>> >>>>>> Zoran >>>>>> >>>>>> On Fri, May 13, 2016 at 5:43 AM, cheng yichen <blessyichen(a)gmail.com> >>>>>> wrote: >>>>>> >>>>>>> >>>>>>> HI all >>>>>>> >>>>>>> I try to enable Lpss device(i2c hs-uart) with ACPI mdoe. >>>>>>> i2c and hs-uart will show yellow mark in device manager with win8.1. >>>>>>> but I can't find the same issue in intel coreboot(versrion MR5). >>>>>>> Do you have any idea for the issue? Thank you >>>>>>> >>>>>>> -- >>>>>>> coreboot mailing list: coreboot(a)coreboot.org >>>>>>> https://www.coreboot.org/mailman/listinfo/coreboot >>>>>>> >>>>>> >>>>>> >>>>> >>>> >>> >>> -- >>> coreboot mailing list: coreboot(a)coreboot.org >>> https://www.coreboot.org/mailman/listinfo/coreboot >>> >> >> >

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Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay
by Zoran Stojsavljevic 21 May '16

21 May '16

Mayuri, > Zoran writes in last email: "...UEFI payload will not find *EFI32* /boot/EFI directory created..." My bad (right thinking, but too fast hands): should read FAT32 instead EFI32. > Sorry, but I am not able to understand what you have mentioned. Please, read carefully the following article: https://www.happyassassin.net/2014/01/25/uefi-boot-how-does-that-actually-w… I have no time explaining the written. You need to spend maybe whole day analyzing it, trying to understand what Adam writes about. Bottom line, your Tiano Core works perfectly as payload, but you have CSM ON formatted HDD (must have CSM OFF). Zoran On Fri, May 20, 2016 at 10:41 AM, Mayuri Tendulkar < mayuri.tendulkar(a)aricent.com> wrote: > Hi Zoran > > > > Sorry, but I am not able to understand what you have mentioned. > > > > Can you please help me explain little detail? > > > > Sorry, but I am new to this coreboot environment. > > > > Regards > > Mayuri > > > > *From:* Zoran Stojsavljevic [mailto:zoran.stojsavljevic@gmail.com] > *Sent:* 20 May 2016 13:39 > *To:* Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com> > *Cc:* coreboot <coreboot(a)coreboot.org> > > *Subject:* Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard > or Bayley bay > > > > Hello Mayuri, > > > > Not sure if I am right, but to bring GRUB 2.0 from CSM OFF and CSM ON > modes, you must have two distinct HDDs, one created with CSM ON, other with > CSM OFF. If you are using one with CSM ON (seems the case), your UEFI > payload will not find EFI32 /boot/EFI directory created, and it does not > understand MBR). > > > > Does this (what I wrote) make sense? > > > > Zoran > > > > > > On Fri, May 20, 2016 at 7:21 AM, Mayuri Tendulkar < > mayuri.tendulkar(a)aricent.com> wrote: > > Hi Zoran > > > > Currently we are using FSP 3. But it works fine with seabios payload. > > > > Only when I include UEFI, I am getting this issue. So I am not sure if > this is related to FSP3 or 4. > > > > My query is there any additional configurations required in UEFI Payload > to make it work for Minnowboard max. > > > > I see difference in addresses for UEFI and Seabios payload. Not sure where > are they set. > > > > *Seabios payload (working)* > > > > CBFS provider active. > > CBFS @ 500000 size 2ff9c0 > > CBFS: Locating 'fallback/payload' > > CBFS: Found @ offset 76b40 size f782 > > 'fallback/payload' located at offset: 576b78 size: f782 > > Loading segment from rom address 0xffd76b78 > > code (compression=1) > > New segment dstaddr 0xe2780 memsize 0x1d880 srcaddr 0xffd76bb0 filesize > 0xf74a > > Loading segment from rom address 0xffd76b94 > > Entry Point 0x000ff06e > > Payload being loaded below 1MiB without region being marked as RAM usable. > > Bounce Buffer at 7ac50000, 451744 bytes > > Loading Segment: addr: 0x00000000000e2780 memsz: 0x000000000001d880 > filesz: 0x000000000000f74a > > lb: [0x0000000000100000, 0x0000000000137250) > > Post relocation: addr: 0x00000000000e2780 memsz: 0x000000000001d880 > filesz: 0x000000000000f74a > > using LZMA > > [ 0x000e2780, 00100000, 0x00100000) <- ffd76bb0 > > dest 000e2780, end 00100000, bouncebuffer 7ac50000 > > Loaded segments > > BS: BS_PAYLOAD_LOAD times (us): entry 0 run 130526 exit 0 > > FspNotify(EnumInitPhaseReadyToBoot) > > fsp_header_ptr: fffc0094 > > FSP Header Version: 1 > > FSP Revision: 3.3 > > Returned from FspNotify(EnumInitPhaseReadyToBoot) > > POST: 0x7b > > Jumping to boot code at 000ff06e(7acbf000) > > POST: 0xf8 > > CPU0: stack: 0012e000 - 0012f000, lowest used address 0012eb10, stack > used: 1264 bytes > > entry = 0x000ff06e > > lb_start = 0x00100000 > > lb_size = 0x00037250 > > buffer = 0x7ac50000 > > SeaBIOS (version rel-1.9.0-127-gc8e105a) > > > > > > > > *UEFI Payload logs (not working)* > > > > CBFS provider active. > > CBFS @ 500000 size 2ff9c0 > > CBFS: Locating 'fallback/payload' > > CBFS: Found @ offset 56ec0 size 90b92 > > '*fallback/payload' located at offset: 556ef8 size: 90b92* > > *L*oading segment from rom address 0xffd56ef8 > > code (compression=1) > > *New segment dstaddr 0x800000 memsize 0x410000 srcaddr 0xffd56f30 > filesize 0x90b5a* > > Loading segment from rom address 0xffd56f14 > > Entry Point 0x008002c0 > > Bounce Buffer at 7ac34000, 437408 bytes > > Loading Segment: addr: 0x0000000000800000 memsz: 0x0000000000410000 > filesz: 0x0000000000090b5a > > lb: [0x0000000000100000, 0x0000000000135650) > > Post relocation: addr: 0x0000000000800000 memsz: 0x0000000000410000 > filesz: 0x0000000000090b5a > > using LZMA > > [ 0x00800000, 00c10000, 0x00c10000) <- ffd56f30 > > dest 00800000, end 00c10000, bouncebuffer 7ac34000 > > Loaded segments > > BS: BS_PAYLOAD_LOAD times (us): entry 0 run 507070 exit 0 > > FspNotify(EnumInitPhaseReadyToBoot) > > fsp_header_ptr: fffc0094 > > FSP Header Version: 1 > > FSP Revision: 3.3 > > Returned from FspNotify(EnumInitPhaseReadyToBoot) > > POST: 0x7b > > Jumping to boot code at 008002c0(7ac9f000) > > POST: 0xf8 > > CPU0: stack: 0012c000 - 0012d000, lowest used address 0012cb10, stack > used: 1264 bytes > > entry = 0x008002c0 > > lb_start = 0x00100000 > > lb_size = 0x00035650 > > buffer = 0x7ac34000 > > > > *From:* Zoran Stojsavljevic [mailto:zoran.stojsavljevic@gmail.com] > *Sent:* 20 May 2016 10:44 > *To:* Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com>; coreboot < > coreboot(a)coreboot.org> > > > *Subject:* Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard > or Bayley bay > > > > Hello Mayuri, > > > > If I am not mistaken (I often mix BYT Coreboot @ threads in my head), you > are using BYT FSP Version 3. > > > > > fsp_header_ptr: fffc0094 <== correct > > > FSP Header Version: 1 > > > FSP Revision: 3.3 <== please, use Version 4 > > > > Please, try to use the latest public BYT FSP Version 4 posted at: > www.intel.com/fsp > > > > *BAYTRAIL_FSP_GOLD_004_22-MAY-2015.fd* > > *BAYTRAIL_FSP_GOLD_004_22-MAY-2015_DEBUG.fd* > > > > Don't remember deltas between V3 and V4, I thing something was wrong in V3 > with MTRRs' setup, if I do not mix data in my head. > > > > INTEL also has Version 5 for a quite some time, but this one for some > reasons never got publicly released. > > > > Please, report if this solved your problems. > > > > Zoran > > > > On Wed, May 18, 2016 at 6:56 AM, Mayuri Tendulkar < > mayuri.tendulkar(a)aricent.com> wrote: > > Hi > > > > While booting my Minnomboard with coreboot and UEFI, it hangs at below > point while loading the payload. > > > > I followed the procedure to download latest EDK2 tree and built > UEFIPAYLOAD.fd and copied it to coreboot/payloads/external/tianocore > folder and gave this path in make menuconfig. > > > > Has anybody come across this? > > > > BS: BS_PAYLOAD_LOAD times (us): entry 0 run 507070 exit 0 > > FspNotify(EnumInitPhaseReadyToBoot) > > fsp_header_ptr: fffc0094 > > FSP Header Version: 1 > > FSP Revision: 3.3 > > Returned from FspNotify(EnumInitPhaseReadyToBoot) > > POST: 0x7b > > Jumping to boot code at 008002c0(7ac9f000) > > POST: 0xf8 > > CPU0: stack: 0012c000 - 0012d000, lowest used address 0012cb10, stack > used: 1264 bytes > > entry = 0x008002c0 > > lb_start = 0x00100000 > > lb_size = 0x00035650 > > buffer = 0x7ac34000 > > > > Regards > > Mayuri > > *From:* Mayuri Tendulkar > *Sent:* 17 May 2016 14:13 > *To:* 'Zoran Stojsavljevic' <zoran.stojsavljevic(a)gmail.com>; > coreboot(a)coreboot.org > *Subject:* Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard > or Bayley bay > > > > Hi Zoran and Martin > > > > Today I was able to build UEFIPAYLOAD separately. I included .fd file > while building coreboot.rom. > > > > But while booting, getting some errors , so debugging those. > > > > Need to check what more customizations to be done in UEFI for Minnowmax. > > > > Has anybody tried it? > > > > Regards > > Mayuri > > > > *From:* Zoran Stojsavljevic [mailto:zoran.stojsavljevic@gmail.com > <zoran.stojsavljevic(a)gmail.com>] > *Sent:* 16 May 2016 21:04 > *To:* Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com>; > coreboot(a)coreboot.org > *Subject:* Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard > or Bayley bay > > > > OK, Mayuri, > > > > You brought an interesting point. And this point is to be not only > investigated by you, rather also by me and, perhaps, Coreboot community. > > > > Since here, in Bayern/Deutschland is Holiday Day, I went to buy a beer in > Munchen HBf, and while walking there I was thinking about your use case. > Thinking deeper. > > > > I know that you are using some INTEL CPU/SoC (do not remember which one, > if you said one). But, while recapping how BIOS looks like, I did notice > that SEC and PEI phases have nothing to do with UEFI EDK2. EDK 2 comes to > play in DXE phase, where EDK2 actually takes place/overtakes control... > > > > It says to me one major thing I did not notice while ago: that ARM SoCs > are also eligible to run on UEFI compliant OSes, namely WIN 8.1+ (including > WIN 10 and WIN 10 Athens/RT WIN 10). Which makes very interesting IOT case > namely for ARM, allowing it also to compete in WIN space. > > > > Interestingly enough, this idea did not come to my mind till few hours > ago... I guess, Vincent (Zimmer) already thought about that. ;-) > > _______ > > > > Martin (Roth) just replied, to solve this immediate mystery. probably for > the beginning only for INTEL SoCs, but, I really hope, ARM will also > integrate in this concept seamlessly! :-) > > > > Zoran > > _______ > > > > On Mon, May 16, 2016 at 2:29 PM, Mayuri Tendulkar < > mayuri.tendulkar(a)aricent.com> wrote: > > Hi Zoran > > > > I have checked that site and downloaded EDK2 code. I am trying to build it > on Linux but facing some issues. > > But if I generate payload file separately, I need to integrate it in > coreboot separately. > > > > So I am checking if there is way to build the payload in coreboot itself. > > > > Regards > > Mayuri > > > > *From:* Zoran Stojsavljevic [mailto:zoran.stojsavljevic@gmail.com] > *Sent:* 16 May 2016 17:57 > *To:* Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com> > *Cc:* coreboot(a)coreboot.org > *Subject:* Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard > or Bayley bay > > > > Hello Mayuri, > > > > You should check payload called: Tiano Core (true UEFI payload). > > > > Zoran > > > > > > On Mon, May 16, 2016 at 2:12 PM, Mayuri Tendulkar < > mayuri.tendulkar(a)aricent.com> wrote: > > Hi > > > > Is there any mechanism to build UEFI payload directly in coreboot similar > like seabios? > > > > Regards > > Mayuri > > "DISCLAIMER: This message is proprietary to Aricent and is intended solely > for the use of the individual to whom it is addressed. It may contain > privileged or confidential information and should not be circulated or used > for any purpose other than for what it is intended. If you have received > this message in error, please notify the originator immediately. If you are > not the intended recipient, you are notified that you are strictly > prohibited from using, copying, altering, or disclosing the contents of > this message. Aricent accepts no responsibility for loss or damage arising > from the use of the information transmitted by this email including damage > from virus." > > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot > > > > "DISCLAIMER: This message is proprietary to Aricent and is intended solely > for the use of the individual to whom it is addressed. It may contain > privileged or confidential information and should not be circulated or used > for any purpose other than for what it is intended. If you have received > this message in error, please notify the originator immediately. If you are > not the intended recipient, you are notified that you are strictly > prohibited from using, copying, altering, or disclosing the contents of > this message. Aricent accepts no responsibility for loss or damage arising > from the use of the information transmitted by this email including damage > from virus." > > > > "DISCLAIMER: This message is proprietary to Aricent and is intended solely > for the use of the individual to whom it is addressed. It may contain > privileged or confidential information and should not be circulated or used > for any purpose other than for what it is intended. If you have received > this message in error, please notify the originator immediately. If you are > not the intended recipient, you are notified that you are strictly > prohibited from using, copying, altering, or disclosing the contents of > this message. Aricent accepts no responsibility for loss or damage arising > from the use of the information transmitted by this email including damage > from virus." > > > > "DISCLAIMER: This message is proprietary to Aricent and is intended solely > for the use of the individual to whom it is addressed. It may contain > privileged or confidential information and should not be circulated or used > for any purpose other than for what it is intended. If you have received > this message in error, please notify the originator immediately. If you are > not the intended recipient, you are notified that you are strictly > prohibited from using, copying, altering, or disclosing the contents of > this message. Aricent accepts no responsibility for loss or damage arising > from the use of the information transmitted by this email including damage > from virus." > > > "DISCLAIMER: This message is proprietary to Aricent and is intended solely > for the use of the individual to whom it is addressed. It may contain > privileged or confidential information and should not be circulated or used > for any purpose other than for what it is intended. If you have received > this message in error, please notify the originator immediately. If you are > not the intended recipient, you are notified that you are strictly > prohibited from using, copying, altering, or disclosing the contents of > this message. Aricent accepts no responsibility for loss or damage arising > from the use of the information transmitted by this email including damage > from virus." >

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Re: [coreboot] [baytrail_FSP] question about lpss device with ACPI mode in win8
by cheng yichen 20 May '16

20 May '16

Hi Zoran Intel coreboot code + FSP + seabios1.91 in win8.1: All device is workable and no yellow mark in device manager. All lpss device is workable and no yellow mark in AMI UEFI BIOS. coreboot4.4 + FSP+seabios1.91 in win8.1: lpss device is shown yellow mark in device manager. Thank you 2016-05-20 15:49 GMT+08:00 Zoran Stojsavljevic < zoran.stojsavljevic(a)gmail.com>: > Hello Chang, > > Just replace these info in my latest email (regarding BYT FSP and > Coreboot). The later use case and questions remain the same. > > Thank you, > Zoran > > > On Fri, May 20, 2016 at 9:16 AM, cheng yichen <blessyichen(a)gmail.com> > wrote: > >> Hi Zoran >> >> Sorry for the information is not clear. The MR5 that I mean is intel >> release coreboot source code and FSP in intel web side. In the debug >> message I find the version is coreboot4.0. >> >> in my previous mail, the MR5 is included intel coreboot source code and >> FSP package. >> >> Thank you >> >> 2016-05-17 11:36 GMT+08:00 Zoran Stojsavljevic < >> zoran.stojsavljevic(a)gmail.com>: >> >>> Hello Cheng, >>> >>> I am afraid, I have no ideas anymore what could be wrong. But I have for >>> you one suggestion (path to resolution, maybe). >>> >>> No idea what you are using. In the sense BYT-FSP (MR5) -> Coreboot -> >>> (payload???). You either use SeaBIOS (CSM ON), or Tiano Core/EK2 (CSM OFF). >>> >>> I would suggest the following: since it depends what payload you use >>> because you would like to reuse your old HDD with WIN 8.1, to make test >>> very short (no need to install other HDD with WIN 8.1). >>> >>> Please, take real UEFI BIOS (for BYT-M N2807 it is Client Group 64bit >>> A093.R42 or later), and install it on some INTEL CRB (BayleyBay or >>> BakerSport) where you already have N2807. Then, in relations what payload >>> you are using, you need to set CSM ON or CSM OFF, to make work/reuse your >>> original HDD with WIN 8.1. >>> >>> Please, after you are able to bring your INTEL BYT-M CRB to WIN 8.1, >>> reboot, and again enter BIOS CMOS. There, under system setup/advanced >>> settings, you should be able to find southbridge setup, where one of the >>> options is LPSS. >>> >>> Please, experiment, with settings within LPSS mode (PCI and ACPI), and, >>> please, report here do you have the same as with BYT-FSP MR5 settings as >>> you use "pcdlpsssioenablepcimode" to "LPSS_PCI_MODE_DISABLE" and >>> "ENABLE/DEFAULT" (do you see the same behavior in WIN 8.1 device manager)? >>> >>> Thank you, >>> Zoran >>> >>> On Mon, May 16, 2016 at 2:06 PM, cheng yichen <blessyichen(a)gmail.com> >>> wrote: >>> >>>> Hi Zoran >>>> >>>> Base on the version Baytrail_coreboot_MR5_Dec-21-2015(coreboot) that is >>>> released by Intel. >>>> In the coreboot(Intel released and defautle is acpi mode) I can install >>>> driver and device is workable in win8. >>>> I can see hs-uart controller in device manage and no yellow mark. >>>> >>>> In last coreboot source code. after I modify "pcdlpsssioenablepcimode" >>>> to "LPSS_PCI_MODE_DISABLE". Then the lpss device will be confgured to ACPI >>>> mode. >>>> but the hs-uart controller and I2C controller will shown yellow mark in >>>> win8 device manager. >>>> Because the main controller is not workable in win8. I don't check the >>>> sub-device device. >>>> >>>> >>>> >>>> >>>> >>>> 2016-05-16 17:16 GMT+08:00 Zoran Stojsavljevic < >>>> zoran.stojsavljevic(a)gmail.com>: >>>> >>>>> Hello Cheng, >>>>> >>>>> Again, I'll repeat my questions: >>>>> [1] Are you talking about BIOS, where you are enabling in LPSS ACPI >>>>> (disabling automatically PCI) mode? >>>>> [2] I need better explanation of your use case... Are you using BYT >>>>> MR4, then MR5, or instead MR4 BIOS, or...? >>>>> [3] For WIN8.1 you need to have the following: >>>>> For BIOS to work (and get rid off these yellow triangles with >>>>> question marks): >>>>> [A] ACPI mode in BIOS: South Cluster Configuration -> LPSS & SCC >>>>> Configuration -> LPSS LPSS & SCC >>>>> Devices Mode -> Select "ACPI Mode"; >>>>> [B] The GPIO controller driver is/should be prerequisite for >>>>> HS-UART driver. There is a document named: >>>>> Intel_Processor_Win8_IO_Drivers_Gold_MR1. You should ask >>>>> for it from INTEL support. If installed >>>>> correctly, you should see HS-UART Controller device under >>>>> System Devices in Device Manager. Also >>>>> new unknown devices should appear: ACPI\BCM2E1A and >>>>> ACPI\BCM4752. These devices are for >>>>> HS-UART Sub Device Driver; >>>>> [C] You should compile the UART Sub Device Driver (by 1.2.1 of >>>>> Intel Atom E3800 Win8.1 HS-UART Sub >>>>> Device Driver Sample Code Guide_1.0), and install after >>>>> building them. After that you should see Ports in >>>>> Device Manager. >>>>> >>>>> Zoran >>>>> >>>>> On Fri, May 13, 2016 at 5:43 AM, cheng yichen <blessyichen(a)gmail.com> >>>>> wrote: >>>>> >>>>>> >>>>>> HI all >>>>>> >>>>>> I try to enable Lpss device(i2c hs-uart) with ACPI mdoe. >>>>>> i2c and hs-uart will show yellow mark in device manager with win8.1. >>>>>> but I can't find the same issue in intel coreboot(versrion MR5). >>>>>> Do you have any idea for the issue? Thank you >>>>>> >>>>>> -- >>>>>> coreboot mailing list: coreboot(a)coreboot.org >>>>>> https://www.coreboot.org/mailman/listinfo/coreboot >>>>>> >>>>> >>>>> >>>> >>> >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> https://www.coreboot.org/mailman/listinfo/coreboot >> > >

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Re: [coreboot] SeaBios serial(RX) is not running.
by Kyösti Mälkki 20 May '16

20 May '16

On Tue, May 17, 2016 at 10:46 PM, Martin Roth <gaumless(a)gmail.com> wrote: > Hi, > If you want bi-directional serial port in SeaBIOS, I think you need > to stick with the version from Sage. As far as I know, it's never been > supported in the upstream SeaBIOS version. > > I have pulled this serial to keyboard mapping change from SageBIOS and posted on the seabios list today. Hitting ESC and changing boot media seemed to work. BR, Kyösti

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Re: [coreboot] coreboot with fsp hangs at post code 19 on Bayley Bay
by Kathappan E 20 May '16

20 May '16

Hi Zoran, Thanks for your help. Currently I don’t have FITC tool package along with TXE / descriptor XML file. I will try to get it to check PCIE port settings and keep you update. Thanks, Kathappan From: Zoran Stojsavljevic [mailto:zoran.stojsavljevic@gmail.com] Sent: 17 May 2016 15:51 To: Kathappan E <Kathappan.E(a)LntTechservices.com>; naveed.ghori(a)dti.com Cc: Zeh, Werner <werner.zeh(a)siemens.com>; coreboot <coreboot(a)coreboot.org> Subject: Re: [coreboot] coreboot with fsp hangs at post code 19 on Bayley Bay Hello Kathappan, Naveed (I am lazy to reply to separate @s), [1/2] I'll answer these two topics altogether. YES, I am asking for that. It is after all E3825, and this SKU has significant difference comparing to E3826, E3827 (not sure about this one), and E3845. All of them are dual-channel DDR3, while E3825 is SINGLE-channel one. YES, YES, you have correct setup, which is NOT at all important for this topic (sorry, I had to ask you before... Maneuvering in The Dark). [3] Here is The IMPORTANT for you: the mentioned PCIe settings are not a part of FSP but rather part of the descriptor. In the descriptor, soft straps are configured and loaded into the hardware upon reset release. The strapping can be modified using FITC tool, which is used to configure the flash image and ME/TXE. If PCIe lanes are disabled in descriptor, Coreboot per default can’t see these PCIe ports. You have to modify the descriptor using Flash Image Configuration Tool (FITC) distributed with the TXE package for Bay Trail. [Inline image 1] Werner, I would like to thank you you for enlightening me (I remembered/recalled our private discussion once upon a time about this topic)... I do need to do further analyses/actions, and teach one seldom old dog (me) the new tricks (they/general public by default say the opposite). ;-) I sincere hope this @ helps to both of you (TO: list - K and N), and NOT only. Zoran _______ On Tue, May 17, 2016 at 10:49 AM, Kathappan E <Kathappan.E(a)lnttechservices.com<mailto:Kathappan.E@lnttechservices.com>> wrote: Hi Zoran, Sorry for the late reply since I had a long week end here. Thanks for your comments. [1] Which BYT SoC you are using (example BYT-M N2807)? Bayley Bay custom board (not a CRB) which is based Atom E3825 and D0 stepping SoC. But I am not sure whether you are asking this. [2] How many DDR3 channels (1 or 2) are you using in your design, and what is the size of memory (most likely not a problem)? Single channel non-ECC 1333/1066 MHz soldered DDR3L memory up to 4GB. DIMM0 is populated with 2 GB and DIMM1 is disabled [3] PCH. Do you have PCIe channels initialized/set in default soft straps (you must have some, at least PCIe root port 0, and PCIe root port 1, as I recalled)? <<==== IMPORTANT? I didn’t see any PCIe related settings available in bsf file(attached) to edit it. Can you please help me more on it to change ? 3 PCIe x1 Gen2 port (0 - 2) , 1 PCIe x1 Gen2 port 3 - GBE Thanks, Kathappan From: Zoran Stojsavljevic [mailto:zoran.stojsavljevic@gmail.com<mailto:zoran.stojsavljevic@gmail.com>] Sent: 17 May 2016 09:16 To: Kathappan E <Kathappan.E(a)LntTechservices.com<mailto:Kathappan.E@LntTechservices.com>>; coreboot <coreboot(a)coreboot.org<mailto:coreboot@coreboot.org>> Subject: Re: [coreboot] coreboot with fsp hangs at post code 19 on Bayley Bay Hello Kathappan, Did you try to (using BCT) to enable PCIe x1, at least PCIe0 and PCIe1 (the same size x1)? Does it work now? Thank you, Zoran On Fri, May 13, 2016 at 9:51 PM, Zoran Stojsavljevic <zoran.stojsavljevic(a)gmail.com<mailto:zoran.stojsavljevic@gmail.com>> wrote: Hello Kathappan, I need to look deeper into this area since I am not expert on FSP, but I have some ideas what could be wrong. Several questions for you: [1] Which BYT SoC you are using (example BYT-M N2807)? [2] How many DDR3 channels (1 or 2) are you using in your design, and what is the size of memory (most likely not a problem)? [3] PCH. Do you have PCIe channels initialized/set in default soft straps (you must have some, at least PCIe root port 0, and PCIe root port 1, as I recalled)? <<==== IMPORTANT? Again, I need to think more about this, and I'll try to find some answers, later... Please, try to see/discover [3] using BCT tool! Zoran _______ On Fri, May 13, 2016 at 3:01 PM, Kathappan E <Kathappan.E(a)lnttechservices.com<mailto:Kathappan.E@lnttechservices.com>> wrote: Hi all, When I try coreboot on Bayley Bay platform along with fsp (BAYTRAIL_FSP_GOLD_004_22-MAY-2015), it is getting hang at post code 19. Also I tried with debug version fsp (BAYTRAIL_FSP_GOLD_004_22-MAY-2015_DEBUG) , it still at that point and below is the debug log. Firmware Image: Have used the 8 MB vendor bios and flashed the last 2 MB region(600000 to 7fffff) with coreboot image. From the debug log: coreboot gives the control to FSP binary routine(FspInitApi) and it is getting hang when trying to do PCH initialize(PchMiscInit) inside FSP part code. POST 19 code info: EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_CLOCK_PEI_INIT_ENTRY ==> Clock Init PEIM Entry I have not seen the clock related setting available when customizing fsp binary using BCT. I tried to disable south cluster component such as EMMC,HSUART,SATA and SIO using BCT , it didn't help me. Can anyone please help me provide some inputs such as related below to proceed further debugging on it ? 1. Any other setting we can try out using BCT 2. About devices configuration to be initialized byPchMiscInit function. 3. Anything need to be cared/double checked from coreboot side in order to giving control to FspInitApi function. 4. Does pch straps settings may cause this since I am using upper 6 MB region flash data which is from vendor bios. 4. Please suggest anything on it. Thanks in advance, Kathappan <<<<<<<<<<<< Debug log Start >>>>>>>>>>>>>>> coreboot-coreboot-unknown Thu May 12 08:04:42 UTC 2016 romstage starting... RTC Init POST: 0x44 POST: 0x47 POST: 0x48 Starting the Intel FSP (early_init) PM1_STS = 0x0 PM1_CNT = 0x0 GEN_PMCON1 = 0x44000 prev_sleep_state = S5 Configure Default UPD Data PcdMrcInitSPDAddr1: 0xa0 (default) PcdMrcInitSPDAddr2: 0xa2 (default) PcdSataMode: 0x01 (set) PcdLpssSioEnablePciMode: 0x01 (default) PcdMrcInitMmioSize: 0x800 (default) PcdIgdDvmt50PreAlloc: 0x02 (default) PcdApertureSize: 0x02 (default) PcdGttSize: 0x02 (default) SerialDebugPortAddress: 0x3f8 (default) SerialDebugPortType: 0x01 (default) PcdMrcDebugMsg: 0x01 (default) PcdSccEnablePciMode: 0x01 (default) IgdRenderStandby: 0x00 (default) TxeUmaEnable: 0x00 (default) PcdOsSelection: 0x04 (default) PcdEMMC45DDR50Enabled: 0x01 (default) PcdEMMC45HS200Enabled: 0x00 (default) PcdEMMC45RetuneTimerValue: 0x08 (default) PcdEnableIgd: 0x01 (default) AutoSelfRefreshEnable: 0x00 (default) APTaskTimeoutCnt: 0x00 (default) GTT Size: 2 MB Tseg Size: 8 MB Aperture Size: 256 MB IGD Memory Size: 64 MB MMIO Size: 2048 MB MIPI/ISP: Disabled Sdio: Enabled Sdcard: Enabled SATA: Enabled SIO Dma 0: Enabled SIO I2C0: Enabled SIO I2C1: Enabled SIO I2C2: Enabled SIO I2C3: Enabled SIO I2C4: Enabled SIO I2C5: Enabled SIO I2C6: Enabled Azalia: Enabled SIO Dma1: Enabled Pwm0: Enabled Pwm1: Enabled Hsuart0: Enabled Hsuart1: Enabled Spi: Enabled Lpe: Disabled eMMC Mode: eMMC 4.5 SATA Mode: AHCI Xhci: Enabled POST: 0x92 ============= PEIM FSP (VLYVIEW0 0x00000304) ============= Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3 Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A The 0th FV start address is 0x000FFFE0400, size is 0x00017C00, handle is 0x0 Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39 Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38 Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6 Install PPI: DBE23AA9-A345-4B97-85B6-B226F1617389 Install PPI: 06E81C58-4AD7-44BC-8390-F10265F72480 Install PPI: 01F34D25-4DE2-23AD-3FF3-36353FF323F1 Install PPI: 49EDB1C1-BF21-4761-BB12-EB0031AABB39 Notify: PPI Guid: 49EDB1C1-BF21-4761-BB12-EB0031AABB39, Peim notify entry point: FFFE0FD4 The 1th FV start address is 0x000FFFB0000, size is 0x0002F400, handle is 0xFFFB0000 Install PPI: A55D6970-1306-440C-8C72-8F51FAFB2926 PcdMrcInitTsegSize = 8 PcdMrcInitMmioSize = 800 PcdMrcInitSPDAddr1 = A0 PcdMrcInitSPDAddr2 = A2 Setting BootMode to 0 Install PPI: 1F4C6F90-B06B-48D8-A201-BAE5F1CD7D56 Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE About to call MrcInit(); BayleyBay Platform Type RID = 0x11. Reg_EFF_DualCH_EN = 0x40030040. CurrentMrcData.BootMode = 4 C1.D0: SPD not present. Configuring Memory Start... START_RMT: RxDqLeft RxDqRight RxVLow RxVHigh TxDqLeft TxDqRight CmdLeft CmdRight ------------------------------------------------------------------------------------------------ Channel 0 Rank 0 -22 21 -21 19 -25 26 0 0 STOP_RMT: CMD module is per channel only and without Rank differentiation Configuring Memory End UpperTotalMemory = 0x80000000 dBMBOUND = 0x80000000 dBMBOUNDHI = 0x80000000 dGFXBase = 0x7BE00000 dTSegBase = 0x7B000000 Save MRC params. Current MRC Data DDR Freq 1 Current MRC Data Core Freq 1 Current MRC Data Tcl 7 Current MRC Data WL 6 Current MRC Data DDRType 1 Current MRC Data MMIO Size 800 Current MRC Data TSeg Size 8 Channel 0 Enabled 1 Socket 0 DimmPresent 1 DimmDataWidth 1 DimmBusWidth 3 DimmSize 2 DimmSides 0 Channel 1 Enabled 0 Socket 0 DimmPresent 0 DimmDataWidth 0 DimmBusWidth 0 DimmSize 0 DimmSides 0 Current MRC Timing Data MRC_DATA_TRP 7 Current MRC Timing Data MRC_DATA_TRCD 7 Current MRC Timing Data MRC_DATA_TRAS 13 Current MRC Timing Data MRC_DATA_TWR 8 Current MRC Timing Data MRC_DATA_TWTR 4 Current MRC Timing Data MRC_DATA_TRRD 4 Current MRC Timing Data MRC_DATA_TRTP 4 Current MRC Timing Data MRC_DATA_TFAW 1B PeiInstallPeiMemory MemoryBegin 0x7AE00000, MemoryLength 0x200000 Old Stack size 24576, New stack size 131072 Heap Offset = 0x0 Stack Offset = 0x840F0000 Stack Hob: BaseAddress=0x7AE00000 Length=0x20000 Reinstall PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3 Reinstall PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A Reinstall PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6 Install PPI: F894643D-C449-42D1-8EA8-85BDD8C65BDE Notify: PPI Guid: F894643D-C449-42D1-8EA8-85BDD8C65BDE, Peim notify entry point: FFFC1281 Install PPI: 0AE8CE5D-E448-4437-A8D7-EBF5F194F731 Install PPI: 1A36E4E7-FAB6-476A-8E75-695A0576FDD7 Install PPI: EF398D58-9DFD-4103-BF94-78C6F4FE712F InstallVlvInitPpi() - Start Register PPI Notify: 7D84B2C2-22A1-4372-B12C-EBB232D3A6A3 InstallVlvInitPpi() - End InstallPchInitPpi() - Start PmcBase needs to be programmed and enabled before here. ProgramGpioSCForSDCardWA Done.... Register PPI Notify: 15344673-D365-4BE2-8513-1497CC07611D Register PPI Notify: 00B710BA-8CD6-4BF3-AB7A-9A24F54CC334 Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE Notify: PPI Guid: F894643D-C449-42D1-8EA8-85BDD8C65BDE, Peim notify entry point: 7AFCB3C4 PchModPhyProgramming() - Start SOC B0 and later ModPhy Table programming PchModPhyProgramming() - End PchSataInit() - Start PchSataInit() - End InstallPchInitPpi() - End Register PPI Notify: 5BAB88BA-E0E2-4674-B6AD-B812F6881CD6 Register PPI Notify: 4B0165A9-61D6-4E23-A0B5-3EC79C2E30D5 Register PPI Notify: 30CFE3E7-3DE1-4586-BE20-DEABA1B3B793 Register PPI Notify: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B Install PPI: DD29124D-7819-4F15-BB07-351E7451D71C Install PPI: 7D84B2C2-22A1-4372-B12C-EBB232D3A6A3 Notify: PPI Guid: 7D84B2C2-22A1-4372-B12C-EBB232D3A6A3, Peim notify entry point: 7AFDE2E9 VlvInitPeiEntryPoint start.... ------------------------ VLV SSA Platform Policy dump Begin --------------- Graphics Configuration: GttSize : 2 MB IgdDvmt50PreAlloc : 2 PrimaryDisplay : 0 ApertureSize : 2 Turbo Enable : 1 ------------------------ VLV SSA Platform Policy dump END ----------------- ProgramEcBase Done.... SSASafeConfiguration Done.... Clear Dbuff to all zero before read 0xFFFFFFFF PUNIT_ISPSSPM0 value is 0x3000003 ISP Device is enabled by fuse Skip ISPConfig InitThermalRegisters Done.... IGD enabled. IGD Turbo Enable. PUNIT_BIOS_CONFIG11 = 0x400301C0. PUNIT_BIOS_CONFIG22 = 0x40030140. TotalMmioLength: 0x10400000 bytes GraphicsInit Done.... Install PPI: 09EA8911-BE0D-4230-A003-EDC693B48E11 Install mVlvPeiInitPpi Done.... Install PPI: 15344673-D365-4BE2-8513-1497CC07611D Notify: PPI Guid: 15344673-D365-4BE2-8513-1497CC07611D, Peim notify entry point: 7AFCBB94 PchInitialize() - Start PchMiscInit() - Start <<<<<<<<<<<<<<<<<< Debug log Start end >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> L&T Technology Services Ltd www.LntTechservices.com<http://www.lnttechservices.com/> This Email may contain confidential or privileged information for the intended recipient (s). If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system. -- coreboot mailing list: coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> https://www.coreboot.org/mailman/listinfo/coreboot L&T Technology Services Ltd www.LntTechservices.com<http://www.lnttechservices.com/> This Email may contain confidential or privileged information for the intended recipient (s). If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system. L&T Technology Services Ltd www.LntTechservices.com<http://www.lnttechservices.com/> This Email may contain confidential or privileged information for the intended recipient (s). If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system.

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Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay
by Mayuri Tendulkar 20 May '16

20 May '16

Hi Zoran Sorry, but I am not able to understand what you have mentioned. Can you please help me explain little detail? Sorry, but I am new to this coreboot environment. Regards Mayuri From: Zoran Stojsavljevic [mailto:zoran.stojsavljevic@gmail.com] Sent: 20 May 2016 13:39 To: Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com> Cc: coreboot <coreboot(a)coreboot.org> Subject: Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay Hello Mayuri, Not sure if I am right, but to bring GRUB 2.0 from CSM OFF and CSM ON modes, you must have two distinct HDDs, one created with CSM ON, other with CSM OFF. If you are using one with CSM ON (seems the case), your UEFI payload will not find EFI32 /boot/EFI directory created, and it does not understand MBR). Does this (what I wrote) make sense? Zoran On Fri, May 20, 2016 at 7:21 AM, Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com<mailto:mayuri.tendulkar@aricent.com>> wrote: Hi Zoran Currently we are using FSP 3. But it works fine with seabios payload. Only when I include UEFI, I am getting this issue. So I am not sure if this is related to FSP3 or 4. My query is there any additional configurations required in UEFI Payload to make it work for Minnowboard max. I see difference in addresses for UEFI and Seabios payload. Not sure where are they set. Seabios payload (working) CBFS provider active. CBFS @ 500000 size 2ff9c0 CBFS: Locating 'fallback/payload' CBFS: Found @ offset 76b40 size f782 'fallback/payload' located at offset: 576b78 size: f782 Loading segment from rom address 0xffd76b78 code (compression=1) New segment dstaddr 0xe2780 memsize 0x1d880 srcaddr 0xffd76bb0 filesize 0xf74a Loading segment from rom address 0xffd76b94 Entry Point 0x000ff06e Payload being loaded below 1MiB without region being marked as RAM usable. Bounce Buffer at 7ac50000, 451744 bytes Loading Segment: addr: 0x00000000000e2780 memsz: 0x000000000001d880 filesz: 0x000000000000f74a lb: [0x0000000000100000, 0x0000000000137250) Post relocation: addr: 0x00000000000e2780 memsz: 0x000000000001d880 filesz: 0x000000000000f74a using LZMA [ 0x000e2780, 00100000, 0x00100000) <- ffd76bb0 dest 000e2780, end 00100000, bouncebuffer 7ac50000 Loaded segments BS: BS_PAYLOAD_LOAD times (us): entry 0 run 130526 exit 0 FspNotify(EnumInitPhaseReadyToBoot) fsp_header_ptr: fffc0094 FSP Header Version: 1 FSP Revision: 3.3 Returned from FspNotify(EnumInitPhaseReadyToBoot) POST: 0x7b Jumping to boot code at 000ff06e(7acbf000) POST: 0xf8 CPU0: stack: 0012e000 - 0012f000, lowest used address 0012eb10, stack used: 1264 bytes entry = 0x000ff06e lb_start = 0x00100000 lb_size = 0x00037250 buffer = 0x7ac50000 SeaBIOS (version rel-1.9.0-127-gc8e105a) UEFI Payload logs (not working) CBFS provider active. CBFS @ 500000 size 2ff9c0 CBFS: Locating 'fallback/payload' CBFS: Found @ offset 56ec0 size 90b92 'fallback/payload' located at offset: 556ef8 size: 90b92 Loading segment from rom address 0xffd56ef8 code (compression=1) New segment dstaddr 0x800000 memsize 0x410000 srcaddr 0xffd56f30 filesize 0x90b5a Loading segment from rom address 0xffd56f14 Entry Point 0x008002c0 Bounce Buffer at 7ac34000, 437408 bytes Loading Segment: addr: 0x0000000000800000 memsz: 0x0000000000410000 filesz: 0x0000000000090b5a lb: [0x0000000000100000, 0x0000000000135650) Post relocation: addr: 0x0000000000800000 memsz: 0x0000000000410000 filesz: 0x0000000000090b5a using LZMA [ 0x00800000, 00c10000, 0x00c10000) <- ffd56f30 dest 00800000, end 00c10000, bouncebuffer 7ac34000 Loaded segments BS: BS_PAYLOAD_LOAD times (us): entry 0 run 507070 exit 0 FspNotify(EnumInitPhaseReadyToBoot) fsp_header_ptr: fffc0094 FSP Header Version: 1 FSP Revision: 3.3 Returned from FspNotify(EnumInitPhaseReadyToBoot) POST: 0x7b Jumping to boot code at 008002c0(7ac9f000) POST: 0xf8 CPU0: stack: 0012c000 - 0012d000, lowest used address 0012cb10, stack used: 1264 bytes entry = 0x008002c0 lb_start = 0x00100000 lb_size = 0x00035650 buffer = 0x7ac34000 From: Zoran Stojsavljevic [mailto:zoran.stojsavljevic@gmail.com<mailto:zoran.stojsavljevic@gmail.com>] Sent: 20 May 2016 10:44 To: Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com<mailto:mayuri.tendulkar@aricent.com>>; coreboot <coreboot(a)coreboot.org<mailto:coreboot@coreboot.org>> Subject: Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay Hello Mayuri, If I am not mistaken (I often mix BYT Coreboot @ threads in my head), you are using BYT FSP Version 3. > fsp_header_ptr: fffc0094 <== correct > FSP Header Version: 1 > FSP Revision: 3.3 <== please, use Version 4 Please, try to use the latest public BYT FSP Version 4 posted at: www.intel.com/fsp<http://www.intel.com/fsp> BAYTRAIL_FSP_GOLD_004_22-MAY-2015.fd BAYTRAIL_FSP_GOLD_004_22-MAY-2015_DEBUG.fd Don't remember deltas between V3 and V4, I thing something was wrong in V3 with MTRRs' setup, if I do not mix data in my head. INTEL also has Version 5 for a quite some time, but this one for some reasons never got publicly released. Please, report if this solved your problems. Zoran On Wed, May 18, 2016 at 6:56 AM, Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com<mailto:mayuri.tendulkar@aricent.com>> wrote: Hi While booting my Minnomboard with coreboot and UEFI, it hangs at below point while loading the payload. I followed the procedure to download latest EDK2 tree and built UEFIPAYLOAD.fd and copied it to coreboot/payloads/external/tianocore folder and gave this path in make menuconfig. Has anybody come across this? BS: BS_PAYLOAD_LOAD times (us): entry 0 run 507070 exit 0 FspNotify(EnumInitPhaseReadyToBoot) fsp_header_ptr: fffc0094 FSP Header Version: 1 FSP Revision: 3.3 Returned from FspNotify(EnumInitPhaseReadyToBoot) POST: 0x7b Jumping to boot code at 008002c0(7ac9f000) POST: 0xf8 CPU0: stack: 0012c000 - 0012d000, lowest used address 0012cb10, stack used: 1264 bytes entry = 0x008002c0 lb_start = 0x00100000 lb_size = 0x00035650 buffer = 0x7ac34000 Regards Mayuri From: Mayuri Tendulkar Sent: 17 May 2016 14:13 To: 'Zoran Stojsavljevic' <zoran.stojsavljevic(a)gmail.com<mailto:zoran.stojsavljevic@gmail.com>>; coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> Subject: RE: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay Hi Zoran and Martin Today I was able to build UEFIPAYLOAD separately. I included .fd file while building coreboot.rom. But while booting, getting some errors , so debugging those. Need to check what more customizations to be done in UEFI for Minnowmax. Has anybody tried it? Regards Mayuri From: Zoran Stojsavljevic [mailto:zoran.stojsavljevic@gmail.com] Sent: 16 May 2016 21:04 To: Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com<mailto:mayuri.tendulkar@aricent.com>>; coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> Subject: Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay OK, Mayuri, You brought an interesting point. And this point is to be not only investigated by you, rather also by me and, perhaps, Coreboot community. Since here, in Bayern/Deutschland is Holiday Day, I went to buy a beer in Munchen HBf, and while walking there I was thinking about your use case. Thinking deeper. I know that you are using some INTEL CPU/SoC (do not remember which one, if you said one). But, while recapping how BIOS looks like, I did notice that SEC and PEI phases have nothing to do with UEFI EDK2. EDK 2 comes to play in DXE phase, where EDK2 actually takes place/overtakes control... It says to me one major thing I did not notice while ago: that ARM SoCs are also eligible to run on UEFI compliant OSes, namely WIN 8.1+ (including WIN 10 and WIN 10 Athens/RT WIN 10). Which makes very interesting IOT case namely for ARM, allowing it also to compete in WIN space. Interestingly enough, this idea did not come to my mind till few hours ago... I guess, Vincent (Zimmer) already thought about that. ;-) _______ Martin (Roth) just replied, to solve this immediate mystery. probably for the beginning only for INTEL SoCs, but, I really hope, ARM will also integrate in this concept seamlessly! :-) Zoran _______ On Mon, May 16, 2016 at 2:29 PM, Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com<mailto:mayuri.tendulkar@aricent.com>> wrote: Hi Zoran I have checked that site and downloaded EDK2 code. I am trying to build it on Linux but facing some issues. But if I generate payload file separately, I need to integrate it in coreboot separately. So I am checking if there is way to build the payload in coreboot itself. Regards Mayuri From: Zoran Stojsavljevic [mailto:zoran.stojsavljevic@gmail.com<mailto:zoran.stojsavljevic@gmail.com>] Sent: 16 May 2016 17:57 To: Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com<mailto:mayuri.tendulkar@aricent.com>> Cc: coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> Subject: Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay Hello Mayuri, You should check payload called: Tiano Core (true UEFI payload). Zoran On Mon, May 16, 2016 at 2:12 PM, Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com<mailto:mayuri.tendulkar@aricent.com>> wrote: Hi Is there any mechanism to build UEFI payload directly in coreboot similar like seabios? Regards Mayuri "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." -- coreboot mailing list: coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> https://www.coreboot.org/mailman/listinfo/coreboot "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus."

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Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay
by Zoran Stojsavljevic 20 May '16

20 May '16

Hello Mayuri, Not sure if I am right, but to bring GRUB 2.0 from CSM OFF and CSM ON modes, you must have two distinct HDDs, one created with CSM ON, other with CSM OFF. If you are using one with CSM ON (seems the case), your UEFI payload will not find EFI32 /boot/EFI directory created, and it does not understand MBR). Does this (what I wrote) make sense? Zoran On Fri, May 20, 2016 at 7:21 AM, Mayuri Tendulkar < mayuri.tendulkar(a)aricent.com> wrote: > Hi Zoran > > > > Currently we are using FSP 3. But it works fine with seabios payload. > > > > Only when I include UEFI, I am getting this issue. So I am not sure if > this is related to FSP3 or 4. > > > > My query is there any additional configurations required in UEFI Payload > to make it work for Minnowboard max. > > > > I see difference in addresses for UEFI and Seabios payload. Not sure where > are they set. > > > > *Seabios payload (working)* > > > > CBFS provider active. > > CBFS @ 500000 size 2ff9c0 > > CBFS: Locating 'fallback/payload' > > CBFS: Found @ offset 76b40 size f782 > > 'fallback/payload' located at offset: 576b78 size: f782 > > Loading segment from rom address 0xffd76b78 > > code (compression=1) > > New segment dstaddr 0xe2780 memsize 0x1d880 srcaddr 0xffd76bb0 filesize > 0xf74a > > Loading segment from rom address 0xffd76b94 > > Entry Point 0x000ff06e > > Payload being loaded below 1MiB without region being marked as RAM usable. > > Bounce Buffer at 7ac50000, 451744 bytes > > Loading Segment: addr: 0x00000000000e2780 memsz: 0x000000000001d880 > filesz: 0x000000000000f74a > > lb: [0x0000000000100000, 0x0000000000137250) > > Post relocation: addr: 0x00000000000e2780 memsz: 0x000000000001d880 > filesz: 0x000000000000f74a > > using LZMA > > [ 0x000e2780, 00100000, 0x00100000) <- ffd76bb0 > > dest 000e2780, end 00100000, bouncebuffer 7ac50000 > > Loaded segments > > BS: BS_PAYLOAD_LOAD times (us): entry 0 run 130526 exit 0 > > FspNotify(EnumInitPhaseReadyToBoot) > > fsp_header_ptr: fffc0094 > > FSP Header Version: 1 > > FSP Revision: 3.3 > > Returned from FspNotify(EnumInitPhaseReadyToBoot) > > POST: 0x7b > > Jumping to boot code at 000ff06e(7acbf000) > > POST: 0xf8 > > CPU0: stack: 0012e000 - 0012f000, lowest used address 0012eb10, stack > used: 1264 bytes > > entry = 0x000ff06e > > lb_start = 0x00100000 > > lb_size = 0x00037250 > > buffer = 0x7ac50000 > > SeaBIOS (version rel-1.9.0-127-gc8e105a) > > > > > > > > *UEFI Payload logs (not working)* > > > > CBFS provider active. > > CBFS @ 500000 size 2ff9c0 > > CBFS: Locating 'fallback/payload' > > CBFS: Found @ offset 56ec0 size 90b92 > > '*fallback/payload' located at offset: 556ef8 size: 90b92* > > *L*oading segment from rom address 0xffd56ef8 > > code (compression=1) > > *New segment dstaddr 0x800000 memsize 0x410000 srcaddr 0xffd56f30 > filesize 0x90b5a* > > Loading segment from rom address 0xffd56f14 > > Entry Point 0x008002c0 > > Bounce Buffer at 7ac34000, 437408 bytes > > Loading Segment: addr: 0x0000000000800000 memsz: 0x0000000000410000 > filesz: 0x0000000000090b5a > > lb: [0x0000000000100000, 0x0000000000135650) > > Post relocation: addr: 0x0000000000800000 memsz: 0x0000000000410000 > filesz: 0x0000000000090b5a > > using LZMA > > [ 0x00800000, 00c10000, 0x00c10000) <- ffd56f30 > > dest 00800000, end 00c10000, bouncebuffer 7ac34000 > > Loaded segments > > BS: BS_PAYLOAD_LOAD times (us): entry 0 run 507070 exit 0 > > FspNotify(EnumInitPhaseReadyToBoot) > > fsp_header_ptr: fffc0094 > > FSP Header Version: 1 > > FSP Revision: 3.3 > > Returned from FspNotify(EnumInitPhaseReadyToBoot) > > POST: 0x7b > > Jumping to boot code at 008002c0(7ac9f000) > > POST: 0xf8 > > CPU0: stack: 0012c000 - 0012d000, lowest used address 0012cb10, stack > used: 1264 bytes > > entry = 0x008002c0 > > lb_start = 0x00100000 > > lb_size = 0x00035650 > > buffer = 0x7ac34000 > > > > *From:* Zoran Stojsavljevic [mailto:zoran.stojsavljevic@gmail.com] > *Sent:* 20 May 2016 10:44 > *To:* Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com>; coreboot < > coreboot(a)coreboot.org> > > *Subject:* Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard > or Bayley bay > > > > Hello Mayuri, > > > > If I am not mistaken (I often mix BYT Coreboot @ threads in my head), you > are using BYT FSP Version 3. > > > > > fsp_header_ptr: fffc0094 <== correct > > > FSP Header Version: 1 > > > FSP Revision: 3.3 <== please, use Version 4 > > > > Please, try to use the latest public BYT FSP Version 4 posted at: > www.intel.com/fsp > > > > *BAYTRAIL_FSP_GOLD_004_22-MAY-2015.fd* > > *BAYTRAIL_FSP_GOLD_004_22-MAY-2015_DEBUG.fd* > > > > Don't remember deltas between V3 and V4, I thing something was wrong in V3 > with MTRRs' setup, if I do not mix data in my head. > > > > INTEL also has Version 5 for a quite some time, but this one for some > reasons never got publicly released. > > > > Please, report if this solved your problems. > > > > Zoran > > > > On Wed, May 18, 2016 at 6:56 AM, Mayuri Tendulkar < > mayuri.tendulkar(a)aricent.com> wrote: > > Hi > > > > While booting my Minnomboard with coreboot and UEFI, it hangs at below > point while loading the payload. > > > > I followed the procedure to download latest EDK2 tree and built > UEFIPAYLOAD.fd and copied it to coreboot/payloads/external/tianocore > folder and gave this path in make menuconfig. > > > > Has anybody come across this? > > > > BS: BS_PAYLOAD_LOAD times (us): entry 0 run 507070 exit 0 > > FspNotify(EnumInitPhaseReadyToBoot) > > fsp_header_ptr: fffc0094 > > FSP Header Version: 1 > > FSP Revision: 3.3 > > Returned from FspNotify(EnumInitPhaseReadyToBoot) > > POST: 0x7b > > Jumping to boot code at 008002c0(7ac9f000) > > POST: 0xf8 > > CPU0: stack: 0012c000 - 0012d000, lowest used address 0012cb10, stack > used: 1264 bytes > > entry = 0x008002c0 > > lb_start = 0x00100000 > > lb_size = 0x00035650 > > buffer = 0x7ac34000 > > > > Regards > > Mayuri > > *From:* Mayuri Tendulkar > *Sent:* 17 May 2016 14:13 > *To:* 'Zoran Stojsavljevic' <zoran.stojsavljevic(a)gmail.com>; > coreboot(a)coreboot.org > *Subject:* Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard > or Bayley bay > > > > Hi Zoran and Martin > > > > Today I was able to build UEFIPAYLOAD separately. I included .fd file > while building coreboot.rom. > > > > But while booting, getting some errors , so debugging those. > > > > Need to check what more customizations to be done in UEFI for Minnowmax. > > > > Has anybody tried it? > > > > Regards > > Mayuri > > > > *From:* Zoran Stojsavljevic [mailto:zoran.stojsavljevic@gmail.com > <zoran.stojsavljevic(a)gmail.com>] > *Sent:* 16 May 2016 21:04 > *To:* Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com>; > coreboot(a)coreboot.org > *Subject:* Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard > or Bayley bay > > > > OK, Mayuri, > > > > You brought an interesting point. And this point is to be not only > investigated by you, rather also by me and, perhaps, Coreboot community. > > > > Since here, in Bayern/Deutschland is Holiday Day, I went to buy a beer in > Munchen HBf, and while walking there I was thinking about your use case. > Thinking deeper. > > > > I know that you are using some INTEL CPU/SoC (do not remember which one, > if you said one). But, while recapping how BIOS looks like, I did notice > that SEC and PEI phases have nothing to do with UEFI EDK2. EDK 2 comes to > play in DXE phase, where EDK2 actually takes place/overtakes control... > > > > It says to me one major thing I did not notice while ago: that ARM SoCs > are also eligible to run on UEFI compliant OSes, namely WIN 8.1+ (including > WIN 10 and WIN 10 Athens/RT WIN 10). Which makes very interesting IOT case > namely for ARM, allowing it also to compete in WIN space. > > > > Interestingly enough, this idea did not come to my mind till few hours > ago... I guess, Vincent (Zimmer) already thought about that. ;-) > > _______ > > > > Martin (Roth) just replied, to solve this immediate mystery. probably for > the beginning only for INTEL SoCs, but, I really hope, ARM will also > integrate in this concept seamlessly! :-) > > > > Zoran > > _______ > > > > On Mon, May 16, 2016 at 2:29 PM, Mayuri Tendulkar < > mayuri.tendulkar(a)aricent.com> wrote: > > Hi Zoran > > > > I have checked that site and downloaded EDK2 code. I am trying to build it > on Linux but facing some issues. > > But if I generate payload file separately, I need to integrate it in > coreboot separately. > > > > So I am checking if there is way to build the payload in coreboot itself. > > > > Regards > > Mayuri > > > > *From:* Zoran Stojsavljevic [mailto:zoran.stojsavljevic@gmail.com] > *Sent:* 16 May 2016 17:57 > *To:* Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com> > *Cc:* coreboot(a)coreboot.org > *Subject:* Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard > or Bayley bay > > > > Hello Mayuri, > > > > You should check payload called: Tiano Core (true UEFI payload). > > > > Zoran > > > > > > On Mon, May 16, 2016 at 2:12 PM, Mayuri Tendulkar < > mayuri.tendulkar(a)aricent.com> wrote: > > Hi > > > > Is there any mechanism to build UEFI payload directly in coreboot similar > like seabios? > > > > Regards > > Mayuri > > "DISCLAIMER: This message is proprietary to Aricent and is intended solely > for the use of the individual to whom it is addressed. It may contain > privileged or confidential information and should not be circulated or used > for any purpose other than for what it is intended. If you have received > this message in error, please notify the originator immediately. If you are > not the intended recipient, you are notified that you are strictly > prohibited from using, copying, altering, or disclosing the contents of > this message. Aricent accepts no responsibility for loss or damage arising > from the use of the information transmitted by this email including damage > from virus." > > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot > > > > "DISCLAIMER: This message is proprietary to Aricent and is intended solely > for the use of the individual to whom it is addressed. It may contain > privileged or confidential information and should not be circulated or used > for any purpose other than for what it is intended. If you have received > this message in error, please notify the originator immediately. If you are > not the intended recipient, you are notified that you are strictly > prohibited from using, copying, altering, or disclosing the contents of > this message. Aricent accepts no responsibility for loss or damage arising > from the use of the information transmitted by this email including damage > from virus." > > > > "DISCLAIMER: This message is proprietary to Aricent and is intended solely > for the use of the individual to whom it is addressed. It may contain > privileged or confidential information and should not be circulated or used > for any purpose other than for what it is intended. If you have received > this message in error, please notify the originator immediately. If you are > not the intended recipient, you are notified that you are strictly > prohibited from using, copying, altering, or disclosing the contents of > this message. Aricent accepts no responsibility for loss or damage arising > from the use of the information transmitted by this email including damage > from virus." > > > "DISCLAIMER: This message is proprietary to Aricent and is intended solely > for the use of the individual to whom it is addressed. It may contain > privileged or confidential information and should not be circulated or used > for any purpose other than for what it is intended. If you have received > this message in error, please notify the originator immediately. If you are > not the intended recipient, you are notified that you are strictly > prohibited from using, copying, altering, or disclosing the contents of > this message. Aricent accepts no responsibility for loss or damage arising > from the use of the information transmitted by this email including damage > from virus." >

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Re: [coreboot] [baytrail_FSP] question about lpss device with ACPI mode in win8
by Zoran Stojsavljevic 20 May '16

20 May '16

Hello Chang, Just replace these info in my latest email (regarding BYT FSP and Coreboot). The later use case and questions remain the same. Thank you, Zoran On Fri, May 20, 2016 at 9:16 AM, cheng yichen <blessyichen(a)gmail.com> wrote: > Hi Zoran > > Sorry for the information is not clear. The MR5 that I mean is intel > release coreboot source code and FSP in intel web side. In the debug > message I find the version is coreboot4.0. > > in my previous mail, the MR5 is included intel coreboot source code and > FSP package. > > Thank you > > 2016-05-17 11:36 GMT+08:00 Zoran Stojsavljevic < > zoran.stojsavljevic(a)gmail.com>: > >> Hello Cheng, >> >> I am afraid, I have no ideas anymore what could be wrong. But I have for >> you one suggestion (path to resolution, maybe). >> >> No idea what you are using. In the sense BYT-FSP (MR5) -> Coreboot -> >> (payload???). You either use SeaBIOS (CSM ON), or Tiano Core/EK2 (CSM OFF). >> >> I would suggest the following: since it depends what payload you use >> because you would like to reuse your old HDD with WIN 8.1, to make test >> very short (no need to install other HDD with WIN 8.1). >> >> Please, take real UEFI BIOS (for BYT-M N2807 it is Client Group 64bit >> A093.R42 or later), and install it on some INTEL CRB (BayleyBay or >> BakerSport) where you already have N2807. Then, in relations what payload >> you are using, you need to set CSM ON or CSM OFF, to make work/reuse your >> original HDD with WIN 8.1. >> >> Please, after you are able to bring your INTEL BYT-M CRB to WIN 8.1, >> reboot, and again enter BIOS CMOS. There, under system setup/advanced >> settings, you should be able to find southbridge setup, where one of the >> options is LPSS. >> >> Please, experiment, with settings within LPSS mode (PCI and ACPI), and, >> please, report here do you have the same as with BYT-FSP MR5 settings as >> you use "pcdlpsssioenablepcimode" to "LPSS_PCI_MODE_DISABLE" and >> "ENABLE/DEFAULT" (do you see the same behavior in WIN 8.1 device manager)? >> >> Thank you, >> Zoran >> >> On Mon, May 16, 2016 at 2:06 PM, cheng yichen <blessyichen(a)gmail.com> >> wrote: >> >>> Hi Zoran >>> >>> Base on the version Baytrail_coreboot_MR5_Dec-21-2015(coreboot) that is >>> released by Intel. >>> In the coreboot(Intel released and defautle is acpi mode) I can install >>> driver and device is workable in win8. >>> I can see hs-uart controller in device manage and no yellow mark. >>> >>> In last coreboot source code. after I modify "pcdlpsssioenablepcimode" >>> to "LPSS_PCI_MODE_DISABLE". Then the lpss device will be confgured to ACPI >>> mode. >>> but the hs-uart controller and I2C controller will shown yellow mark in >>> win8 device manager. >>> Because the main controller is not workable in win8. I don't check the >>> sub-device device. >>> >>> >>> >>> >>> >>> 2016-05-16 17:16 GMT+08:00 Zoran Stojsavljevic < >>> zoran.stojsavljevic(a)gmail.com>: >>> >>>> Hello Cheng, >>>> >>>> Again, I'll repeat my questions: >>>> [1] Are you talking about BIOS, where you are enabling in LPSS ACPI >>>> (disabling automatically PCI) mode? >>>> [2] I need better explanation of your use case... Are you using BYT >>>> MR4, then MR5, or instead MR4 BIOS, or...? >>>> [3] For WIN8.1 you need to have the following: >>>> For BIOS to work (and get rid off these yellow triangles with >>>> question marks): >>>> [A] ACPI mode in BIOS: South Cluster Configuration -> LPSS & SCC >>>> Configuration -> LPSS LPSS & SCC >>>> Devices Mode -> Select "ACPI Mode"; >>>> [B] The GPIO controller driver is/should be prerequisite for >>>> HS-UART driver. There is a document named: >>>> Intel_Processor_Win8_IO_Drivers_Gold_MR1. You should ask >>>> for it from INTEL support. If installed >>>> correctly, you should see HS-UART Controller device under >>>> System Devices in Device Manager. Also >>>> new unknown devices should appear: ACPI\BCM2E1A and >>>> ACPI\BCM4752. These devices are for >>>> HS-UART Sub Device Driver; >>>> [C] You should compile the UART Sub Device Driver (by 1.2.1 of >>>> Intel Atom E3800 Win8.1 HS-UART Sub >>>> Device Driver Sample Code Guide_1.0), and install after >>>> building them. After that you should see Ports in >>>> Device Manager. >>>> >>>> Zoran >>>> >>>> On Fri, May 13, 2016 at 5:43 AM, cheng yichen <blessyichen(a)gmail.com> >>>> wrote: >>>> >>>>> >>>>> HI all >>>>> >>>>> I try to enable Lpss device(i2c hs-uart) with ACPI mdoe. >>>>> i2c and hs-uart will show yellow mark in device manager with win8.1. >>>>> but I can't find the same issue in intel coreboot(versrion MR5). >>>>> Do you have any idea for the issue? Thank you >>>>> >>>>> -- >>>>> coreboot mailing list: coreboot(a)coreboot.org >>>>> https://www.coreboot.org/mailman/listinfo/coreboot >>>>> >>>> >>>> >>> >> > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot >

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Re: [coreboot] [baytrail_FSP] question about lpss device with ACPI mode in win8
by cheng yichen 20 May '16

20 May '16

Hi Zoran Sorry for the information is not clear. The MR5 that I mean is intel release coreboot source code and FSP in intel web side. In the debug message I find the version is coreboot4.0. in my previous mail, the MR5 is included intel coreboot source code and FSP package. Thank you 2016-05-17 11:36 GMT+08:00 Zoran Stojsavljevic < zoran.stojsavljevic(a)gmail.com>: > Hello Cheng, > > I am afraid, I have no ideas anymore what could be wrong. But I have for > you one suggestion (path to resolution, maybe). > > No idea what you are using. In the sense BYT-FSP (MR5) -> Coreboot -> > (payload???). You either use SeaBIOS (CSM ON), or Tiano Core/EK2 (CSM OFF). > > I would suggest the following: since it depends what payload you use > because you would like to reuse your old HDD with WIN 8.1, to make test > very short (no need to install other HDD with WIN 8.1). > > Please, take real UEFI BIOS (for BYT-M N2807 it is Client Group 64bit > A093.R42 or later), and install it on some INTEL CRB (BayleyBay or > BakerSport) where you already have N2807. Then, in relations what payload > you are using, you need to set CSM ON or CSM OFF, to make work/reuse your > original HDD with WIN 8.1. > > Please, after you are able to bring your INTEL BYT-M CRB to WIN 8.1, > reboot, and again enter BIOS CMOS. There, under system setup/advanced > settings, you should be able to find southbridge setup, where one of the > options is LPSS. > > Please, experiment, with settings within LPSS mode (PCI and ACPI), and, > please, report here do you have the same as with BYT-FSP MR5 settings as > you use "pcdlpsssioenablepcimode" to "LPSS_PCI_MODE_DISABLE" and > "ENABLE/DEFAULT" (do you see the same behavior in WIN 8.1 device manager)? > > Thank you, > Zoran > > On Mon, May 16, 2016 at 2:06 PM, cheng yichen <blessyichen(a)gmail.com> > wrote: > >> Hi Zoran >> >> Base on the version Baytrail_coreboot_MR5_Dec-21-2015(coreboot) that is >> released by Intel. >> In the coreboot(Intel released and defautle is acpi mode) I can install >> driver and device is workable in win8. >> I can see hs-uart controller in device manage and no yellow mark. >> >> In last coreboot source code. after I modify "pcdlpsssioenablepcimode" to >> "LPSS_PCI_MODE_DISABLE". Then the lpss device will be confgured to ACPI >> mode. >> but the hs-uart controller and I2C controller will shown yellow mark in >> win8 device manager. >> Because the main controller is not workable in win8. I don't check the >> sub-device device. >> >> >> >> >> >> 2016-05-16 17:16 GMT+08:00 Zoran Stojsavljevic < >> zoran.stojsavljevic(a)gmail.com>: >> >>> Hello Cheng, >>> >>> Again, I'll repeat my questions: >>> [1] Are you talking about BIOS, where you are enabling in LPSS ACPI >>> (disabling automatically PCI) mode? >>> [2] I need better explanation of your use case... Are you using BYT MR4, >>> then MR5, or instead MR4 BIOS, or...? >>> [3] For WIN8.1 you need to have the following: >>> For BIOS to work (and get rid off these yellow triangles with >>> question marks): >>> [A] ACPI mode in BIOS: South Cluster Configuration -> LPSS & SCC >>> Configuration -> LPSS LPSS & SCC >>> Devices Mode -> Select "ACPI Mode"; >>> [B] The GPIO controller driver is/should be prerequisite for >>> HS-UART driver. There is a document named: >>> Intel_Processor_Win8_IO_Drivers_Gold_MR1. You should ask for >>> it from INTEL support. If installed >>> correctly, you should see HS-UART Controller device under >>> System Devices in Device Manager. Also >>> new unknown devices should appear: ACPI\BCM2E1A and >>> ACPI\BCM4752. These devices are for >>> HS-UART Sub Device Driver; >>> [C] You should compile the UART Sub Device Driver (by 1.2.1 of >>> Intel Atom E3800 Win8.1 HS-UART Sub >>> Device Driver Sample Code Guide_1.0), and install after >>> building them. After that you should see Ports in >>> Device Manager. >>> >>> Zoran >>> >>> On Fri, May 13, 2016 at 5:43 AM, cheng yichen <blessyichen(a)gmail.com> >>> wrote: >>> >>>> >>>> HI all >>>> >>>> I try to enable Lpss device(i2c hs-uart) with ACPI mdoe. >>>> i2c and hs-uart will show yellow mark in device manager with win8.1. >>>> but I can't find the same issue in intel coreboot(versrion MR5). >>>> Do you have any idea for the issue? Thank you >>>> >>>> -- >>>> coreboot mailing list: coreboot(a)coreboot.org >>>> https://www.coreboot.org/mailman/listinfo/coreboot >>>> >>> >>> >> >

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coreboot May 2016