coreboot May 2016

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Re: [coreboot] coreboot with fsp hangs at post code 19 on Bayley Bay
by Naveed Ghori 31 May '16

31 May '16

Kathappan, Not sure if you have gotten any further but I have a couple of suggestions since I am now at the Seabios stage of booting. Do you have the FITC tool? Intel may be able to provide it to you (requires an NDA or SLA) . There is one on the web however that should work too. I can reproduce a log that ends where your log ends if I simply change the DELAY_PCIE_RLS soft strap (SOC strap 4) so you may wish to try that. Hope this helps, Naveed. From: Naveed Ghori Sent: Wednesday, 18 May 2016 2:18 PM To: 'Zoran Stojsavljevic'; Kathappan E; naveed.ghori(a)dti.com Cc: Zeh, Werner; coreboot Subject: RE: [coreboot] coreboot with fsp hangs at post code 19 on Bayley Bay Zoran, Thanks for the quick reply. I managed to find FITC form a non-intel site and am playing with it. For my vendor supplied current image (loaded as a bin) PCIe is enabled (false). Images I created with FITC currently do not enter load and stop at POST 0x92. I will play with a bit more to try and get my image back to starting into ramstage (where it currently crashes). Regards, Naveed. From: coreboot [mailto:coreboot-bounces@coreboot.org] On Behalf Of Zoran Stojsavljevic Sent: Tuesday, 17 May 2016 6:21 PM To: Kathappan E; naveed.ghori(a)dti.com<mailto:naveed.ghori@dti.com> Cc: Zeh, Werner; coreboot Subject: Re: [coreboot] coreboot with fsp hangs at post code 19 on Bayley Bay Hello Kathappan, Naveed (I am lazy to reply to separate @s), [1/2] I'll answer these two topics altogether. YES, I am asking for that. It is after all E3825, and this SKU has significant difference comparing to E3826, E3827 (not sure about this one), and E3845. All of them are dual-channel DDR3, while E3825 is SINGLE-channel one. YES, YES, you have correct setup, which is NOT at all important for this topic (sorry, I had to ask you before... Maneuvering in The Dark). [3] Here is The IMPORTANT for you: the mentioned PCIe settings are not a part of FSP but rather part of the descriptor. In the descriptor, soft straps are configured and loaded into the hardware upon reset release. The strapping can be modified using FITC tool, which is used to configure the flash image and ME/TXE. If PCIe lanes are disabled in descriptor, Coreboot per default can’t see these PCIe ports. You have to modify the descriptor using Flash Image Configuration Tool (FITC) distributed with the TXE package for Bay Trail. [Inline image 1] Werner, I would like to thank you you for enlightening me (I remembered/recalled our private discussion once upon a time about this topic)... I do need to do further analyses/actions, and teach one seldom old dog (me) the new tricks (they/general public by default say the opposite). ;-) I sincere hope this @ helps to both of you (TO: list - K and N), and NOT only. Zoran _______ On Tue, May 17, 2016 at 10:49 AM, Kathappan E <Kathappan.E(a)lnttechservices.com<mailto:Kathappan.E@lnttechservices.com>> wrote: Hi Zoran, Sorry for the late reply since I had a long week end here. Thanks for your comments. [1] Which BYT SoC you are using (example BYT-M N2807)? Bayley Bay custom board (not a CRB) which is based Atom E3825 and D0 stepping SoC. But I am not sure whether you are asking this. [2] How many DDR3 channels (1 or 2) are you using in your design, and what is the size of memory (most likely not a problem)? Single channel non-ECC 1333/1066 MHz soldered DDR3L memory up to 4GB. DIMM0 is populated with 2 GB and DIMM1 is disabled [3] PCH. Do you have PCIe channels initialized/set in default soft straps (you must have some, at least PCIe root port 0, and PCIe root port 1, as I recalled)? <<==== IMPORTANT? I didn’t see any PCIe related settings available in bsf file(attached) to edit it. Can you please help me more on it to change ? 3 PCIe x1 Gen2 port (0 - 2) , 1 PCIe x1 Gen2 port 3 - GBE Thanks, Kathappan From: Zoran Stojsavljevic [mailto:zoran.stojsavljevic@gmail.com<mailto:zoran.stojsavljevic@gmail.com>] Sent: 17 May 2016 09:16 To: Kathappan E <Kathappan.E(a)LntTechservices.com<mailto:Kathappan.E@LntTechservices.com>>; coreboot <coreboot(a)coreboot.org<mailto:coreboot@coreboot.org>> Subject: Re: [coreboot] coreboot with fsp hangs at post code 19 on Bayley Bay Hello Kathappan, Did you try to (using BCT) to enable PCIe x1, at least PCIe0 and PCIe1 (the same size x1)? Does it work now? Thank you, Zoran On Fri, May 13, 2016 at 9:51 PM, Zoran Stojsavljevic <zoran.stojsavljevic(a)gmail.com<mailto:zoran.stojsavljevic@gmail.com>> wrote: Hello Kathappan, I need to look deeper into this area since I am not expert on FSP, but I have some ideas what could be wrong. Several questions for you: [1] Which BYT SoC you are using (example BYT-M N2807)? [2] How many DDR3 channels (1 or 2) are you using in your design, and what is the size of memory (most likely not a problem)? [3] PCH. Do you have PCIe channels initialized/set in default soft straps (you must have some, at least PCIe root port 0, and PCIe root port 1, as I recalled)? <<==== IMPORTANT? Again, I need to think more about this, and I'll try to find some answers, later... Please, try to see/discover [3] using BCT tool! Zoran _______ On Fri, May 13, 2016 at 3:01 PM, Kathappan E <Kathappan.E(a)lnttechservices.com<mailto:Kathappan.E@lnttechservices.com>> wrote: Hi all, When I try coreboot on Bayley Bay platform along with fsp (BAYTRAIL_FSP_GOLD_004_22-MAY-2015), it is getting hang at post code 19. Also I tried with debug version fsp (BAYTRAIL_FSP_GOLD_004_22-MAY-2015_DEBUG) , it still at that point and below is the debug log. Firmware Image: Have used the 8 MB vendor bios and flashed the last 2 MB region(600000 to 7fffff) with coreboot image. From the debug log: coreboot gives the control to FSP binary routine(FspInitApi) and it is getting hang when trying to do PCH initialize(PchMiscInit) inside FSP part code. POST 19 code info: EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_CLOCK_PEI_INIT_ENTRY ==> Clock Init PEIM Entry I have not seen the clock related setting available when customizing fsp binary using BCT. I tried to disable south cluster component such as EMMC,HSUART,SATA and SIO using BCT , it didn't help me. Can anyone please help me provide some inputs such as related below to proceed further debugging on it ? 1. Any other setting we can try out using BCT 2. About devices configuration to be initialized byPchMiscInit function. 3. Anything need to be cared/double checked from coreboot side in order to giving control to FspInitApi function. 4. Does pch straps settings may cause this since I am using upper 6 MB region flash data which is from vendor bios. 4. Please suggest anything on it. Thanks in advance, Kathappan <<<<<<<<<<<< Debug log Start >>>>>>>>>>>>>>> coreboot-coreboot-unknown Thu May 12 08:04:42 UTC 2016 romstage starting... RTC Init POST: 0x44 POST: 0x47 POST: 0x48 Starting the Intel FSP (early_init) PM1_STS = 0x0 PM1_CNT = 0x0 GEN_PMCON1 = 0x44000 prev_sleep_state = S5 Configure Default UPD Data PcdMrcInitSPDAddr1: 0xa0 (default) PcdMrcInitSPDAddr2: 0xa2 (default) PcdSataMode: 0x01 (set) PcdLpssSioEnablePciMode: 0x01 (default) PcdMrcInitMmioSize: 0x800 (default) PcdIgdDvmt50PreAlloc: 0x02 (default) PcdApertureSize: 0x02 (default) PcdGttSize: 0x02 (default) SerialDebugPortAddress: 0x3f8 (default) SerialDebugPortType: 0x01 (default) PcdMrcDebugMsg: 0x01 (default) PcdSccEnablePciMode: 0x01 (default) IgdRenderStandby: 0x00 (default) TxeUmaEnable: 0x00 (default) PcdOsSelection: 0x04 (default) PcdEMMC45DDR50Enabled: 0x01 (default) PcdEMMC45HS200Enabled: 0x00 (default) PcdEMMC45RetuneTimerValue: 0x08 (default) PcdEnableIgd: 0x01 (default) AutoSelfRefreshEnable: 0x00 (default) APTaskTimeoutCnt: 0x00 (default) GTT Size: 2 MB Tseg Size: 8 MB Aperture Size: 256 MB IGD Memory Size: 64 MB MMIO Size: 2048 MB MIPI/ISP: Disabled Sdio: Enabled Sdcard: Enabled SATA: Enabled SIO Dma 0: Enabled SIO I2C0: Enabled SIO I2C1: Enabled SIO I2C2: Enabled SIO I2C3: Enabled SIO I2C4: Enabled SIO I2C5: Enabled SIO I2C6: Enabled Azalia: Enabled SIO Dma1: Enabled Pwm0: Enabled Pwm1: Enabled Hsuart0: Enabled Hsuart1: Enabled Spi: Enabled Lpe: Disabled eMMC Mode: eMMC 4.5 SATA Mode: AHCI Xhci: Enabled POST: 0x92 ============= PEIM FSP (VLYVIEW0 0x00000304) ============= Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3 Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A The 0th FV start address is 0x000FFFE0400, size is 0x00017C00, handle is 0x0 Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39 Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38 Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6 Install PPI: DBE23AA9-A345-4B97-85B6-B226F1617389 Install PPI: 06E81C58-4AD7-44BC-8390-F10265F72480 Install PPI: 01F34D25-4DE2-23AD-3FF3-36353FF323F1 Install PPI: 49EDB1C1-BF21-4761-BB12-EB0031AABB39 Notify: PPI Guid: 49EDB1C1-BF21-4761-BB12-EB0031AABB39, Peim notify entry point: FFFE0FD4 The 1th FV start address is 0x000FFFB0000, size is 0x0002F400, handle is 0xFFFB0000 Install PPI: A55D6970-1306-440C-8C72-8F51FAFB2926 PcdMrcInitTsegSize = 8 PcdMrcInitMmioSize = 800 PcdMrcInitSPDAddr1 = A0 PcdMrcInitSPDAddr2 = A2 Setting BootMode to 0 Install PPI: 1F4C6F90-B06B-48D8-A201-BAE5F1CD7D56 Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE About to call MrcInit(); BayleyBay Platform Type RID = 0x11. Reg_EFF_DualCH_EN = 0x40030040. CurrentMrcData.BootMode = 4 C1.D0: SPD not present. Configuring Memory Start... START_RMT: RxDqLeft RxDqRight RxVLow RxVHigh TxDqLeft TxDqRight CmdLeft CmdRight ------------------------------------------------------------------------------------------------ Channel 0 Rank 0 -22 21 -21 19 -25 26 0 0 STOP_RMT: CMD module is per channel only and without Rank differentiation Configuring Memory End UpperTotalMemory = 0x80000000 dBMBOUND = 0x80000000 dBMBOUNDHI = 0x80000000 dGFXBase = 0x7BE00000 dTSegBase = 0x7B000000 Save MRC params. Current MRC Data DDR Freq 1 Current MRC Data Core Freq 1 Current MRC Data Tcl 7 Current MRC Data WL 6 Current MRC Data DDRType 1 Current MRC Data MMIO Size 800 Current MRC Data TSeg Size 8 Channel 0 Enabled 1 Socket 0 DimmPresent 1 DimmDataWidth 1 DimmBusWidth 3 DimmSize 2 DimmSides 0 Channel 1 Enabled 0 Socket 0 DimmPresent 0 DimmDataWidth 0 DimmBusWidth 0 DimmSize 0 DimmSides 0 Current MRC Timing Data MRC_DATA_TRP 7 Current MRC Timing Data MRC_DATA_TRCD 7 Current MRC Timing Data MRC_DATA_TRAS 13 Current MRC Timing Data MRC_DATA_TWR 8 Current MRC Timing Data MRC_DATA_TWTR 4 Current MRC Timing Data MRC_DATA_TRRD 4 Current MRC Timing Data MRC_DATA_TRTP 4 Current MRC Timing Data MRC_DATA_TFAW 1B PeiInstallPeiMemory MemoryBegin 0x7AE00000, MemoryLength 0x200000 Old Stack size 24576, New stack size 131072 Heap Offset = 0x0 Stack Offset = 0x840F0000 Stack Hob: BaseAddress=0x7AE00000 Length=0x20000 Reinstall PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3 Reinstall PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A Reinstall PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6 Install PPI: F894643D-C449-42D1-8EA8-85BDD8C65BDE Notify: PPI Guid: F894643D-C449-42D1-8EA8-85BDD8C65BDE, Peim notify entry point: FFFC1281 Install PPI: 0AE8CE5D-E448-4437-A8D7-EBF5F194F731 Install PPI: 1A36E4E7-FAB6-476A-8E75-695A0576FDD7 Install PPI: EF398D58-9DFD-4103-BF94-78C6F4FE712F InstallVlvInitPpi() - Start Register PPI Notify: 7D84B2C2-22A1-4372-B12C-EBB232D3A6A3 InstallVlvInitPpi() - End InstallPchInitPpi() - Start PmcBase needs to be programmed and enabled before here. ProgramGpioSCForSDCardWA Done.... Register PPI Notify: 15344673-D365-4BE2-8513-1497CC07611D Register PPI Notify: 00B710BA-8CD6-4BF3-AB7A-9A24F54CC334 Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE Notify: PPI Guid: F894643D-C449-42D1-8EA8-85BDD8C65BDE, Peim notify entry point: 7AFCB3C4 PchModPhyProgramming() - Start SOC B0 and later ModPhy Table programming PchModPhyProgramming() - End PchSataInit() - Start PchSataInit() - End InstallPchInitPpi() - End Register PPI Notify: 5BAB88BA-E0E2-4674-B6AD-B812F6881CD6 Register PPI Notify: 4B0165A9-61D6-4E23-A0B5-3EC79C2E30D5 Register PPI Notify: 30CFE3E7-3DE1-4586-BE20-DEABA1B3B793 Register PPI Notify: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B Install PPI: DD29124D-7819-4F15-BB07-351E7451D71C Install PPI: 7D84B2C2-22A1-4372-B12C-EBB232D3A6A3 Notify: PPI Guid: 7D84B2C2-22A1-4372-B12C-EBB232D3A6A3, Peim notify entry point: 7AFDE2E9 VlvInitPeiEntryPoint start.... ------------------------ VLV SSA Platform Policy dump Begin --------------- Graphics Configuration: GttSize : 2 MB IgdDvmt50PreAlloc : 2 PrimaryDisplay : 0 ApertureSize : 2 Turbo Enable : 1 ------------------------ VLV SSA Platform Policy dump END ----------------- ProgramEcBase Done.... SSASafeConfiguration Done.... Clear Dbuff to all zero before read 0xFFFFFFFF PUNIT_ISPSSPM0 value is 0x3000003 ISP Device is enabled by fuse Skip ISPConfig InitThermalRegisters Done.... IGD enabled. IGD Turbo Enable. PUNIT_BIOS_CONFIG11 = 0x400301C0. PUNIT_BIOS_CONFIG22 = 0x40030140. TotalMmioLength: 0x10400000 bytes GraphicsInit Done.... Install PPI: 09EA8911-BE0D-4230-A003-EDC693B48E11 Install mVlvPeiInitPpi Done.... Install PPI: 15344673-D365-4BE2-8513-1497CC07611D Notify: PPI Guid: 15344673-D365-4BE2-8513-1497CC07611D, Peim notify entry point: 7AFCBB94 PchInitialize() - Start PchMiscInit() - Start <<<<<<<<<<<<<<<<<< Debug log Start end >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> L&T Technology Services Ltd www.LntTechservices.com<http://www.lnttechservices.com/> This Email may contain confidential or privileged information for the intended recipient (s). If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system. -- coreboot mailing list: coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> https://www.coreboot.org/mailman/listinfo/coreboot L&T Technology Services Ltd www.LntTechservices.com<http://www.lnttechservices.com/> This Email may contain confidential or privileged information for the intended recipient (s). If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system.

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Re: [coreboot] Debug builds and memory testing
by Naveed Ghori 31 May '16

31 May '16

To clarify. DDR3L is the correct one to use (I was wrongly using DDR3) From: Naveed Ghori Sent: Tuesday, 31 May 2016 12:45 PM To: 'Mayuri Tendulkar'; coreboot Subject: Re: Debug builds and memory testing I was using DDR3 instead of the low voltage DDR3L From: Mayuri Tendulkar [mailto:mayuri.tendulkar@aricent.com] Sent: Tuesday, 31 May 2016 12:40 PM To: Naveed Ghori; coreboot Subject: Re: Debug builds and memory testing How u resolved memory issue? From: coreboot [mailto:coreboot-bounces@coreboot.org] On Behalf Of Naveed Ghori Sent: 31 May 2016 06:52 To: coreboot <coreboot(a)coreboot.org<mailto:coreboot@coreboot.org>> Subject: Re: [coreboot] Debug builds and memory testing To update this: There are option in the menuconfig to enable various debugging options and logs. From: Naveed Ghori Sent: Tuesday, 24 May 2016 2:04 PM To: coreboot Subject: Debug builds and memory testing Hi all, Is there a debug build of coreboot or a way to test memory very early on. My custom board goes through the romstage just fine but stops booting while trying to enumerate the buses. I am suspecting RAM might be an issue so would like to eliminate that by doing a memory test on it. -------------- POST: 0x72 Enumerating buses... Show all devs... Before device enumeration. Root Dev -------------- Thanks in advance, Naveed "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus."

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Re: [coreboot] Query regarding coreboot for new intel customized board
by Naveed Ghori 31 May '16

31 May '16

I believe the Valley Island design does not support DDR3 (only DDR-3L). You are getting output from the serial port I assume based on your previous log. Try the Gold4 FSP (debug version) to get more details on memory initialization. From: Mayuri Tendulkar [mailto:mayuri.tendulkar@aricent.com] Sent: Tuesday, 31 May 2016 12:39 PM To: Naveed Ghori; Wim Vervoorn; Zoran Stojsavljevic Cc: coreboot Subject: RE: [coreboot] Query regarding coreboot for new intel customized board Hi Naveed Thanks for your inputs. But currently my board is not booting up. Not sure what caused this. Last we flashed coreboot where I used Minnowboard Max reference, did changes for our design and patched TXE and descriptor file from reference bios of my board. Currently DDR3 is in reset, so debugging that. Regards Mayuri From: Naveed Ghori [mailto:naveed.ghori@dti.com.au] Sent: 31 May 2016 07:22 To: Wim Vervoorn <wvervoorn(a)eltan.com<mailto:wvervoorn@eltan.com>>; Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com<mailto:mayuri.tendulkar@aricent.com>>; Zoran Stojsavljevic <zoran.stojsavljevic(a)gmail.com<mailto:zoran.stojsavljevic@gmail.com>> Cc: coreboot <coreboot(a)coreboot.org<mailto:coreboot@coreboot.org>> Subject: RE: [coreboot] Query regarding coreboot for new intel customized board Mayuri, Not sure if you have gotten further but a few more suggestions: - As your board is based on Valley Island, use the Bayley bay as a base (I may be able to help more with that as that is what I used) - Initially Use FPS v4 as there is a debug version that gives some more output (especially about the RAM etc) - Use the correct memory. If you use the wrong type it will get stuck at the location you mentioned - Memory (DDR-3L, not DDR3). Best to use similar sticks to remove that as a possible obstacle - Get access the FITC tool if you do not have it. Ask your Intel rep. - For the Bayley bay you will need to modify at least the GPIO files to match your design (based on valley Island). Best of luck, Naveed Ghori From: coreboot [mailto:coreboot-bounces@coreboot.org] On Behalf Of Wim Vervoorn Sent: Thursday, 26 May 2016 4:01 PM To: Mayuri Tendulkar; Zoran Stojsavljevic Cc: coreboot Subject: Re: [coreboot] Query regarding coreboot for new intel customized board Hello Zoran, This is a nice suggestion but it doesn’t work as the system is not booting. Best Regards, Wim Vervoorn Eltan B.V. Ambachtstraat 23 5481 SM Schijndel The Netherlands T : +31-(0)73-594 46 64 E : wvervoorn(a)eltan.com<mailto:wvervoorn@eltan.com> W : http://www.eltan.com "THIS MESSAGE CONTAINS CONFIDENTIAL INFORMATION. UNLESS YOU ARE THE INTENDED RECIPIENT OF THIS MESSAGE, ANY USE OF THIS MESSAGE IS STRICTLY PROHIBITED. IF YOU HAVE RECEIVED THIS MESSAGE IN ERROR, PLEASE IMMEDIATELY NOTIFY THE SENDER BY TELEPHONE +31-(0)73-5944664 OR REPLY EMAIL, AND IMMEDIATELY DELETE THIS MESSAGE AND ALL COPIES." From: Mayuri Tendulkar [mailto:mayuri.tendulkar@aricent.com] Sent: Thursday, May 26, 2016 8:57 AM To: Zoran Stojsavljevic <zoran.stojsavljevic(a)gmail.com<mailto:zoran.stojsavljevic@gmail.com>> Cc: Wim Vervoorn <wvervoorn(a)eltan.com<mailto:wvervoorn@eltan.com>>; coreboot <coreboot(a)coreboot.org<mailto:coreboot@coreboot.org>> Subject: RE: [coreboot] Query regarding coreboot for new intel customized board Thanks. I will check on this option. I am trying putty only to check serial o/p. From: Zoran Stojsavljevic [mailto:zoran.stojsavljevic@gmail.com] Sent: 26 May 2016 12:13 To: Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com<mailto:mayuri.tendulkar@aricent.com>> Cc: Wim Vervoorn <wvervoorn(a)eltan.com<mailto:wvervoorn@eltan.com>>; coreboot <coreboot(a)coreboot.org<mailto:coreboot@coreboot.org>> Subject: Re: [coreboot] Query regarding coreboot for new intel customized board Hello Mayuri, You need to play (maybe, just a kludge) a bit with Coreboot "make menuconfig", and there with console setup: [Inline image 1] You also might want to install on your Linux distro PuTTY console (given UBUNTU apt-get and Fedora dnf commands), to set your Rx terminal correctly (at least, I know PuTTY well, always worked for me): sudo apt-get/dnf install putty Zoran On Thu, May 26, 2016 at 6:33 AM, Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com<mailto:mayuri.tendulkar@aricent.com>> wrote: Thanks Vim. Currently I am not able to get any serial prints out on my reference board. My board is based on Intel ISX board based on Baytrail-I soc E3825 given below. https://www-ssl.intel.com/content/www/us/en/embedded/design-tools/evaluatio… I have built coreboot for this, but unable to get serial prints. How I should debug this further. Regards Mayuri From: Wim Vervoorn [mailto:wvervoorn@eltan.com<mailto:wvervoorn@eltan.com>] Sent: 24 May 2016 13:26 To: Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com<mailto:mayuri.tendulkar@aricent.com>> Subject: Re: Query regarding coreboot for new intel customized board Hello Mayuri, If your rom image is the same it could be due to the lack of support for the flash device you are using. The MRC cache is preserved in flash so you need to be able to write it. For the others the numbers etc you mention are informational for the OS. They are not strictly required but the OS builds a registry of the items it retrieves from the SMBIOS. If you don’t require this you could also disable the functionality. Best Regards, Wim Vervoorn Eltan B.V. Ambachtstraat 23 5481 SM Schijndel The Netherlands T : +31-(0)73-594 46 64 E : wvervoorn(a)eltan.com<mailto:wvervoorn@eltan.com> W : http://www.eltan.com "THIS MESSAGE CONTAINS CONFIDENTIAL INFORMATION. UNLESS YOU ARE THE INTENDED RECIPIENT OF THIS MESSAGE, ANY USE OF THIS MESSAGE IS STRICTLY PROHIBITED. IF YOU HAVE RECEIVED THIS MESSAGE IN ERROR, PLEASE IMMEDIATELY NOTIFY THE SENDER BY TELEPHONE +31-(0)73-5944664<tel:%2B31-%280%2973-5944664> OR REPLY EMAIL, AND IMMEDIATELY DELETE THIS MESSAGE AND ALL COPIES." From: coreboot [mailto:coreboot-bounces@coreboot.org] On Behalf Of Mayuri Tendulkar Sent: Tuesday, May 24, 2016 7:26 AM To: coreboot <coreboot(a)coreboot.org<mailto:coreboot@coreboot.org>> Subject: [coreboot] Query regarding coreboot for new intel customized board Hi team I am working on building coreboot for one of our customized board. This is based on Intel ISX board reference design, reference can be taken as Minnowboard or BayleyBay CRB. As per documentation given under coreboot, I created folder with my board name under src/intel/mainboard/xxx and did changes required. If I tried the coreboot with these changes on minnowboard, it got stuck at FSP MRC Cache not found. But if the same code changes I copied under src/intel/mainboard/minnowmax and built, it booted fine. I would like to know what is the importance of these board names, SMBIOS table name, serial no which are defined for Minnowmax. Is there some master registry where all these are stored, and if any new entry comes, how we should add it. Regards Mayuri "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." -- coreboot mailing list: coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> https://www.coreboot.org/mailman/listinfo/coreboot "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus."

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Re: [coreboot] Debug builds and memory testing
by Naveed Ghori 31 May '16

31 May '16

I was using DDR3 instead of the low voltage DDR3L From: Mayuri Tendulkar [mailto:mayuri.tendulkar@aricent.com] Sent: Tuesday, 31 May 2016 12:40 PM To: Naveed Ghori; coreboot Subject: Re: Debug builds and memory testing How u resolved memory issue? From: coreboot [mailto:coreboot-bounces@coreboot.org] On Behalf Of Naveed Ghori Sent: 31 May 2016 06:52 To: coreboot <coreboot(a)coreboot.org<mailto:coreboot@coreboot.org>> Subject: Re: [coreboot] Debug builds and memory testing To update this: There are option in the menuconfig to enable various debugging options and logs. From: Naveed Ghori Sent: Tuesday, 24 May 2016 2:04 PM To: coreboot Subject: Debug builds and memory testing Hi all, Is there a debug build of coreboot or a way to test memory very early on. My custom board goes through the romstage just fine but stops booting while trying to enumerate the buses. I am suspecting RAM might be an issue so would like to eliminate that by doing a memory test on it. -------------- POST: 0x72 Enumerating buses... Show all devs... Before device enumeration. Root Dev -------------- Thanks in advance, Naveed "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus."

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Re: [coreboot] Debug builds and memory testing
by Naveed Ghori 31 May '16

31 May '16

To update this: There are option in the menuconfig to enable various debugging options and logs. From: Naveed Ghori Sent: Tuesday, 24 May 2016 2:04 PM To: coreboot Subject: Debug builds and memory testing Hi all, Is there a debug build of coreboot or a way to test memory very early on. My custom board goes through the romstage just fine but stops booting while trying to enumerate the buses. I am suspecting RAM might be an issue so would like to eliminate that by doing a memory test on it. -------------- POST: 0x72 Enumerating buses... Show all devs... Before device enumeration. Root Dev -------------- Thanks in advance, Naveed

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Re: [coreboot] Query regarding coreboot for new intel customized board
by Wim Vervoorn 31 May '16

31 May '16

Hello Zoran, This is a nice suggestion but it doesn’t work as the system is not booting. Best Regards, Wim Vervoorn Eltan B.V. Ambachtstraat 23 5481 SM Schijndel The Netherlands T : +31-(0)73-594 46 64 E : wvervoorn(a)eltan.com W : http://www.eltan.com "THIS MESSAGE CONTAINS CONFIDENTIAL INFORMATION. UNLESS YOU ARE THE INTENDED RECIPIENT OF THIS MESSAGE, ANY USE OF THIS MESSAGE IS STRICTLY PROHIBITED. IF YOU HAVE RECEIVED THIS MESSAGE IN ERROR, PLEASE IMMEDIATELY NOTIFY THE SENDER BY TELEPHONE +31-(0)73-5944664 OR REPLY EMAIL, AND IMMEDIATELY DELETE THIS MESSAGE AND ALL COPIES." From: Mayuri Tendulkar [mailto:mayuri.tendulkar@aricent.com] Sent: Thursday, May 26, 2016 8:57 AM To: Zoran Stojsavljevic <zoran.stojsavljevic(a)gmail.com> Cc: Wim Vervoorn <wvervoorn(a)eltan.com>; coreboot <coreboot(a)coreboot.org> Subject: RE: [coreboot] Query regarding coreboot for new intel customized board Thanks. I will check on this option. I am trying putty only to check serial o/p. From: Zoran Stojsavljevic [mailto:zoran.stojsavljevic@gmail.com] Sent: 26 May 2016 12:13 To: Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com<mailto:mayuri.tendulkar@aricent.com>> Cc: Wim Vervoorn <wvervoorn(a)eltan.com<mailto:wvervoorn@eltan.com>>; coreboot <coreboot(a)coreboot.org<mailto:coreboot@coreboot.org>> Subject: Re: [coreboot] Query regarding coreboot for new intel customized board Hello Mayuri, You need to play (maybe, just a kludge) a bit with Coreboot "make menuconfig", and there with console setup: [Inline image 1] You also might want to install on your Linux distro PuTTY console (given UBUNTU apt-get and Fedora dnf commands), to set your Rx terminal correctly (at least, I know PuTTY well, always worked for me): sudo apt-get/dnf install putty Zoran On Thu, May 26, 2016 at 6:33 AM, Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com<mailto:mayuri.tendulkar@aricent.com>> wrote: Thanks Vim. Currently I am not able to get any serial prints out on my reference board. My board is based on Intel ISX board based on Baytrail-I soc E3825 given below. https://www-ssl.intel.com/content/www/us/en/embedded/design-tools/evaluatio… I have built coreboot for this, but unable to get serial prints. How I should debug this further. Regards Mayuri From: Wim Vervoorn [mailto:wvervoorn@eltan.com<mailto:wvervoorn@eltan.com>] Sent: 24 May 2016 13:26 To: Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com<mailto:mayuri.tendulkar@aricent.com>> Subject: Re: Query regarding coreboot for new intel customized board Hello Mayuri, If your rom image is the same it could be due to the lack of support for the flash device you are using. The MRC cache is preserved in flash so you need to be able to write it. For the others the numbers etc you mention are informational for the OS. They are not strictly required but the OS builds a registry of the items it retrieves from the SMBIOS. If you don’t require this you could also disable the functionality. Best Regards, Wim Vervoorn Eltan B.V. Ambachtstraat 23 5481 SM Schijndel The Netherlands T : +31-(0)73-594 46 64 E : wvervoorn(a)eltan.com<mailto:wvervoorn@eltan.com> W : http://www.eltan.com "THIS MESSAGE CONTAINS CONFIDENTIAL INFORMATION. UNLESS YOU ARE THE INTENDED RECIPIENT OF THIS MESSAGE, ANY USE OF THIS MESSAGE IS STRICTLY PROHIBITED. IF YOU HAVE RECEIVED THIS MESSAGE IN ERROR, PLEASE IMMEDIATELY NOTIFY THE SENDER BY TELEPHONE +31-(0)73-5944664<tel:%2B31-%280%2973-5944664> OR REPLY EMAIL, AND IMMEDIATELY DELETE THIS MESSAGE AND ALL COPIES." From: coreboot [mailto:coreboot-bounces@coreboot.org] On Behalf Of Mayuri Tendulkar Sent: Tuesday, May 24, 2016 7:26 AM To: coreboot <coreboot(a)coreboot.org<mailto:coreboot@coreboot.org>> Subject: [coreboot] Query regarding coreboot for new intel customized board Hi team I am working on building coreboot for one of our customized board. This is based on Intel ISX board reference design, reference can be taken as Minnowboard or BayleyBay CRB. As per documentation given under coreboot, I created folder with my board name under src/intel/mainboard/xxx and did changes required. If I tried the coreboot with these changes on minnowboard, it got stuck at FSP MRC Cache not found. But if the same code changes I copied under src/intel/mainboard/minnowmax and built, it booted fine. I would like to know what is the importance of these board names, SMBIOS table name, serial no which are defined for Minnowmax. Is there some master registry where all these are stored, and if any new entry comes, how we should add it. Regards Mayuri "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." -- coreboot mailing list: coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> https://www.coreboot.org/mailman/listinfo/coreboot "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus."

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16GB dimm on Sandy/Ivy Bridge status
by Iru Cai 31 May '16

31 May '16

Hi, I'm tesing to see if the coreboot Sandy/Ivy MRC supports 16GB DIMMs. Here's my result. I'm using a MT16KTF2G64HZ-1G6A1[1]. My machine is Lenovo T420 with i7-3630QM. With this module inserted (I've tested 16G+0 and 16G+8G), the system can light up, but it'll then get crashed. - with GRUB2 payload, it'll crash after the payload loads - with SeaBIOS payload with proprietary VGABIOS, I can see the prompt, and can boot to a GRUB or syslinux loader on my USB stick, but when I try to boot a system, it get crashed. If I boot to Memtest86+ on my USB stick, the system will crash when memtest starts to test the memory. And another thing I can see is, the first boot can boot to payload, but the second boot will fail. I think it's caused by the MRC cache. I'm still wondering if Sandy/Ivy northbridge can support 16GB DIMMs. I'll give a more detailed EHCI debug output later. According to [2], I think the incompatibility is an MRC issue instead of hardware incompatibility. [1] https://www.micron.com/parts/modules/ddr3-sdram/mt16ktf2g64hz-1g6?pc={E1D8F… [2] http://www.intelligentmemory.com/fileadmin/download/compatibilitylist.pdf Iru.

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ASUS KFSN4-DRE Automated Test Failure [master]
by Raptor Engineering Automated Coreboot Test Stand 30 May '16

30 May '16

The ASUS KFSN4-DRE fails verification for branch master as of commit 17163755075149f36c37458af0cb5f398d2a6766 The following tests failed: VIDEO_FAILURE Commits since last successful test: 1716375 pcengines/apu1: Rename Kconfig variables for pinmux e084935 AMD/spi: Do not reset fifo after skipping the sent bytes 69088c2 sio/winbond/w83667hg-a: Add pinmux defines for UART B e4cca16 sio/winbond/common: Add function to configure pin mux 161d233 util/cbfstool: Include commonlib/helpers.h in common.h <41 commits skipped> 3a39f44 gpio: Add a function to map GPIO to ACPI path 2f6fb9f skylake: Add ACPI device name handler d9af3ce device: Add an ACPI device name and path concept to devices 3829f23 acpigen: Add function to generate ToUUID() from a string b955284 hexstrtobin: Add a library function to decode ASCII hex into binary See attached log for details This message was automatically generated from Raptor Engineering's ASUS KFSN4-DRE test stand Want to test on your own equipment? Check out https://www.raptorengineeringinc.com/content/REACTS/intro.html Raptor Engineering also offers coreboot consulting services! Please visit https://www.raptorengineeringinc.com for more information Please contact Timothy Pearson at Raptor Engineering <tpearson(a)raptorengineeringinc.com> regarding any issues stemming from this notification

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Core boot on a fujitsu laptop motherboard
by Gregor Mahnic 30 May '16

30 May '16

Hello, I am trying to set up coreboot on a fujitsu laptop with the mother board title of: DAFH5BMB6G0 I am not sure what mother board manufacturere to chose from the 65 choices. There is none for fujitsu though. Best regards

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building a payload using libpayload and SDL
by daoud yessine 30 May '16

30 May '16

Hello , I wanna building a payload using the libpayload and SDL library . Can you help me ! thx ᐧ

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coreboot May 2016