You mean this warning?
========================================================================
WARNING! You seem to be running flashrom on an unsupported laptop.
Laptops, notebooks and netbooks are difficult to support and we
recommend to use the vendor flashing utility. The embedded controller
(EC) in these machines often interacts badly with flashing.
See the manpage and http://www.flashrom.org/Laptops for details.
If flash is shared with the EC, erase is guaranteed to brick your laptop
and write may brick your laptop.
Read and probe may irritate your EC and cause fan failure, backlight
failure and sudden poweroff.
You have been warned.
========================================================================
Use `flashrom -p internal:laptop=force_I_want_a_brick` (also see the
manpage) to circumvent it, on my thinkpad x220 that just works, but as
the warning says, if the flash is shared with the EC, weird things can
and will happen, so i'd try an external programmer, stock BIOS is most
likely write-locked anyway. Make a good backup of the stock bios and
keep it safe!
Kind regards,
Jan Tatje
On Sat, May 28, 2016 at 6:13 AM, thejapanscout .
<dragonwarriorxtreme(a)gmail.com> wrote:
> I think I may have found a likely coreboot candidate-- with hardware far
> more supported than the hardware on the laptop from 2005 that I posted
> earlier.
>
> Currently, Coreboot has no Fujitsu mobos. But the specs of this Lifebook
> P1610 are close to a Thinkpad X60, except for the NIC, CPU, and
> astonishingly the mPCIe cards. Most models of the P1610 shipped with an
> Ath5k Wi-Fi mPCIe card, which has free software drivers, along with the rest
> of the non-ME hardware, including the fingerprint reader, making it
> essentially free-software compatible on the software side.
>
> It also has a touch-screen, making it nifty for artists and workers that
> want a tablet.
>
> Before you ask, GOOD NEWS! Most of the hardware, as seen in my lspci -tvnn
> output, has completely added support in coreboot. It also runs off a
> GM45-based chipset, which can have it's ME deblobbed, making it viable for
> GNU libreboot.
>
> -[0000:00]-+-00.0 Intel Corporation Mobile 945GM/PM/GMS, 943/940GML and
> 945GT Express Memory Controller Hub [8086:27a0]
> +-02.0 Intel Corporation Mobile 945GM/GMS, 943/940GML Express
> Integrated Graphics Controller [8086:27a2]
> +-02.1 Intel Corporation Mobile 945GM/GMS/GME, 943/940GML
> Express Integrated Graphics Controller [8086:27a6]
> +-1b.0 Intel Corporation NM10/ICH7 Family High Definition Audio
> Controller [8086:27d8]
> +-1c.0-[02]----00.0 Marvell Technology Group Ltd. 88E8055 PCI-E
> Gigabit Ethernet Controller [11ab:4363]
> +-1c.2-[05]----00.0 Qualcomm Atheros AR242x / AR542x Wireless
> Network Adapter (PCI-Express) [168c:001c]
> +-1d.0 Intel Corporation NM10/ICH7 Family USB UHCI Controller #1
> [8086:27c8]
> +-1d.1 Intel Corporation NM10/ICH7 Family USB UHCI Controller #2
> [8086:27c9]
> +-1d.2 Intel Corporation NM10/ICH7 Family USB UHCI Controller #3
> [8086:27ca]
> +-1d.3 Intel Corporation NM10/ICH7 Family USB UHCI Controller #4
> [8086:27cb]
> +-1d.7 Intel Corporation NM10/ICH7 Family USB2 EHCI Controller
> [8086:27cc]
> +-1e.0-[08-0c]--+-03.0 Ricoh Co Ltd RL5c476 II [1180:0476]
> | \-03.1 Ricoh Co Ltd R5C822 SD/SDIO/MMC/MS/MSPro
> Host Adapter [1180:0822]
> +-1f.0 Intel Corporation 82801GBM (ICH7-M) LPC Interface Bridge
> [8086:27b9]
> +-1f.1 Intel Corporation 82801G (ICH7 Family) IDE Controller
> [8086:27df]
> \-1f.3 Intel Corporation NM10/ICH7 Family SMBus Controller
> [8086:27da]
>
> SN and UUID:
> R7108162
> 13F0737D-AD13-11DB-8B14-001742268EEB
>
> Baseboard SN:
> FJNB1C5
>
> superiotool -dV log:
> Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e...
> Found SMSC LPC47N217 (id=0x7a, rev=0x00) at 0x2e
> No dump available for this Super I/O
> Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e...
> Found SMSC FDC37N972 (id=0x0b, rev=0x00) at 0x4e
> Register dump:
> idx 02 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f
> val 00 0b 00 00 00 00 00 4e 00 00 00 00 00 00 00 00 00
> def 00 0b 00 00 00 04 04 NA NA 00 00 00 00 00 00 00 00
> LDN 0x00 (Floppy)
> idx 30 60 61 70 74 f0 f1 f2 f3 f4 f5
> val 01 fd 00 00 00 00 d1 15 0b 00 10
> def 00 03 f0 06 02 0e 00 ff RR 00 00
> LDN 0x01 (Power management (PM1))
> idx 30 60 61
> val 01 fd 00
> def 00 00 00
> LDN 0x03 (Parallel port)
> idx 30 60 61 70 74 f0 f1
> val 01 fd 00 00 00 00 d1
> def 00 00 00 00 04 3c 00
> LDN 0x04 (COM1)
> idx 30 60 61 70 f0
> val 01 fd 00 00 00
> def 00 00 00 00 00
> LDN 0x05 (COM2)
> idx 30 60 61 62 63 70 74 f0 f1 f2 f7 f8
> val 01 fd 00 00 00 00 00 00 d1 15 00 00
> def 00 00 00 00 00 00 04 00 02 03 00 00
> LDN 0x06 (Real-time clock (RTC))
> idx 30 60 61 62 63 70 f0 f1
> val 01 fd 00 00 00 00 00 d1
> def 00 00 70 00 74 00 00 NA
> LDN 0x07 (Keyboard)
> idx 30 60 61 70 72 f0
> val 01 fd 00 00 00 00
> def 00 00 00 00 00 00
> LDN 0x08 (Embedded controller (EC))
> idx 30 60 61
> val 01 fd 00
> def 00 00 62
> LDN 0x09 (Mailbox)
> idx 30 60 61
> val 01 fd 00
> def 00 00 00
>
> flashrom is once again, detecting an unsupported laptop though. Is there an
> option to bypass detection in flashrom?
>
> --
> coreboot mailing list: coreboot(a)coreboot.org
> https://www.coreboot.org/mailman/listinfo/coreboot
I think I may have found a likely coreboot candidate-- with hardware far
more supported than the hardware on the laptop from 2005 that I posted
earlier.
Currently, Coreboot has no Fujitsu mobos. But the specs of this Lifebook
P1610 are close to a Thinkpad X60, except for the NIC, CPU, and
astonishingly the mPCIe cards. Most models of the P1610 shipped with an
Ath5k Wi-Fi mPCIe card, which has free software drivers, along with the
rest of the non-ME hardware, including the fingerprint reader, making it
essentially free-software compatible on the software side.
It also has a touch-screen, making it nifty for artists and workers that
want a tablet.
Before you ask, GOOD NEWS! Most of the hardware, as seen in my lspci -tvnn
output, has completely added support in coreboot. It also runs off a
GM45-based chipset, which can have it's ME deblobbed, making it viable for
GNU libreboot.
-[0000:00]-+-00.0 Intel Corporation Mobile 945GM/PM/GMS, 943/940GML and
945GT Express Memory Controller Hub [8086:27a0]
+-02.0 Intel Corporation Mobile 945GM/GMS, 943/940GML Express
Integrated Graphics Controller [8086:27a2]
+-02.1 Intel Corporation Mobile 945GM/GMS/GME, 943/940GML
Express Integrated Graphics Controller [8086:27a6]
+-1b.0 Intel Corporation NM10/ICH7 Family High Definition Audio
Controller [8086:27d8]
+-1c.0-[02]----00.0 Marvell Technology Group Ltd. 88E8055 PCI-E
Gigabit Ethernet Controller [11ab:4363]
+-1c.2-[05]----00.0 Qualcomm Atheros AR242x / AR542x Wireless
Network Adapter (PCI-Express) [168c:001c]
+-1d.0 Intel Corporation NM10/ICH7 Family USB UHCI Controller
#1 [8086:27c8]
+-1d.1 Intel Corporation NM10/ICH7 Family USB UHCI Controller
#2 [8086:27c9]
+-1d.2 Intel Corporation NM10/ICH7 Family USB UHCI Controller
#3 [8086:27ca]
+-1d.3 Intel Corporation NM10/ICH7 Family USB UHCI Controller
#4 [8086:27cb]
+-1d.7 Intel Corporation NM10/ICH7 Family USB2 EHCI Controller
[8086:27cc]
+-1e.0-[08-0c]--+-03.0 Ricoh Co Ltd RL5c476 II [1180:0476]
| \-03.1 Ricoh Co Ltd R5C822 SD/SDIO/MMC/MS/MSPro
Host Adapter [1180:0822]
+-1f.0 Intel Corporation 82801GBM (ICH7-M) LPC Interface Bridge
[8086:27b9]
+-1f.1 Intel Corporation 82801G (ICH7 Family) IDE Controller
[8086:27df]
\-1f.3 Intel Corporation NM10/ICH7 Family SMBus Controller
[8086:27da]
SN and UUID:
R7108162
13F0737D-AD13-11DB-8B14-001742268EEB
Baseboard SN:
FJNB1C5
superiotool -dV log:
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e...
Found SMSC LPC47N217 (id=0x7a, rev=0x00) at 0x2e
No dump available for this Super I/O
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e...
Found SMSC FDC37N972 (id=0x0b, rev=0x00) at 0x4e
Register dump:
idx 02 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f
val 00 0b 00 00 00 00 00 4e 00 00 00 00 00 00 00 00 00
def 00 0b 00 00 00 04 04 NA NA 00 00 00 00 00 00 00 00
LDN 0x00 (Floppy)
idx 30 60 61 70 74 f0 f1 f2 f3 f4 f5
val 01 fd 00 00 00 00 d1 15 0b 00 10
def 00 03 f0 06 02 0e 00 ff RR 00 00
LDN 0x01 (Power management (PM1))
idx 30 60 61
val 01 fd 00
def 00 00 00
LDN 0x03 (Parallel port)
idx 30 60 61 70 74 f0 f1
val 01 fd 00 00 00 00 d1
def 00 00 00 00 04 3c 00
LDN 0x04 (COM1)
idx 30 60 61 70 f0
val 01 fd 00 00 00
def 00 00 00 00 00
LDN 0x05 (COM2)
idx 30 60 61 62 63 70 74 f0 f1 f2 f7 f8
val 01 fd 00 00 00 00 00 00 d1 15 00 00
def 00 00 00 00 00 00 04 00 02 03 00 00
LDN 0x06 (Real-time clock (RTC))
idx 30 60 61 62 63 70 f0 f1
val 01 fd 00 00 00 00 00 d1
def 00 00 70 00 74 00 00 NA
LDN 0x07 (Keyboard)
idx 30 60 61 70 72 f0
val 01 fd 00 00 00 00
def 00 00 00 00 00 00
LDN 0x08 (Embedded controller (EC))
idx 30 60 61
val 01 fd 00
def 00 00 62
LDN 0x09 (Mailbox)
idx 30 60 61
val 01 fd 00
def 00 00 00
flashrom is once again, detecting an unsupported laptop though. Is there an
option to bypass detection in flashrom?
If you are still interested try this commit:
https://review.coreboot.org/#/c/14989/
It should work. The instructions on the wiki are not needed now, just
make the payload.
On 27/05/16 08:48, David Griffith wrote:
>
> Has anyone here been able to produce a Coreboot image that contains
> tint? It won't compile without a lot of tinkering and uses a really
> old version.
>
--
Sent from my Android device with K-9 Mail. Please excuse my brevity.
Has anyone here been able to produce a Coreboot image that contains tint?
It won't compile without a lot of tinkering and uses a really old version.
--
David Griffith
dave(a)661.org
A: Because it fouls the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing in e-mail?
Hi,
I'm new to coreboot. I would like to have it working on the following
hardware:
* Fujitsu D3231 (Q87)
* Intel DQ87PG (Q87)
* Intel DQ67OW (Q67)
* Intel DQ45CB (Q45)
Focusing on the first 3, which are all core-i systems, sandybridge and
haswell. I *believe* that coreboot would already support the CPU and
Chipsets.
(If that is correct?)
However, the SuperIO I know is not supported. They are respectively:
* SMSC SCH5636, devid '0xc7', kdriver 'sch5636'
* NCT6683D-T, devid '0xc730', kdriver 'nct6683'
* W83677HG-I, devid '0xb470', kdriver 'w83627ehf'
* WPCD377I, devid '0xf1', kdriver 'not-a-sensor'?
I know that these chips are supported in the kernel/lm_sensors. So
perhaps all the info I need to add the support into coreboot is already
available?
However, I'm not entirely sure how best to go about this. I don't
really understand what needs to be achieved or how.
I need some guidance to figure this out, is there an good example I
could follow where by a driver from kernel/lm_sensors has been ported
into coreboot?
If I port the superIO chip successfully, is the next stage to simply
create a board which combines the 3 components CPU,Chipset and SIO? or
am I underestimating this?
Could anyone possibly comment on how much work this will be? The
SuperIO support files don't look that indepth, however if that were
true, and if all the info required is already in the kernel - I wonder
why coreboot doesn't already implement the same list in the kernel.
Thanks,
Andy
--------------------------------------------------------------------------------------------------
This email and any attachments are confidential and are for the use of the
addressee only. If you are not the addressee, you must not use or disclose the
contents to any other person. Please immediately notify the sender and
delete the email. Statements and opinions expressed here may not
represent those of the company. Email correspondence is monitored by
the company. This information may be subject to export control
regulation. You are obliged to comply with such regulations.
Renishaw plc (company number 1106260) and Wotton Travel Limited (company
number 01973158) are companies registered in England and Wales with a registered office
at New Mills, Wotton-under-Edge, Gloucestershire, GL12 8JR,
United Kingdom, Telephone +44 1453 524524.
--------------------------------------------------------------------------------------------------
Thanks. I will check on this option.
I am trying putty only to check serial o/p.
From: Zoran Stojsavljevic [mailto:zoran.stojsavljevic@gmail.com]
Sent: 26 May 2016 12:13
To: Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com>
Cc: Wim Vervoorn <wvervoorn(a)eltan.com>; coreboot <coreboot(a)coreboot.org>
Subject: Re: [coreboot] Query regarding coreboot for new intel customized board
Hello Mayuri,
You need to play (maybe, just a kludge) a bit with Coreboot "make menuconfig", and there with console setup:
[Inline image 1]
You also might want to install on your Linux distro PuTTY console (given UBUNTU apt-get and Fedora dnf commands), to set your Rx terminal correctly (at least, I know PuTTY well, always worked for me):
sudo apt-get/dnf install putty
Zoran
On Thu, May 26, 2016 at 6:33 AM, Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com<mailto:mayuri.tendulkar@aricent.com>> wrote:
Thanks Vim.
Currently I am not able to get any serial prints out on my reference board.
My board is based on Intel ISX board based on Baytrail-I soc E3825 given below.
https://www-ssl.intel.com/content/www/us/en/embedded/design-tools/evaluatio…
I have built coreboot for this, but unable to get serial prints.
How I should debug this further.
Regards
Mayuri
From: Wim Vervoorn [mailto:wvervoorn@eltan.com<mailto:wvervoorn@eltan.com>]
Sent: 24 May 2016 13:26
To: Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com<mailto:mayuri.tendulkar@aricent.com>>
Subject: Re: Query regarding coreboot for new intel customized board
Hello Mayuri,
If your rom image is the same it could be due to the lack of support for the flash device you are using. The MRC cache is preserved in flash so you need to be able to write it.
For the others the numbers etc you mention are informational for the OS. They are not strictly required but the OS builds a registry of the items it retrieves from the SMBIOS. If you don’t require this you could also disable the functionality.
Best Regards,
Wim Vervoorn
Eltan B.V.
Ambachtstraat 23
5481 SM Schijndel
The Netherlands
T : +31-(0)73-594 46 64
E : wvervoorn(a)eltan.com<mailto:wvervoorn@eltan.com>
W : http://www.eltan.com
"THIS MESSAGE CONTAINS CONFIDENTIAL INFORMATION. UNLESS YOU ARE THE INTENDED RECIPIENT OF THIS MESSAGE, ANY USE OF THIS MESSAGE IS STRICTLY PROHIBITED. IF YOU HAVE RECEIVED THIS MESSAGE IN ERROR, PLEASE IMMEDIATELY NOTIFY THE SENDER BY TELEPHONE +31-(0)73-5944664<tel:%2B31-%280%2973-5944664> OR REPLY EMAIL, AND IMMEDIATELY DELETE THIS MESSAGE AND ALL COPIES."
From: coreboot [mailto:coreboot-bounces@coreboot.org] On Behalf Of Mayuri Tendulkar
Sent: Tuesday, May 24, 2016 7:26 AM
To: coreboot <coreboot(a)coreboot.org<mailto:coreboot@coreboot.org>>
Subject: [coreboot] Query regarding coreboot for new intel customized board
Hi team
I am working on building coreboot for one of our customized board. This is based on Intel ISX board reference design, reference can be taken as Minnowboard or BayleyBay CRB.
As per documentation given under coreboot, I created folder with my board name under src/intel/mainboard/xxx and did changes required.
If I tried the coreboot with these changes on minnowboard, it got stuck at FSP MRC Cache not found.
But if the same code changes I copied under src/intel/mainboard/minnowmax and built, it booted fine.
I would like to know what is the importance of these board names, SMBIOS table name, serial no which are defined for Minnowmax.
Is there some master registry where all these are stored, and if any new entry comes, how we should add it.
Regards
Mayuri
"DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus."
"DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus."
--
coreboot mailing list: coreboot(a)coreboot.org<mailto:coreboot@coreboot.org>
https://www.coreboot.org/mailman/listinfo/coreboot
"DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus."
Hello Mayuri,
You need to play (maybe, just a kludge) a bit with Coreboot "make
menuconfig", and there with console setup:
[image: Inline image 1]
You also might want to install on your Linux distro PuTTY console (given
UBUNTU apt-get and Fedora dnf commands), to set your Rx terminal correctly
(at least, I know PuTTY well, always worked for me):
sudo apt-get/dnf install putty
Zoran
On Thu, May 26, 2016 at 6:33 AM, Mayuri Tendulkar <
mayuri.tendulkar(a)aricent.com> wrote:
> Thanks Vim.
>
>
>
> Currently I am not able to get any serial prints out on my reference board.
>
>
>
> My board is based on Intel ISX board based on Baytrail-I soc E3825 given
> below.
>
>
>
>
> https://www-ssl.intel.com/content/www/us/en/embedded/design-tools/evaluatio…
>
>
>
> I have built coreboot for this, but unable to get serial prints.
>
>
>
> How I should debug this further.
>
>
>
> Regards
>
> Mayuri
>
>
>
> *From:* Wim Vervoorn [mailto:wvervoorn@eltan.com]
> *Sent:* 24 May 2016 13:26
> *To:* Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com>
> *Subject:* Re: Query regarding coreboot for new intel customized board
>
>
>
> Hello Mayuri,
>
>
>
> If your rom image is the same it could be due to the lack of support for
> the flash device you are using. The MRC cache is preserved in flash so you
> need to be able to write it.
>
>
>
> For the others the numbers etc you mention are informational for the OS.
> They are not strictly required but the OS builds a registry of the items it
> retrieves from the SMBIOS. If you don’t require this you could also disable
> the functionality.
>
>
>
>
>
> Best Regards,
>
> Wim Vervoorn
>
>
>
> Eltan B.V.
>
> Ambachtstraat 23
>
> 5481 SM Schijndel
>
> The Netherlands
>
>
>
> T : +31-(0)73-594 46 64
>
> E : wvervoorn(a)eltan.com
>
> W : http://www.eltan.com
>
> "THIS MESSAGE CONTAINS CONFIDENTIAL INFORMATION. UNLESS YOU ARE THE
> INTENDED RECIPIENT OF THIS MESSAGE, ANY USE OF THIS MESSAGE IS STRICTLY
> PROHIBITED. IF YOU HAVE RECEIVED THIS MESSAGE IN ERROR, PLEASE IMMEDIATELY
> NOTIFY THE SENDER BY TELEPHONE +31-(0)73-5944664 OR REPLY EMAIL, AND
> IMMEDIATELY DELETE THIS MESSAGE AND ALL COPIES."
>
>
>
>
>
>
>
>
>
>
>
> *From:* coreboot [mailto:coreboot-bounces@coreboot.org
> <coreboot-bounces(a)coreboot.org>] *On Behalf Of *Mayuri Tendulkar
> *Sent:* Tuesday, May 24, 2016 7:26 AM
> *To:* coreboot <coreboot(a)coreboot.org>
> *Subject:* [coreboot] Query regarding coreboot for new intel customized
> board
>
>
>
> Hi team
>
>
>
> I am working on building coreboot for one of our customized board. This is
> based on Intel ISX board reference design, reference can be taken as
> Minnowboard or BayleyBay CRB.
>
>
>
> As per documentation given under coreboot, I created folder with my board
> name under src/intel/mainboard/xxx and did changes required.
>
>
>
> If I tried the coreboot with these changes on minnowboard, it got stuck at
> FSP MRC Cache not found.
>
>
>
> But if the same code changes I copied under src/intel/mainboard/minnowmax
> and built, it booted fine.
>
>
>
> I would like to know what is the importance of these board names, SMBIOS
> table name, serial no which are defined for Minnowmax.
>
>
>
> Is there some master registry where all these are stored, and if any new
> entry comes, how we should add it.
>
>
>
> Regards
>
> Mayuri
>
>
>
>
>
> "DISCLAIMER: This message is proprietary to Aricent and is intended solely
> for the use of the individual to whom it is addressed. It may contain
> privileged or confidential information and should not be circulated or used
> for any purpose other than for what it is intended. If you have received
> this message in error, please notify the originator immediately. If you are
> not the intended recipient, you are notified that you are strictly
> prohibited from using, copying, altering, or disclosing the contents of
> this message. Aricent accepts no responsibility for loss or damage arising
> from the use of the information transmitted by this email including damage
> from virus."
> "DISCLAIMER: This message is proprietary to Aricent and is intended solely
> for the use of the individual to whom it is addressed. It may contain
> privileged or confidential information and should not be circulated or used
> for any purpose other than for what it is intended. If you have received
> this message in error, please notify the originator immediately. If you are
> not the intended recipient, you are notified that you are strictly
> prohibited from using, copying, altering, or disclosing the contents of
> this message. Aricent accepts no responsibility for loss or damage arising
> from the use of the information transmitted by this email including damage
> from virus."
>
> --
> coreboot mailing list: coreboot(a)coreboot.org
> https://www.coreboot.org/mailman/listinfo/coreboot
>
Dear Sir.
My platform is intel rangely.
I'm must contol the GPIO pins, But i'm can't found the example code on
coreboot source tree.
Could you show me the example code to control GPIO?
Thank you.
That looks a lot like the Valley Island design.
I was able to get serial output by overwriting coreboot (last 2MB of the 8MB bios chip) on the bios that comes with it.
However as you will see in the history of emails still get stuck during the boot process.
Hope the above helps you get further.
From: coreboot [mailto:coreboot-bounces@coreboot.org] On Behalf Of Mayuri Tendulkar
Sent: Thursday, 26 May 2016 12:33 PM
To: Wim Vervoorn; coreboot
Subject: Re: [coreboot] Query regarding coreboot for new intel customized board
Thanks Vim.
Currently I am not able to get any serial prints out on my reference board.
My board is based on Intel ISX board based on Baytrail-I soc E3825 given below.
https://www-ssl.intel.com/content/www/us/en/embedded/design-tools/evaluatio…
I have built coreboot for this, but unable to get serial prints.
How I should debug this further.
Regards
Mayuri
From: Wim Vervoorn [mailto:wvervoorn@eltan.com]
Sent: 24 May 2016 13:26
To: Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com<mailto:mayuri.tendulkar@aricent.com>>
Subject: Re: Query regarding coreboot for new intel customized board
Hello Mayuri,
If your rom image is the same it could be due to the lack of support for the flash device you are using. The MRC cache is preserved in flash so you need to be able to write it.
For the others the numbers etc you mention are informational for the OS. They are not strictly required but the OS builds a registry of the items it retrieves from the SMBIOS. If you don't require this you could also disable the functionality.
Best Regards,
Wim Vervoorn
Eltan B.V.
Ambachtstraat 23
5481 SM Schijndel
The Netherlands
T : +31-(0)73-594 46 64
E : wvervoorn(a)eltan.com<mailto:wvervoorn@eltan.com>
W : http://www.eltan.com
"THIS MESSAGE CONTAINS CONFIDENTIAL INFORMATION. UNLESS YOU ARE THE INTENDED RECIPIENT OF THIS MESSAGE, ANY USE OF THIS MESSAGE IS STRICTLY PROHIBITED. IF YOU HAVE RECEIVED THIS MESSAGE IN ERROR, PLEASE IMMEDIATELY NOTIFY THE SENDER BY TELEPHONE +31-(0)73-5944664 OR REPLY EMAIL, AND IMMEDIATELY DELETE THIS MESSAGE AND ALL COPIES."
From: coreboot [mailto:coreboot-bounces@coreboot.org] On Behalf Of Mayuri Tendulkar
Sent: Tuesday, May 24, 2016 7:26 AM
To: coreboot <coreboot(a)coreboot.org<mailto:coreboot@coreboot.org>>
Subject: [coreboot] Query regarding coreboot for new intel customized board
Hi team
I am working on building coreboot for one of our customized board. This is based on Intel ISX board reference design, reference can be taken as Minnowboard or BayleyBay CRB.
As per documentation given under coreboot, I created folder with my board name under src/intel/mainboard/xxx and did changes required.
If I tried the coreboot with these changes on minnowboard, it got stuck at FSP MRC Cache not found.
But if the same code changes I copied under src/intel/mainboard/minnowmax and built, it booted fine.
I would like to know what is the importance of these board names, SMBIOS table name, serial no which are defined for Minnowmax.
Is there some master registry where all these are stored, and if any new entry comes, how we should add it.
Regards
Mayuri
"DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus."
"DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus."
Thanks Vim.
Currently I am not able to get any serial prints out on my reference board.
My board is based on Intel ISX board based on Baytrail-I soc E3825 given below.
https://www-ssl.intel.com/content/www/us/en/embedded/design-tools/evaluatio…
I have built coreboot for this, but unable to get serial prints.
How I should debug this further.
Regards
Mayuri
From: Wim Vervoorn [mailto:wvervoorn@eltan.com]
Sent: 24 May 2016 13:26
To: Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com>
Subject: Re: Query regarding coreboot for new intel customized board
Hello Mayuri,
If your rom image is the same it could be due to the lack of support for the flash device you are using. The MRC cache is preserved in flash so you need to be able to write it.
For the others the numbers etc you mention are informational for the OS. They are not strictly required but the OS builds a registry of the items it retrieves from the SMBIOS. If you don't require this you could also disable the functionality.
Best Regards,
Wim Vervoorn
Eltan B.V.
Ambachtstraat 23
5481 SM Schijndel
The Netherlands
T : +31-(0)73-594 46 64
E : wvervoorn(a)eltan.com<mailto:wvervoorn@eltan.com>
W : http://www.eltan.com
"THIS MESSAGE CONTAINS CONFIDENTIAL INFORMATION. UNLESS YOU ARE THE INTENDED RECIPIENT OF THIS MESSAGE, ANY USE OF THIS MESSAGE IS STRICTLY PROHIBITED. IF YOU HAVE RECEIVED THIS MESSAGE IN ERROR, PLEASE IMMEDIATELY NOTIFY THE SENDER BY TELEPHONE +31-(0)73-5944664 OR REPLY EMAIL, AND IMMEDIATELY DELETE THIS MESSAGE AND ALL COPIES."
From: coreboot [mailto:coreboot-bounces@coreboot.org] On Behalf Of Mayuri Tendulkar
Sent: Tuesday, May 24, 2016 7:26 AM
To: coreboot <coreboot(a)coreboot.org<mailto:coreboot@coreboot.org>>
Subject: [coreboot] Query regarding coreboot for new intel customized board
Hi team
I am working on building coreboot for one of our customized board. This is based on Intel ISX board reference design, reference can be taken as Minnowboard or BayleyBay CRB.
As per documentation given under coreboot, I created folder with my board name under src/intel/mainboard/xxx and did changes required.
If I tried the coreboot with these changes on minnowboard, it got stuck at FSP MRC Cache not found.
But if the same code changes I copied under src/intel/mainboard/minnowmax and built, it booted fine.
I would like to know what is the importance of these board names, SMBIOS table name, serial no which are defined for Minnowmax.
Is there some master registry where all these are stored, and if any new entry comes, how we should add it.
Regards
Mayuri
"DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus."
"DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus."
