coreboot May 2016

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Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay
by Mayuri Tendulkar 20 May '16

20 May '16

Hi Zoran Currently we are using FSP 3. But it works fine with seabios payload. Only when I include UEFI, I am getting this issue. So I am not sure if this is related to FSP3 or 4. My query is there any additional configurations required in UEFI Payload to make it work for Minnowboard max. I see difference in addresses for UEFI and Seabios payload. Not sure where are they set. Seabios payload (working) CBFS provider active. CBFS @ 500000 size 2ff9c0 CBFS: Locating 'fallback/payload' CBFS: Found @ offset 76b40 size f782 'fallback/payload' located at offset: 576b78 size: f782 Loading segment from rom address 0xffd76b78 code (compression=1) New segment dstaddr 0xe2780 memsize 0x1d880 srcaddr 0xffd76bb0 filesize 0xf74a Loading segment from rom address 0xffd76b94 Entry Point 0x000ff06e Payload being loaded below 1MiB without region being marked as RAM usable. Bounce Buffer at 7ac50000, 451744 bytes Loading Segment: addr: 0x00000000000e2780 memsz: 0x000000000001d880 filesz: 0x000000000000f74a lb: [0x0000000000100000, 0x0000000000137250) Post relocation: addr: 0x00000000000e2780 memsz: 0x000000000001d880 filesz: 0x000000000000f74a using LZMA [ 0x000e2780, 00100000, 0x00100000) <- ffd76bb0 dest 000e2780, end 00100000, bouncebuffer 7ac50000 Loaded segments BS: BS_PAYLOAD_LOAD times (us): entry 0 run 130526 exit 0 FspNotify(EnumInitPhaseReadyToBoot) fsp_header_ptr: fffc0094 FSP Header Version: 1 FSP Revision: 3.3 Returned from FspNotify(EnumInitPhaseReadyToBoot) POST: 0x7b Jumping to boot code at 000ff06e(7acbf000) POST: 0xf8 CPU0: stack: 0012e000 - 0012f000, lowest used address 0012eb10, stack used: 1264 bytes entry = 0x000ff06e lb_start = 0x00100000 lb_size = 0x00037250 buffer = 0x7ac50000 SeaBIOS (version rel-1.9.0-127-gc8e105a) UEFI Payload logs (not working) CBFS provider active. CBFS @ 500000 size 2ff9c0 CBFS: Locating 'fallback/payload' CBFS: Found @ offset 56ec0 size 90b92 'fallback/payload' located at offset: 556ef8 size: 90b92 Loading segment from rom address 0xffd56ef8 code (compression=1) New segment dstaddr 0x800000 memsize 0x410000 srcaddr 0xffd56f30 filesize 0x90b5a Loading segment from rom address 0xffd56f14 Entry Point 0x008002c0 Bounce Buffer at 7ac34000, 437408 bytes Loading Segment: addr: 0x0000000000800000 memsz: 0x0000000000410000 filesz: 0x0000000000090b5a lb: [0x0000000000100000, 0x0000000000135650) Post relocation: addr: 0x0000000000800000 memsz: 0x0000000000410000 filesz: 0x0000000000090b5a using LZMA [ 0x00800000, 00c10000, 0x00c10000) <- ffd56f30 dest 00800000, end 00c10000, bouncebuffer 7ac34000 Loaded segments BS: BS_PAYLOAD_LOAD times (us): entry 0 run 507070 exit 0 FspNotify(EnumInitPhaseReadyToBoot) fsp_header_ptr: fffc0094 FSP Header Version: 1 FSP Revision: 3.3 Returned from FspNotify(EnumInitPhaseReadyToBoot) POST: 0x7b Jumping to boot code at 008002c0(7ac9f000) POST: 0xf8 CPU0: stack: 0012c000 - 0012d000, lowest used address 0012cb10, stack used: 1264 bytes entry = 0x008002c0 lb_start = 0x00100000 lb_size = 0x00035650 buffer = 0x7ac34000 From: Zoran Stojsavljevic [mailto:zoran.stojsavljevic@gmail.com] Sent: 20 May 2016 10:44 To: Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com>; coreboot <coreboot(a)coreboot.org> Subject: Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay Hello Mayuri, If I am not mistaken (I often mix BYT Coreboot @ threads in my head), you are using BYT FSP Version 3. > fsp_header_ptr: fffc0094 <== correct > FSP Header Version: 1 > FSP Revision: 3.3 <== please, use Version 4 Please, try to use the latest public BYT FSP Version 4 posted at: www.intel.com/fsp<http://www.intel.com/fsp> BAYTRAIL_FSP_GOLD_004_22-MAY-2015.fd BAYTRAIL_FSP_GOLD_004_22-MAY-2015_DEBUG.fd Don't remember deltas between V3 and V4, I thing something was wrong in V3 with MTRRs' setup, if I do not mix data in my head. INTEL also has Version 5 for a quite some time, but this one for some reasons never got publicly released. Please, report if this solved your problems. Zoran On Wed, May 18, 2016 at 6:56 AM, Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com<mailto:mayuri.tendulkar@aricent.com>> wrote: Hi While booting my Minnomboard with coreboot and UEFI, it hangs at below point while loading the payload. I followed the procedure to download latest EDK2 tree and built UEFIPAYLOAD.fd and copied it to coreboot/payloads/external/tianocore folder and gave this path in make menuconfig. Has anybody come across this? BS: BS_PAYLOAD_LOAD times (us): entry 0 run 507070 exit 0 FspNotify(EnumInitPhaseReadyToBoot) fsp_header_ptr: fffc0094 FSP Header Version: 1 FSP Revision: 3.3 Returned from FspNotify(EnumInitPhaseReadyToBoot) POST: 0x7b Jumping to boot code at 008002c0(7ac9f000) POST: 0xf8 CPU0: stack: 0012c000 - 0012d000, lowest used address 0012cb10, stack used: 1264 bytes entry = 0x008002c0 lb_start = 0x00100000 lb_size = 0x00035650 buffer = 0x7ac34000 Regards Mayuri From: Mayuri Tendulkar Sent: 17 May 2016 14:13 To: 'Zoran Stojsavljevic' <zoran.stojsavljevic(a)gmail.com<mailto:zoran.stojsavljevic@gmail.com>>; coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> Subject: RE: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay Hi Zoran and Martin Today I was able to build UEFIPAYLOAD separately. I included .fd file while building coreboot.rom. But while booting, getting some errors , so debugging those. Need to check what more customizations to be done in UEFI for Minnowmax. Has anybody tried it? Regards Mayuri From: Zoran Stojsavljevic [mailto:zoran.stojsavljevic@gmail.com] Sent: 16 May 2016 21:04 To: Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com<mailto:mayuri.tendulkar@aricent.com>>; coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> Subject: Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay OK, Mayuri, You brought an interesting point. And this point is to be not only investigated by you, rather also by me and, perhaps, Coreboot community. Since here, in Bayern/Deutschland is Holiday Day, I went to buy a beer in Munchen HBf, and while walking there I was thinking about your use case. Thinking deeper. I know that you are using some INTEL CPU/SoC (do not remember which one, if you said one). But, while recapping how BIOS looks like, I did notice that SEC and PEI phases have nothing to do with UEFI EDK2. EDK 2 comes to play in DXE phase, where EDK2 actually takes place/overtakes control... It says to me one major thing I did not notice while ago: that ARM SoCs are also eligible to run on UEFI compliant OSes, namely WIN 8.1+ (including WIN 10 and WIN 10 Athens/RT WIN 10). Which makes very interesting IOT case namely for ARM, allowing it also to compete in WIN space. Interestingly enough, this idea did not come to my mind till few hours ago... I guess, Vincent (Zimmer) already thought about that. ;-) _______ Martin (Roth) just replied, to solve this immediate mystery. probably for the beginning only for INTEL SoCs, but, I really hope, ARM will also integrate in this concept seamlessly! :-) Zoran _______ On Mon, May 16, 2016 at 2:29 PM, Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com<mailto:mayuri.tendulkar@aricent.com>> wrote: Hi Zoran I have checked that site and downloaded EDK2 code. I am trying to build it on Linux but facing some issues. But if I generate payload file separately, I need to integrate it in coreboot separately. So I am checking if there is way to build the payload in coreboot itself. Regards Mayuri From: Zoran Stojsavljevic [mailto:zoran.stojsavljevic@gmail.com<mailto:zoran.stojsavljevic@gmail.com>] Sent: 16 May 2016 17:57 To: Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com<mailto:mayuri.tendulkar@aricent.com>> Cc: coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> Subject: Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay Hello Mayuri, You should check payload called: Tiano Core (true UEFI payload). Zoran On Mon, May 16, 2016 at 2:12 PM, Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com<mailto:mayuri.tendulkar@aricent.com>> wrote: Hi Is there any mechanism to build UEFI payload directly in coreboot similar like seabios? Regards Mayuri "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." -- coreboot mailing list: coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> https://www.coreboot.org/mailman/listinfo/coreboot "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus."

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Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay
by Zoran Stojsavljevic 20 May '16

20 May '16

Hello Mayuri, If I am not mistaken (I often mix BYT Coreboot @ threads in my head), you are using BYT FSP Version 3. > fsp_header_ptr: fffc0094 <== correct > FSP Header Version: 1 > FSP Revision: 3.3 <== please, use Version 4 Please, try to use the latest public BYT FSP Version 4 posted at: www.intel.com/fsp *BAYTRAIL_FSP_GOLD_004_22-MAY-2015.fd* *BAYTRAIL_FSP_GOLD_004_22-MAY-2015_DEBUG.fd* Don't remember deltas between V3 and V4, I thing something was wrong in V3 with MTRRs' setup, if I do not mix data in my head. INTEL also has Version 5 for a quite some time, but this one for some reasons never got publicly released. Please, report if this solved your problems. Zoran On Wed, May 18, 2016 at 6:56 AM, Mayuri Tendulkar < mayuri.tendulkar(a)aricent.com> wrote: > Hi > > > > While booting my Minnomboard with coreboot and UEFI, it hangs at below > point while loading the payload. > > > > I followed the procedure to download latest EDK2 tree and built > UEFIPAYLOAD.fd and copied it to coreboot/payloads/external/tianocore > folder and gave this path in make menuconfig. > > > > Has anybody come across this? > > > > BS: BS_PAYLOAD_LOAD times (us): entry 0 run 507070 exit 0 > > FspNotify(EnumInitPhaseReadyToBoot) > > fsp_header_ptr: fffc0094 > > FSP Header Version: 1 > > FSP Revision: 3.3 > > Returned from FspNotify(EnumInitPhaseReadyToBoot) > > POST: 0x7b > > Jumping to boot code at 008002c0(7ac9f000) > > POST: 0xf8 > > CPU0: stack: 0012c000 - 0012d000, lowest used address 0012cb10, stack > used: 1264 bytes > > entry = 0x008002c0 > > lb_start = 0x00100000 > > lb_size = 0x00035650 > > buffer = 0x7ac34000 > > > > Regards > > Mayuri > > *From:* Mayuri Tendulkar > *Sent:* 17 May 2016 14:13 > *To:* 'Zoran Stojsavljevic' <zoran.stojsavljevic(a)gmail.com>; > coreboot(a)coreboot.org > *Subject:* Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard > or Bayley bay > > > > Hi Zoran and Martin > > > > Today I was able to build UEFIPAYLOAD separately. I included .fd file > while building coreboot.rom. > > > > But while booting, getting some errors , so debugging those. > > > > Need to check what more customizations to be done in UEFI for Minnowmax. > > > > Has anybody tried it? > > > > Regards > > Mayuri > > > > *From:* Zoran Stojsavljevic [mailto:zoran.stojsavljevic@gmail.com > <zoran.stojsavljevic(a)gmail.com>] > *Sent:* 16 May 2016 21:04 > *To:* Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com>; > coreboot(a)coreboot.org > *Subject:* Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard > or Bayley bay > > > > OK, Mayuri, > > > > You brought an interesting point. And this point is to be not only > investigated by you, rather also by me and, perhaps, Coreboot community. > > > > Since here, in Bayern/Deutschland is Holiday Day, I went to buy a beer in > Munchen HBf, and while walking there I was thinking about your use case. > Thinking deeper. > > > > I know that you are using some INTEL CPU/SoC (do not remember which one, > if you said one). But, while recapping how BIOS looks like, I did notice > that SEC and PEI phases have nothing to do with UEFI EDK2. EDK 2 comes to > play in DXE phase, where EDK2 actually takes place/overtakes control... > > > > It says to me one major thing I did not notice while ago: that ARM SoCs > are also eligible to run on UEFI compliant OSes, namely WIN 8.1+ (including > WIN 10 and WIN 10 Athens/RT WIN 10). Which makes very interesting IOT case > namely for ARM, allowing it also to compete in WIN space. > > > > Interestingly enough, this idea did not come to my mind till few hours > ago... I guess, Vincent (Zimmer) already thought about that. ;-) > > _______ > > > > Martin (Roth) just replied, to solve this immediate mystery. probably for > the beginning only for INTEL SoCs, but, I really hope, ARM will also > integrate in this concept seamlessly! :-) > > > > Zoran > > _______ > > > > On Mon, May 16, 2016 at 2:29 PM, Mayuri Tendulkar < > mayuri.tendulkar(a)aricent.com> wrote: > > Hi Zoran > > > > I have checked that site and downloaded EDK2 code. I am trying to build it > on Linux but facing some issues. > > But if I generate payload file separately, I need to integrate it in > coreboot separately. > > > > So I am checking if there is way to build the payload in coreboot itself. > > > > Regards > > Mayuri > > > > *From:* Zoran Stojsavljevic [mailto:zoran.stojsavljevic@gmail.com] > *Sent:* 16 May 2016 17:57 > *To:* Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com> > *Cc:* coreboot(a)coreboot.org > *Subject:* Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard > or Bayley bay > > > > Hello Mayuri, > > > > You should check payload called: Tiano Core (true UEFI payload). > > > > Zoran > > > > > > On Mon, May 16, 2016 at 2:12 PM, Mayuri Tendulkar < > mayuri.tendulkar(a)aricent.com> wrote: > > Hi > > > > Is there any mechanism to build UEFI payload directly in coreboot similar > like seabios? > > > > Regards > > Mayuri > > "DISCLAIMER: This message is proprietary to Aricent and is intended solely > for the use of the individual to whom it is addressed. It may contain > privileged or confidential information and should not be circulated or used > for any purpose other than for what it is intended. If you have received > this message in error, please notify the originator immediately. If you are > not the intended recipient, you are notified that you are strictly > prohibited from using, copying, altering, or disclosing the contents of > this message. Aricent accepts no responsibility for loss or damage arising > from the use of the information transmitted by this email including damage > from virus." > > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot > > > > "DISCLAIMER: This message is proprietary to Aricent and is intended solely > for the use of the individual to whom it is addressed. It may contain > privileged or confidential information and should not be circulated or used > for any purpose other than for what it is intended. If you have received > this message in error, please notify the originator immediately. If you are > not the intended recipient, you are notified that you are strictly > prohibited from using, copying, altering, or disclosing the contents of > this message. Aricent accepts no responsibility for loss or damage arising > from the use of the information transmitted by this email including damage > from virus." > > > "DISCLAIMER: This message is proprietary to Aricent and is intended solely > for the use of the individual to whom it is addressed. It may contain > privileged or confidential information and should not be circulated or used > for any purpose other than for what it is intended. If you have received > this message in error, please notify the originator immediately. If you are > not the intended recipient, you are notified that you are strictly > prohibited from using, copying, altering, or disclosing the contents of > this message. Aricent accepts no responsibility for loss or damage arising > from the use of the information transmitted by this email including damage > from virus." >

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Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay
by Mayuri Tendulkar 20 May '16

20 May '16

Can anybody help here? Do we have UEFI payload changes for Minnowmax available? From: Mayuri Tendulkar Sent: 18 May 2016 10:27 To: 'Zoran Stojsavljevic' <zoran.stojsavljevic(a)gmail.com>; 'coreboot(a)coreboot.org' <coreboot(a)coreboot.org> Subject: RE: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay Hi While booting my Minnomboard with coreboot and UEFI, it hangs at below point while loading the payload. I followed the procedure to download latest EDK2 tree and built UEFIPAYLOAD.fd and copied it to coreboot/payloads/external/tianocore folder and gave this path in make menuconfig. Has anybody come across this? BS: BS_PAYLOAD_LOAD times (us): entry 0 run 507070 exit 0 FspNotify(EnumInitPhaseReadyToBoot) fsp_header_ptr: fffc0094 FSP Header Version: 1 FSP Revision: 3.3 Returned from FspNotify(EnumInitPhaseReadyToBoot) POST: 0x7b Jumping to boot code at 008002c0(7ac9f000) POST: 0xf8 CPU0: stack: 0012c000 - 0012d000, lowest used address 0012cb10, stack used: 1264 bytes entry = 0x008002c0 lb_start = 0x00100000 lb_size = 0x00035650 buffer = 0x7ac34000 Regards Mayuri From: Mayuri Tendulkar Sent: 17 May 2016 14:13 To: 'Zoran Stojsavljevic' <zoran.stojsavljevic(a)gmail.com<mailto:zoran.stojsavljevic@gmail.com>>; coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> Subject: RE: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay Hi Zoran and Martin Today I was able to build UEFIPAYLOAD separately. I included .fd file while building coreboot.rom. But while booting, getting some errors , so debugging those. Need to check what more customizations to be done in UEFI for Minnowmax. Has anybody tried it? Regards Mayuri From: Zoran Stojsavljevic [mailto:zoran.stojsavljevic@gmail.com] Sent: 16 May 2016 21:04 To: Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com<mailto:mayuri.tendulkar@aricent.com>>; coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> Subject: Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay OK, Mayuri, You brought an interesting point. And this point is to be not only investigated by you, rather also by me and, perhaps, Coreboot community. Since here, in Bayern/Deutschland is Holiday Day, I went to buy a beer in Munchen HBf, and while walking there I was thinking about your use case. Thinking deeper. I know that you are using some INTEL CPU/SoC (do not remember which one, if you said one). But, while recapping how BIOS looks like, I did notice that SEC and PEI phases have nothing to do with UEFI EDK2. EDK 2 comes to play in DXE phase, where EDK2 actually takes place/overtakes control... It says to me one major thing I did not notice while ago: that ARM SoCs are also eligible to run on UEFI compliant OSes, namely WIN 8.1+ (including WIN 10 and WIN 10 Athens/RT WIN 10). Which makes very interesting IOT case namely for ARM, allowing it also to compete in WIN space. Interestingly enough, this idea did not come to my mind till few hours ago... I guess, Vincent (Zimmer) already thought about that. ;-) _______ Martin (Roth) just replied, to solve this immediate mystery. probably for the beginning only for INTEL SoCs, but, I really hope, ARM will also integrate in this concept seamlessly! :-) Zoran _______ On Mon, May 16, 2016 at 2:29 PM, Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com<mailto:mayuri.tendulkar@aricent.com>> wrote: Hi Zoran I have checked that site and downloaded EDK2 code. I am trying to build it on Linux but facing some issues. But if I generate payload file separately, I need to integrate it in coreboot separately. So I am checking if there is way to build the payload in coreboot itself. Regards Mayuri From: Zoran Stojsavljevic [mailto:zoran.stojsavljevic@gmail.com<mailto:zoran.stojsavljevic@gmail.com>] Sent: 16 May 2016 17:57 To: Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com<mailto:mayuri.tendulkar@aricent.com>> Cc: coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> Subject: Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay Hello Mayuri, You should check payload called: Tiano Core (true UEFI payload). Zoran On Mon, May 16, 2016 at 2:12 PM, Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com<mailto:mayuri.tendulkar@aricent.com>> wrote: Hi Is there any mechanism to build UEFI payload directly in coreboot similar like seabios? Regards Mayuri "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." -- coreboot mailing list: coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> https://www.coreboot.org/mailman/listinfo/coreboot "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus."

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Re: [coreboot] permissions error building external payload
by David Griffith 20 May '16

20 May '16

On Thu, 19 May 2016, Martin Roth wrote: > -coreboot mailing list > > Everyone with a coreboot gerrit account automatically has the rights > to push, but you may need to configure some things. > > Log into the coreboot gerrit if you haven't already done it. > Once logged in, you'll need to set a username first thing. > Next, upload your ssh key or generate an html password. > > If you downloaded the original repo that you've been working in with > anonymous http, at this point you'll want to set a new remote or > origin with the new repo information if you're good with git, or just > clone a new copy of the repo if you're not reasonably expert in git. > > > Make sure you run 'make gitconfig' to set up the hooks. You need the > commit-msg hook at the very least to generate the change-id line in > the commit message. > > Here's the page about git & gerrit on our wiki. https://www.coreboot.org/Git > > > If it's git that's telling you you need push rights, you're trying to > push directly into git, not into gerrit. running 'make gitconfig' > should take care of this as well. Make sure you amend your commit to > get the change-id into the commit message if that's the case. > > For the future though, this is the command to push into gerrit: > git push origin HEAD:refs/for/master Ah, I see. I didn't do "make gitconfig". So, I pulled down a fresh copy of the repo, did "make gitconfig", applied my changes, then typed "git commit -a". I got this: ===begin quote=== ... lint-stable-013-site-local Verify that site-local is not in the coreboot repository ======== success ======== WARNING: please write a paragraph that describes the config symbol fully #33: FILE: payloads/external/OpenBIOS/Kconfig:7: +config OPENBIOS_STABLE WARNING: please write a paragraph that describes the config symbol fully #38: FILE: payloads/external/OpenBIOS/Kconfig:12: +config OPENBIOS_MASTER total: 0 errors, 2 warnings, 117 lines checked ===end quote=== Where should these paragraphs go? Basically I just copied and adapted what I found in payloads/external/SeaBIOS. -- David Griffith dave(a)661.org

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Re: [coreboot] permissions error building external payload
by David Griffith 20 May '16

20 May '16

On Thu, 19 May 2016, Martin Roth wrote: > Hi David, > I think clearing MFLAGS & MAKEFLAGS should fix the issue for you: > > $(MAKE) -C payloads/external/OpenBIOS all \ > HOSTCC="$(HOSTCC)" \ > CONFIG_OPENBIOS_DEVEL=$(CONFIG_OPENBIOS_MASTER) \ > CONFIG_OPENBIOS_STABLE=$(CONFIG_OPENBIOS_STABLE) \ > CONFIG_OPENBIOS_REVISION=$(CONFIG_OPENBIOS_REVISION) \ > CONFIG_OPENBIOS_REVISION_ID=$(CONFIG_OPENBIOS_REVISION_ID) \ > MFLAGS= MAKEFLAGS= That did the trick. Now I need 'Push' rights. -- David Griffith dave(a)661.org

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Re: [coreboot] permissions error building external payload
by David Griffith 19 May '16

19 May '16

On Wed, 18 May 2016, Martin Roth wrote: > Hi David, > You need to add a rule to payloads/external/Makefile.inc as well. > Here's a start: > > payloads/external/OpenBIOS/openbios/obj-x86/openbios-builtin.elf > openbios: $(top)/$(DOTCONFIG) > $(MAKE) -C payloads/external/OpenBIOS all \ > CONFIG_OPENBIOS_MASTER=$(CONFIG_OPENBIOS_MASTER) \ > CONFIG_OPENBIOS_STABLE=$(CONFIG_OPENBIOS_STABLE) \ > CONFIG_OPENBIOS_REVISION=$(CONFIG_OPENBIOS_REVISION) \ > CONFIG_OPENBIOS_REVISION_ID=$(CONFIG_OPENBIOS_REVISION_ID) > > You'll probably want to add some additional variables to configure > openbios to use the coreboot toolchain. All of the variables will need > to be exported or passed on the command line between > external/Makefile.inc and external/OpenBIOS/Makefile. > > With your changes and the ones to Makefile.inc, I get to this point: > > Checking out OpenBIOS from Git > Cloning into 'openbios'... > remote: Counting objects: 11801, done. > remote: Total 11801 (delta 0), reused 0 (delta 0), pack-reused 11801 > Receiving objects: 100% (11801/11801), 2.30 MiB | 1.95 MiB/s, done. > Resolving deltas: 100% (9310/9310), done. > Checking connectivity... done. > Checking out OpenBIOS revision v1.1 > Already on 'master' > Your branch is up-to-date with 'origin/master'. > Switched to a new branch 'coreboot' > CONFIG OpenBIOS v1.1 > MAKE OpenBIOS v1.1 > Configuring OpenBIOS on amd64 for x86 > ERROR: no i486 cross-compiler found ! > make[1]: *** [build] Error 1 I forgot to mention payloads/external/Makefile.inc. Here is the entry I made: payloads/external/OpenBIOS/openbios/obj-x86/openbios-builtin.elf openbios: $(MAKE) -C payloads/external/OpenBIOS all \ HOSTCC="$(HOSTCC)" \ CONFIG_OPENBIOS_DEVEL=$(CONFIG_OPENBIOS_MASTER) \ CONFIG_OPENBIOS_STABLE=$(CONFIG_OPENBIOS_STABLE) \ CONFIG_OPENBIOS_REVISION=$(CONFIG_OPENBIOS_REVISION) \ CONFIG_OPENBIOS_REVISION_ID=$(CONFIG_OPENBIOS_REVISION_ID) With your example, I doubt it would get to the point where I got stuck because you don't have the x86 cross-compiler installed. -- David Griffith dave(a)661.org

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gfx_uma_size on GM45
by Arthur Heymans 19 May '16

19 May '16

Hi On gm45 targets there are some option to set different vram option using the cmos parameter gfx_uma_size. The northbridge code however allows many more option, ranging for 1M to 352M. So I tried making them an on option by modifying cmos.default and the northbridge code that uses those cmos bits. Now the size of this cmos parameter has to be increased for 3 to 4 bits to be able to hold all those options. My problem is that only the 3 smallest bits from the cmos parameter are used. The problem is truly there because hardcoding the vram size instead works fine. these are the changes I tried (at 256M it forgets highest bit and is read as 0 in cmos and 1M is used): --- a/src/mainboard/lenovo/x200/cmos.layout +++ b/src/mainboard/lenovo/x200/cmos.layout @@ -77,9 +77,9 @@ entries 940 1 e 1 uwb # coreboot config options: northbridge -941 3 e 11 gfx_uma_size +941 4 e 11 gfx_uma_size -944 8 h 0 volume +945 8 h 0 volume # coreboot config options: check sums 984 16 h 0 check_sum @@ -125,12 +125,19 @@ enumerations 9 1 Primary 10 0 AHCI 10 1 Compatible -11 0 32M -11 1 48M -11 2 64M -11 3 128M -11 5 96M -11 6 160M +11 0 1M +11 1 4M +11 2 8M +11 3 16M +11 4 32M +11 5 48M +11 6 64M +11 7 128M +11 8 256M +11 9 96M +11 10 160M +11 11 224M +11 12 352M --- a/src/northbridge/intel/gm45/igd.c +++ b/src/northbridge/intel/gm45/igd.c @@ -153,10 +153,10 @@ void igd_compute_ggc(sysinfo_t *const sysinfo) /* Graphics Stolen Memory: 2MB GTT (0x0300) when VT-d disabled, 2MB GTT + 2MB shadow GTT (0x0b00) else. */ if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) { - /* 0 for 32MB */ - gfxsize = 0; + /* 4 for 32MB, default if not set in cmos */ + gfxsize = 4; } - sysinfo->ggc = 0x0300 | ((gfxsize + 5) << 4); + sysinfo->ggc = 0x0300 | ((gfxsize + 1) << 4); if (!(capid & (1 << (48 - 32)))) sysinfo->ggc |= 0x0800; } Kind regards -- Arthur Heymans

2 2

Upstream coreboot/SeaBIOS on google/ninja -- no emmc, video
by Matt DeVillier 19 May '16

19 May '16

Greetings all! Currently I'm working on getting upstream coreboot + SeaBIOS working on a Baytrail-based ChromeOS device (NINJA / AOpen Chromebox commerical). After resolving some config issues which prevented the board from booting, I'm left with two issues on which I'm stuck: 1) the internal emmc / sdhci controller fails to initialize, and is unavailable for boot or OS installation 2) video output works properly for SeaBIOS and grub/syslinux, but output is disabled once the OS / kernel driver loads For the emmc, cbmem shows that the sdhci controller is timing out after setting the initial frequency, somewhere after line 410 of seabios/src/hw/sdcard.c. Since the same exact SeaBIOS payload works properly with the stock ChromeOS firmware (in both the RW_LEGACY and BOOT_STUB slots), I suspect that the issue is with coreboot, but the SoC init is pretty much identical between upstream and NINJA's CrOS branch (save for a few base addresses and offset calculations), so not sure where to start looking. I've also tried putting the sdhci controller back into PCI mode (vs ACPI) which had no effect. For the video output, the same vgabios file is being used as stock CrOS, and same SeaBIOS payload. The i915 kernel driver reports that no displays are connected, and there are some errors in the drm module just prior. I tested with a few different flavors of linux as well as Windows 10, to be certain it wasn't driver-related. Attached are the cbmem and kernel logs from both working (stock CroS firmware + upstream SeaBIOS/BOOT_STUB) and non-working (upstream coreboot+SeaBIOS) cases. As the board hasn't been officially upstreamed yet (something I will do once these issues are resolved), source can be found in my github repo here (it's just 3 commits on top of the current master branch): https://github.com/MattDevo/coreboot/tree/ninja_upstream Hopefully someone can point me in the right direction here :) cheers, Matt

2 2

PSA: old coreboot versions now available via git
by Stefan Reinauer 19 May '16

19 May '16

Hi, the ancient coreboot versions coreboot v1 and coreboot v3 have been recovered from some old svn trees and are now available in the coreboot repository under the branch names "coreboot-v1" and "coreboot-v3". Enjoy, Stefan

1 0

permissions error building external payload
by David Griffith 18 May '16

18 May '16

I ran into a problem with my project to get the coreboot build process to download, build, and include openbios. Things go okay until this point: Creating config files...ok. /usr/bin/xsltproc Building OpenBIOS for x86 Building... error: GEN target/include/openbios-version.h GEN forth/version.fs HOSTCC host/kernel/dict.o /home/dave/proj/coreboot/coreboot/payloads/external/OpenBIOS/openbios/kernel/dict.c:320:1: fatal error: opening dependency file /.d: Permission denied } ^ compilation terminated. I can compile openbios just fine by going into payloads/external/OpenBIOS/openbios/ and typing "make". What am I doing wrong? Here's the contents of payloads/external/OpenBIOS: http://pastebin.com/9DKJGbyc -- David Griffith dave(a)661.org

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