Greetings all! Currently I'm working on getting upstream coreboot + SeaBIOS working on a Baytrail-based ChromeOS device (NINJA / AOpen Chromebox commerical). After resolving some config issues which prevented the board from booting, I'm left with two issues on which I'm stuck:
1) the internal emmc / sdhci controller fails to initialize, and is unavailable for boot or OS installation 2) video output works properly for SeaBIOS and grub/syslinux, but output is disabled once the OS / kernel driver loads
For the emmc, cbmem shows that the sdhci controller is timing out after setting the initial frequency, somewhere after line 410 of seabios/src/hw/sdcard.c. Since the same exact SeaBIOS payload works properly with the stock ChromeOS firmware (in both the RW_LEGACY and BOOT_STUB slots), I suspect that the issue is with coreboot, but the SoC init is pretty much identical between upstream and NINJA's CrOS branch (save for a few base addresses and offset calculations), so not sure where to start looking. I've also tried putting the sdhci controller back into PCI mode (vs ACPI) which had no effect.
For the video output, the same vgabios file is being used as stock CrOS, and same SeaBIOS payload. The i915 kernel driver reports that no displays are connected, and there are some errors in the drm module just prior. I tested with a few different flavors of linux as well as Windows 10, to be certain it wasn't driver-related.
Attached are the cbmem and kernel logs from both working (stock CroS firmware + upstream SeaBIOS/BOOT_STUB) and non-working (upstream coreboot+SeaBIOS) cases.
As the board hasn't been officially upstreamed yet (something I will do once these issues are resolved), source can be found in my github repo here (it's just 3 commits on top of the current master branch): https://github.com/MattDevo/coreboot/tree/ninja_upstream
Hopefully someone can point me in the right direction here :)
cheers, Matt
Hello Matt,
I'll try to help you... Please, do understand that I did not get well what really you are trying to do. Let us do one step at the time.
This step: 2) video output works properly for SeaBIOS and grub/syslinux, but output is disabled once the OS / kernel driver loads. _______
What I am getting from this email is the following (correct me if I am wrong): BYT-FSP -> Coreboot -> (payload) SeaBIOS -> grub (2.0???) -> Linux kernel 3/4.x.y (?).
Now. If you use as payload SeaBIOS, my best understanding is that you'll use CSM (Compatibility Support Mode). So, in other words, you'll use (if you will?) in Coreboot vBIOS (not GOP driver). Now, furthermore, you MUST use vBIOS, since you are using SeaBIOS. And Linux will use vBIOS (not GOP driver), since you'll pass INT 0x15 mechanisms for Linux GFX (using mandatory vBIOS passed from Coreboot), enforced from SeaBIOS - CSM?!
The question here is the following: why, for the change, you do not use as payload TianoCore? This one is UEFI compatible, and very well suits UEFI compliant Linux? In other words, you will use Linux as UEFI compliant/compatible OS. Compliant to Tiano Core, which brings to you UEFI features (initialized by default with Linux). Simply and plain... And see what will happen?
Final line: I suspect, you did not built-in in Coreboot vBIOS package and vBIOS init (just serial output), which is, using SeaBIOS payload (CSM mechanism), I guess, mandatory (for Linux to overtake/inherit legacy, to work with GFX).
Thank you, Zoran
On Sun, May 15, 2016 at 12:19 AM, Matt DeVillier matt.devillier@gmail.com wrote:
Greetings all! Currently I'm working on getting upstream coreboot + SeaBIOS working on a Baytrail-based ChromeOS device (NINJA / AOpen Chromebox commerical). After resolving some config issues which prevented the board from booting, I'm left with two issues on which I'm stuck:
- the internal emmc / sdhci controller fails to initialize, and is
unavailable for boot or OS installation 2) video output works properly for SeaBIOS and grub/syslinux, but output is disabled once the OS / kernel driver loads
For the emmc, cbmem shows that the sdhci controller is timing out after setting the initial frequency, somewhere after line 410 of seabios/src/hw/sdcard.c. Since the same exact SeaBIOS payload works properly with the stock ChromeOS firmware (in both the RW_LEGACY and BOOT_STUB slots), I suspect that the issue is with coreboot, but the SoC init is pretty much identical between upstream and NINJA's CrOS branch (save for a few base addresses and offset calculations), so not sure where to start looking. I've also tried putting the sdhci controller back into PCI mode (vs ACPI) which had no effect.
For the video output, the same vgabios file is being used as stock CrOS, and same SeaBIOS payload. The i915 kernel driver reports that no displays are connected, and there are some errors in the drm module just prior. I tested with a few different flavors of linux as well as Windows 10, to be certain it wasn't driver-related.
Attached are the cbmem and kernel logs from both working (stock CroS firmware + upstream SeaBIOS/BOOT_STUB) and non-working (upstream coreboot+SeaBIOS) cases.
As the board hasn't been officially upstreamed yet (something I will do once these issues are resolved), source can be found in my github repo here (it's just 3 commits on top of the current master branch): https://github.com/MattDevo/coreboot/tree/ninja_upstream
Hopefully someone can point me in the right direction here :)
cheers, Matt
-- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
just to close the loop on this, the issue was the board's gpio.c not be included in the build, due to being conditional on CONFIG_CHROMEOS in the board's Makefile.inc - an difference I didn't catch when comparing with the existing Baytrail ChromeOS reference board (Rambi). Just need to iron out a few things and will commit the board for review
cheers, Matt
On 5/14/2016 5:19 PM, Matt DeVillier wrote:
Greetings all! Currently I'm working on getting upstream coreboot + SeaBIOS working on a Baytrail-based ChromeOS device (NINJA / AOpen Chromebox commerical). After resolving some config issues which prevented the board from booting, I'm left with two issues on which I'm stuck:
- the internal emmc / sdhci controller fails to initialize, and is
unavailable for boot or OS installation 2) video output works properly for SeaBIOS and grub/syslinux, but output is disabled once the OS / kernel driver loads
For the emmc, cbmem shows that the sdhci controller is timing out after setting the initial frequency, somewhere after line 410 of seabios/src/hw/sdcard.c. Since the same exact SeaBIOS payload works properly with the stock ChromeOS firmware (in both the RW_LEGACY and BOOT_STUB slots), I suspect that the issue is with coreboot, but the SoC init is pretty much identical between upstream and NINJA's CrOS branch (save for a few base addresses and offset calculations), so not sure where to start looking. I've also tried putting the sdhci controller back into PCI mode (vs ACPI) which had no effect.
For the video output, the same vgabios file is being used as stock CrOS, and same SeaBIOS payload. The i915 kernel driver reports that no displays are connected, and there are some errors in the drm module just prior. I tested with a few different flavors of linux as well as Windows 10, to be certain it wasn't driver-related.
Attached are the cbmem and kernel logs from both working (stock CroS firmware + upstream SeaBIOS/BOOT_STUB) and non-working (upstream coreboot+SeaBIOS) cases.
As the board hasn't been officially upstreamed yet (something I will do once these issues are resolved), source can be found in my github repo here (it's just 3 commits on top of the current master branch): https://github.com/MattDevo/coreboot/tree/ninja_upstream
Hopefully someone can point me in the right direction here :)
cheers, Matt
-
Matt DeVillier -
Zoran Stojsavljevic