coreboot February 2013

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Patch set updated for coreboot: 02a9862 build system: Retire REQUIRES_BLOB
by Patrick Georgi 17 Feb '13

17 Feb '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2418 -gerrit commit 02a9862d6728ec14c2330059b1fb5008b2241155 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Feb 16 01:06:57 2013 +0100 build system: Retire REQUIRES_BLOB REQUIRES_BLOB assumes that all blob files come from the 3rdparty directory, builds failed when all files were configured to point to other sources. This change modifies the blob mechanism so that cbfs-files can be tagged as "required" with some specification what is missing. If the configured files can't be found (wrong path, missing file), the build system returns a list of descriptions, then aborts. Change-Id: Icc128e3afcee8acf49bff9409b93af7769db3517 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- Makefile | 3 +++ Makefile.inc | 12 +++++++----- src/Kconfig | 10 ---------- src/cpu/amd/geode_gx2/Makefile.inc | 2 ++ src/cpu/amd/geode_lx/Kconfig | 1 - src/cpu/amd/geode_lx/Makefile.inc | 2 ++ src/southbridge/amd/agesa/hudson/Kconfig | 3 --- src/southbridge/amd/agesa/hudson/Makefile.inc | 4 ++++ 8 files changed, 18 insertions(+), 19 deletions(-) diff --git a/Makefile b/Makefile index 92b4d0b..9aafe7c 100644 --- a/Makefile +++ b/Makefile @@ -232,6 +232,9 @@ evaluate_subdirs= \ # collect all object files eligible for building subdirs:=$(TOPLEVEL) $(eval $(call evaluate_subdirs)) +ifeq ($(FAILBUILD),1) +$(error cannot continue build) +endif # Eliminate duplicate mentions of source files in a class $(foreach class,$(classes),$(eval $(class)-srcs:=$(sort $($(class)-srcs)))) diff --git a/Makefile.inc b/Makefile.inc index 069bdfe..ad97363 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -105,10 +105,6 @@ endif ifeq ($(CONFIG_USE_BLOBS),y) forgetthis:=$(shell git submodule update --init --checkout 3rdparty) -else -ifeq ($(CONFIG_REQUIRES_BLOB),y) -$(error Your current configuration requires binary-only components, but you did not choose to use them) -endif endif bootblock-c-ccopts:=-D__BOOT_BLOCK__ -D__PRE_RAM__ @@ -164,6 +160,11 @@ cbfs-files-handler= \ $(if $(wildcard $(1)$($(2)-file)), \ $(eval tmp-cbfs-file:= $(wildcard $(1)$($(2)-file))), \ $(eval tmp-cbfs-file:= $($(2)-file))) \ + $(if $(strip $($(2)-required)), \ + $(if $(wildcard $(tmp-cbfs-file)),, \ + $(info This build configuration requires $($(2)-required)) \ + $(eval FAILBUILD:=1) \ + )) \ $(if $(tmp-cbfs-method), \ $(eval tmp-old-cbfs-file:=$(tmp-cbfs-file)) \ $(eval tmp-cbfs-file:=$(shell mkdir -p $(obj)/mainboard/$(MAINBOARDDIR); mktemp $(obj)/mainboard/$(MAINBOARDDIR)/cbfs-file.XXXXXX).out) \ @@ -172,7 +173,8 @@ cbfs-files-handler= \ $(eval $(2)-name:=) \ $(eval $(2)-type:=) \ $(eval $(2)-compression:=) \ - $(eval $(2)-position:=) + $(eval $(2)-position:=) \ + $(eval $(2)-required:=) ####################################################################### # a variety of flags for our build diff --git a/src/Kconfig b/src/Kconfig index 4e7957e..2dc251d 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -184,16 +184,6 @@ config USE_BLOBS might be required for some chipsets or boards. This flag ensures that a "Free" option remains available for users. -config REQUIRES_BLOB - bool - default n - help - This option can be configured by boards that require the blobs - repository for the default configuration. It will make the build - fail if USE_BLOBS is disabled. Users that still desire to do a - coreboot build for such a board can override this manually, but - this option serves as warning that it might fail. - config COVERAGE bool "Code coverage support" depends on COMPILER_GCC diff --git a/src/cpu/amd/geode_gx2/Makefile.inc b/src/cpu/amd/geode_gx2/Makefile.inc index b3f3de9..f42f1bd 100644 --- a/src/cpu/amd/geode_gx2/Makefile.inc +++ b/src/cpu/amd/geode_gx2/Makefile.inc @@ -11,3 +11,5 @@ cpu_incs += $(src)/cpu/amd/geode_gx2/cache_as_ram.inc cbfs-files-$(CONFIG_GEODE_VSA_FILE) += vsa vsa-file = $(call strip_quotes,$(CONFIG_VSA_FILENAME)):vsa vsa-type = stage +vsa-required = VSA binary + diff --git a/src/cpu/amd/geode_lx/Kconfig b/src/cpu/amd/geode_lx/Kconfig index 777dc94..7deb100 100644 --- a/src/cpu/amd/geode_lx/Kconfig +++ b/src/cpu/amd/geode_lx/Kconfig @@ -19,7 +19,6 @@ config GEODE_VSA bool default y select PCI_OPTION_ROM_RUN_REALMODE - select REQUIRES_BLOB config GEODE_VSA_FILE bool "Add a VSA image" diff --git a/src/cpu/amd/geode_lx/Makefile.inc b/src/cpu/amd/geode_lx/Makefile.inc index c9df888..b1922ae 100644 --- a/src/cpu/amd/geode_lx/Makefile.inc +++ b/src/cpu/amd/geode_lx/Makefile.inc @@ -11,3 +11,5 @@ cpu_incs += $(src)/cpu/amd/geode_lx/cache_as_ram.inc cbfs-files-$(CONFIG_GEODE_VSA_FILE) += vsa vsa-file = $(call strip_quotes,$(CONFIG_VSA_FILENAME)):vsa vsa-type = stage +vsa-required = VSA binary (available in coreboot/3rdparty if enabled, both binary and MASM source code) + diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index 92e5960..6cbed53 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -46,21 +46,18 @@ if SOUTHBRIDGE_AMD_AGESA_HUDSON config HUDSON_XHCI_FWM bool "Add xhci firmware" default y - select REQUIRES_BLOB help Add Hudson 2/3/4 XHCI Firmware to support the onboard usb3.0 config HUDSON_IMC_FWM bool "Add imc firmware" default y - select REQUIRES_BLOB help Add Hudson 2/3/4 IMC Firmware to support the onboard fan control config HUDSON_GEC_FWM bool "Add gec firmware" default n - select REQUIRES_BLOB help Add Hudson 2/3/4 GEC Firmware diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index c9a1731..18a0ffb 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -74,6 +74,7 @@ cbfs-files-y += hudson/xhci hudson/xhci-file := $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) hudson/xhci-position := $(HUDSON_XHCI_POSITION) hudson/xhci-type := raw +hudson/xhci-required := Hudson XHCI firmware (available in coreboot/3rdparty if enabled) endif ifeq ($(CONFIG_HUDSON_IMC_FWM), y) @@ -81,6 +82,7 @@ cbfs-files-y += hudson/imc hudson/imc-file := $(call strip_quotes, $(CONFIG_HUDSON_IMC_FWM_FILE)) hudson/imc-position := $(HUDSON_IMC_POSITION) hudson/imc-type := raw +hudson/imc-required := Hudson IMC Firmware (available in coreboot/3rdparty if enabled) endif ifeq ($(CONFIG_HUDSON_GEC_FWM), y) @@ -88,6 +90,7 @@ cbfs-files-y += hudson/gec hudson/gec-file := $(call strip_quotes, $(CONFIG_HUDSON_GEC_FWM_FILE)) hudson/gec-position := $(HUDSON_GEC_POSITION) hudson/gec-type := raw +hudson/gec-required := Hudson Gigabit Ethernet Controller Firmware (Contact your AMD representative) endif #ifeq ($(CONFIG_HUDSON_SATA_AHCI), y) @@ -96,5 +99,6 @@ stripped_ahci_rom_id = $(call strip_quotes,$(CONFIG_AHCI_ROM_ID)) cbfs-files-y += pci$(stripped_ahci_rom_id).rom pci$(stripped_ahci_rom_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_ROM_FILE)) pci$(stripped_ahci_rom_id).rom-type := optionrom +pci$(stripped_ahci_rom_id).rom-required := Hudson AHCI Option ROM (Contact your AMD representative) #endif endif

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Patch set updated for coreboot: ba3d2c5 AMD S3: Introduce Kconfig variable 'S3_DATA_SIZE'
by Zheng Bao 17 Feb '13

17 Feb '13

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2383 -gerrit commit ba3d2c5023bb15ca147e31bb100d54ebdd994aa7 Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Sun Feb 17 18:38:38 2013 +0800 AMD S3: Introduce Kconfig variable 'S3_DATA_SIZE' Currently the size of the volatile storage for S3 reserved in the image is hardcoded to 32768 bytes. Make that configurable by introducing the Kconfig 'S3_DATA_SIZE'. As the storage space is needed for storing non-volatile, volatile and MTRR data, add a check if the size is big enough. Change-Id: I9152797cf0045c8da48109a9d760e417717686db Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- src/cpu/amd/agesa/s3_resume.h | 4 ++++ src/southbridge/amd/Makefile.inc | 2 +- src/southbridge/amd/agesa/hudson/Kconfig | 8 ++++++++ src/southbridge/amd/cimx/sb700/Kconfig | 8 ++++++++ src/southbridge/amd/cimx/sb800/Kconfig | 8 ++++++++ src/southbridge/amd/cimx/sb900/Kconfig | 8 ++++++++ 6 files changed, 37 insertions(+), 1 deletion(-) diff --git a/src/cpu/amd/agesa/s3_resume.h b/src/cpu/amd/agesa/s3_resume.h index 367cc3f..af5b509 100644 --- a/src/cpu/amd/agesa/s3_resume.h +++ b/src/cpu/amd/agesa/s3_resume.h @@ -28,6 +28,10 @@ #define S3_DATA_MTRR_POS (CONFIG_S3_DATA_POS + S3_DATA_VOLATILE_SIZE) #define S3_DATA_NONVOLATILE_POS (CONFIG_S3_DATA_POS + S3_DATA_VOLATILE_SIZE + S3_DATA_MTRR_SIZE) +#if (S3_DATA_VOLATILE_SIZE + S3_DATA_MTRR_SIZE + S3_DATA_NONVOLATILE_SIZE) > CONFIG_S3_DATA_SIZE +#error "Please increase the value of S3_DATA_SIZE" +#endif + typedef enum { S3DataTypeNonVolatile=0, ///< NonVolatile Data Type S3DataTypeVolatile ///< Volatile Data Type diff --git a/src/southbridge/amd/Makefile.inc b/src/southbridge/amd/Makefile.inc index 5f54314..cce4702 100644 --- a/src/southbridge/amd/Makefile.inc +++ b/src/southbridge/amd/Makefile.inc @@ -22,7 +22,7 @@ ifeq ($(CONFIG_CPU_AMD_AGESA), y) $(obj)/coreboot_s3nv.rom: $(obj)/config.h echo " S3 NVRAM $(CONFIG_S3_DATA_POS) (S3 storage area)" # force C locale, so cygwin awk doesn't try to interpret the 0xff below as UTF-8 (or worse) - LC_ALL=C awk 'BEGIN {for (i=0; i<32768; i++) {printf "%c", 255}}' > $@.tmp + printf %d $(CONFIG_S3_DATA_SIZE) | LC_ALL=C awk '{for (i=0; i<$$1; i++) {printf "%c", 255}}' > $@.tmp mv $@.tmp $@ cbfs-files-y += s3nv diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index a469970..644d356 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -212,6 +212,14 @@ config S3_DATA_POS For a system with S3 feature, the BIOS needs to save some data to non-volatile storage at cold boot stage. +config S3_DATA_SIZE + hex "S3 volatile storage size" + default 0x8000 + depends on HAVE_ACPI_RESUME + help + For a system with S3 feature, the BIOS needs to save some data to + non-volatile storage at cold boot stage. + config HUDSON_LEGACY_FREE bool "System is legacy free" help diff --git a/src/southbridge/amd/cimx/sb700/Kconfig b/src/southbridge/amd/cimx/sb700/Kconfig index 706309d..1a88f48 100644 --- a/src/southbridge/amd/cimx/sb700/Kconfig +++ b/src/southbridge/amd/cimx/sb700/Kconfig @@ -68,5 +68,13 @@ config S3_DATA_POS For a system with S3 feature, the BIOS needs to save some data to non-volatile storage at cold boot stage. +config S3_DATA_SIZE + hex "S3 volatile storage size" + default 0x8000 + depends on HAVE_ACPI_RESUME + help + For a system with S3 feature, the BIOS needs to save some data to + non-volatile storage at cold boot stage. + endif #SOUTHBRIDGE_AMD_CIMX_SB700 diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index f56e017..a065f77 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -130,6 +130,14 @@ config S3_DATA_POS For a system with S3 feature, the BIOS needs to save some data to non-volatile storage at cold boot stage. +config S3_DATA_SIZE + hex "S3 volatile storage size" + default 0x8000 + depends on HAVE_ACPI_RESUME + help + For a system with S3 feature, the BIOS needs to save some data to + non-volatile storage at cold boot stage. + config SB800_IMC_FWM bool "Add IMC firmware" default n diff --git a/src/southbridge/amd/cimx/sb900/Kconfig b/src/southbridge/amd/cimx/sb900/Kconfig index 3cadba1..897f0e6 100755 --- a/src/southbridge/amd/cimx/sb900/Kconfig +++ b/src/southbridge/amd/cimx/sb900/Kconfig @@ -61,5 +61,13 @@ config S3_DATA_POS For a system with S3 feature, the BIOS needs to save some data to non-volatile storage at cold boot stage. +config S3_DATA_SIZE + hex "S3 volatile storage size" + default 0x8000 + depends on HAVE_ACPI_RESUME + help + For a system with S3 feature, the BIOS needs to save some data to + non-volatile storage at cold boot stage. + endif #SOUTHBRIDGE_AMD_CIMX_SB900

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Patch set updated for coreboot: b097a0d AMD S3: Fix typo vol*a*tile in southbridge Kconfig
by Paul Menzel 17 Feb '13

17 Feb '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2437 -gerrit commit b097a0d6a0d974c58b82672f08b9b3ce611c7529 Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Sun Feb 17 16:41:14 2013 +0800 AMD S3: Fix typo vol*a*tile in southbridge Kconfig Change non-volitile to non-volatile. Change-Id: Idfc7db3b3dcf078f0f3134fc62679bed439a4fd2 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- src/southbridge/amd/agesa/hudson/Kconfig | 2 +- src/southbridge/amd/cimx/sb700/Kconfig | 2 +- src/southbridge/amd/cimx/sb800/Kconfig | 2 +- src/southbridge/amd/cimx/sb900/Kconfig | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index 92e5960..35d8996 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -210,7 +210,7 @@ config S3_VOLATILE_POS depends on HAVE_ACPI_RESUME help For a system with S3 feature, the BIOS needs to save some data to - non-volitile storage at cold boot stage. + non-volatile storage at cold boot stage. config HUDSON_LEGACY_FREE bool "System is legacy free" diff --git a/src/southbridge/amd/cimx/sb700/Kconfig b/src/southbridge/amd/cimx/sb700/Kconfig index f139450..ee740d5 100644 --- a/src/southbridge/amd/cimx/sb700/Kconfig +++ b/src/southbridge/amd/cimx/sb700/Kconfig @@ -66,7 +66,7 @@ config S3_VOLATILE_POS depends on HAVE_ACPI_RESUME help For a system with S3 feature, the BIOS needs to save some data to - non-volitile storage at cold boot stage. + non-volatile storage at cold boot stage. endif #SOUTHBRIDGE_AMD_CIMX_SB700 diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index 1f3ee9a..2620974 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -128,7 +128,7 @@ config S3_VOLATILE_POS depends on HAVE_ACPI_RESUME help For a system with S3 feature, the BIOS needs to save some data to - non-volitile storage at cold boot stage. + non-volatile storage at cold boot stage. config SB800_IMC_FWM bool "Add IMC firmware" diff --git a/src/southbridge/amd/cimx/sb900/Kconfig b/src/southbridge/amd/cimx/sb900/Kconfig index acc369e..0efbf97 100755 --- a/src/southbridge/amd/cimx/sb900/Kconfig +++ b/src/southbridge/amd/cimx/sb900/Kconfig @@ -59,7 +59,7 @@ config S3_VOLATILE_POS depends on HAVE_ACPI_RESUME help For a system with S3 feature, the BIOS needs to save some data to - non-volitile storage at cold boot stage. + non-volatile storage at cold boot stage. endif #SOUTHBRIDGE_AMD_CIMX_SB900

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Patch set updated for coreboot: 7c9d956 AMD S3: Program the flash in a bigger data packet
by Zheng Bao 17 Feb '13

17 Feb '13

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2306 -gerrit commit 7c9d9567b0c0e3f4b7aaa7ae70612bc4b7cacc50 Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Sun Feb 17 17:27:46 2013 +0800 AMD S3: Program the flash in a bigger data packet According to spi.c in src/southbridge/amd/agesa/hudson readwrite = (bytesin + readoffby1) << 4 | bytesout; We can see that Hudson limits the SPI programming data packet size as 15. We used to write data to SPI in dword mode. It didn't take full advantage of the data packet size. We need to leverage that to speed up programming time. Change-Id: I615e3c8e754e58702247bc26cfffbedaf5827ea8 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- src/cpu/amd/agesa/s3_resume.c | 56 +++++++++++++++++-------------------------- 1 file changed, 22 insertions(+), 34 deletions(-) diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index ee9d7c9..278c1da 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -178,29 +178,21 @@ void OemAgesaSaveMtrr(void) /* Fixed MTRRs */ msr_data = rdmsr(0x250); - flash->write(flash, nvram_pos, 4, &msr_data.lo); - nvram_pos += 4; - flash->write(flash, nvram_pos, 4, &msr_data.hi); - nvram_pos += 4; + flash->write(flash, nvram_pos, 8, &msr_data); + nvram_pos += 8; msr_data = rdmsr(0x258); - flash->write(flash, nvram_pos, 4, &msr_data.lo); - nvram_pos += 4; - flash->write(flash, nvram_pos, 4, &msr_data.hi); - nvram_pos += 4; + flash->write(flash, nvram_pos, 8, &msr_data); + nvram_pos += 8; msr_data = rdmsr(0x259); - flash->write(flash, nvram_pos, 4, &msr_data.lo); - nvram_pos += 4; - flash->write(flash, nvram_pos, 4, &msr_data.hi); - nvram_pos += 4; + flash->write(flash, nvram_pos, 8, &msr_data); + nvram_pos += 8; for (i = 0x268; i < 0x270; i++) { msr_data = rdmsr(i); - flash->write(flash, nvram_pos, 4, &msr_data.lo); - nvram_pos += 4; - flash->write(flash, nvram_pos, 4, &msr_data.hi); - nvram_pos += 4; + flash->write(flash, nvram_pos, 8, &msr_data); + nvram_pos += 8; } /* Disable access to AMD RdDram and WrDram extension bits */ @@ -211,32 +203,24 @@ void OemAgesaSaveMtrr(void) /* Variable MTRRs */ for (i = 0x200; i < 0x210; i++) { msr_data = rdmsr(i); - flash->write(flash, nvram_pos, 4, &msr_data.lo); - nvram_pos += 4; - flash->write(flash, nvram_pos, 4, &msr_data.hi); - nvram_pos += 4; + flash->write(flash, nvram_pos, 8, &msr_data); + nvram_pos += 8; } /* SYS_CFG */ msr_data = rdmsr(0xC0010010); - flash->write(flash, nvram_pos, 4, &msr_data.lo); - nvram_pos += 4; - flash->write(flash, nvram_pos, 4, &msr_data.hi); - nvram_pos += 4; + flash->write(flash, nvram_pos, 8, &msr_data); + nvram_pos += 8; /* TOM */ msr_data = rdmsr(0xC001001A); - flash->write(flash, nvram_pos, 4, &msr_data.lo); - nvram_pos += 4; - flash->write(flash, nvram_pos, 4, &msr_data.hi); - nvram_pos += 4; + flash->write(flash, nvram_pos, 8, &msr_data); + nvram_pos += 8; /* TOM2 */ msr_data = rdmsr(0xC001001D); - flash->write(flash, nvram_pos, 4, &msr_data.lo); - nvram_pos += 4; - flash->write(flash, nvram_pos, 4, &msr_data.hi); - nvram_pos += 4; + flash->write(flash, nvram_pos, 8, &msr_data); + nvram_pos += 8; flash->spi->rw = SPI_WRITE_FLAG; spi_release_bus(flash->spi); @@ -290,13 +274,17 @@ u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data) flash->erase(flash, S3_DATA_VOLATILE_POS, S3_DATA_VOLATILE_SIZE); } +#ifndef SPI_DATA_PACKET_SIZE +#define SPI_DATA_PACKET_SIZE 0xF +#endif nvram_pos = 0; flash->write(flash, nvram_pos + pos, sizeof(DataSize), &DataSize); - for (nvram_pos = 0; nvram_pos < DataSize; nvram_pos += 4) { + for (nvram_pos = 0; nvram_pos < DataSize - SPI_DATA_PACKET_SIZE; nvram_pos += SPI_DATA_PACKET_SIZE) { data = *(u32 *) (Data + nvram_pos); - flash->write(flash, nvram_pos + pos + 4, sizeof(u32), (u32 *)(Data + nvram_pos)); + flash->write(flash, nvram_pos + pos + 4, SPI_DATA_PACKET_SIZE, (u8 *)(Data + nvram_pos)); } + flash->write(flash, nvram_pos + pos + 4, DataSize % SPI_DATA_PACKET_SIZE, (u8 *)(Data + nvram_pos)); flash->spi->rw = SPI_WRITE_FLAG; spi_release_bus(flash->spi);

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New patch to review for coreboot: 5aa32e0 AMD S3: Fix a typo in southbridge Kconfig
by Zheng Bao 17 Feb '13

17 Feb '13

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2437 -gerrit commit 5aa32e0c897df01b7f39dc48163066d4d304d428 Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Sun Feb 17 16:41:14 2013 +0800 AMD S3: Fix a typo in southbridge Kconfig Change non-volitile to non-volatile. Change-Id: Idfc7db3b3dcf078f0f3134fc62679bed439a4fd2 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- src/southbridge/amd/agesa/hudson/Kconfig | 2 +- src/southbridge/amd/cimx/sb700/Kconfig | 2 +- src/southbridge/amd/cimx/sb800/Kconfig | 2 +- src/southbridge/amd/cimx/sb900/Kconfig | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index 92e5960..35d8996 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -210,7 +210,7 @@ config S3_VOLATILE_POS depends on HAVE_ACPI_RESUME help For a system with S3 feature, the BIOS needs to save some data to - non-volitile storage at cold boot stage. + non-volatile storage at cold boot stage. config HUDSON_LEGACY_FREE bool "System is legacy free" diff --git a/src/southbridge/amd/cimx/sb700/Kconfig b/src/southbridge/amd/cimx/sb700/Kconfig index f139450..ee740d5 100644 --- a/src/southbridge/amd/cimx/sb700/Kconfig +++ b/src/southbridge/amd/cimx/sb700/Kconfig @@ -66,7 +66,7 @@ config S3_VOLATILE_POS depends on HAVE_ACPI_RESUME help For a system with S3 feature, the BIOS needs to save some data to - non-volitile storage at cold boot stage. + non-volatile storage at cold boot stage. endif #SOUTHBRIDGE_AMD_CIMX_SB700 diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index 1f3ee9a..2620974 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -128,7 +128,7 @@ config S3_VOLATILE_POS depends on HAVE_ACPI_RESUME help For a system with S3 feature, the BIOS needs to save some data to - non-volitile storage at cold boot stage. + non-volatile storage at cold boot stage. config SB800_IMC_FWM bool "Add IMC firmware" diff --git a/src/southbridge/amd/cimx/sb900/Kconfig b/src/southbridge/amd/cimx/sb900/Kconfig index acc369e..0efbf97 100755 --- a/src/southbridge/amd/cimx/sb900/Kconfig +++ b/src/southbridge/amd/cimx/sb900/Kconfig @@ -59,7 +59,7 @@ config S3_VOLATILE_POS depends on HAVE_ACPI_RESUME help For a system with S3 feature, the BIOS needs to save some data to - non-volitile storage at cold boot stage. + non-volatile storage at cold boot stage. endif #SOUTHBRIDGE_AMD_CIMX_SB900

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Patch set updated for coreboot: 03d26c6 AMD S3: Introduce Kconfig variable 'S3_DATA_SIZE'
by Zheng Bao 17 Feb '13

17 Feb '13

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2383 -gerrit commit 03d26c6d02caefad6b12ff5d04c9c4c4f782976e Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Sun Feb 17 17:11:27 2013 +0800 AMD S3: Introduce Kconfig variable 'S3_DATA_SIZE' Currently the size of the volatile storage for S3 reserved in the image is hardcoded to 32768 bytes. Make that configurable by introducing the Kconfig 'S3_DATA_SIZE'. As the storage space is needed for storing non-volatile, volatile and MTRR data. Therefore add a check if the size is big enough. Change-Id: I9152797cf0045c8da48109a9d760e417717686db Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zheng Bao <fishbaozi(a)gmail.com> --- src/cpu/amd/agesa/s3_resume.h | 4 ++++ src/southbridge/amd/Makefile.inc | 2 +- src/southbridge/amd/agesa/hudson/Kconfig | 8 ++++++++ src/southbridge/amd/cimx/sb700/Kconfig | 8 ++++++++ src/southbridge/amd/cimx/sb800/Kconfig | 8 ++++++++ src/southbridge/amd/cimx/sb900/Kconfig | 8 ++++++++ 6 files changed, 37 insertions(+), 1 deletion(-) diff --git a/src/cpu/amd/agesa/s3_resume.h b/src/cpu/amd/agesa/s3_resume.h index 367cc3f..cdf41e6 100644 --- a/src/cpu/amd/agesa/s3_resume.h +++ b/src/cpu/amd/agesa/s3_resume.h @@ -28,6 +28,10 @@ #define S3_DATA_MTRR_POS (CONFIG_S3_DATA_POS + S3_DATA_VOLATILE_SIZE) #define S3_DATA_NONVOLATILE_POS (CONFIG_S3_DATA_POS + S3_DATA_VOLATILE_SIZE + S3_DATA_MTRR_SIZE) +#if (S3_DATA_VOLATILE_SIZE + S3_DATA_MTRR_SIZE + S3_DATA_NONVOLATILE_SIZE) > CONFIG_S3_DATA_SIZE +#error "Please increase the value of S3_VOLATILE_SIZE" +#endif + typedef enum { S3DataTypeNonVolatile=0, ///< NonVolatile Data Type S3DataTypeVolatile ///< Volatile Data Type diff --git a/src/southbridge/amd/Makefile.inc b/src/southbridge/amd/Makefile.inc index 5f54314..cce4702 100644 --- a/src/southbridge/amd/Makefile.inc +++ b/src/southbridge/amd/Makefile.inc @@ -22,7 +22,7 @@ ifeq ($(CONFIG_CPU_AMD_AGESA), y) $(obj)/coreboot_s3nv.rom: $(obj)/config.h echo " S3 NVRAM $(CONFIG_S3_DATA_POS) (S3 storage area)" # force C locale, so cygwin awk doesn't try to interpret the 0xff below as UTF-8 (or worse) - LC_ALL=C awk 'BEGIN {for (i=0; i<32768; i++) {printf "%c", 255}}' > $@.tmp + printf %d $(CONFIG_S3_DATA_SIZE) | LC_ALL=C awk '{for (i=0; i<$$1; i++) {printf "%c", 255}}' > $@.tmp mv $@.tmp $@ cbfs-files-y += s3nv diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index a469970..644d356 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -212,6 +212,14 @@ config S3_DATA_POS For a system with S3 feature, the BIOS needs to save some data to non-volatile storage at cold boot stage. +config S3_DATA_SIZE + hex "S3 volatile storage size" + default 0x8000 + depends on HAVE_ACPI_RESUME + help + For a system with S3 feature, the BIOS needs to save some data to + non-volatile storage at cold boot stage. + config HUDSON_LEGACY_FREE bool "System is legacy free" help diff --git a/src/southbridge/amd/cimx/sb700/Kconfig b/src/southbridge/amd/cimx/sb700/Kconfig index 706309d..1a88f48 100644 --- a/src/southbridge/amd/cimx/sb700/Kconfig +++ b/src/southbridge/amd/cimx/sb700/Kconfig @@ -68,5 +68,13 @@ config S3_DATA_POS For a system with S3 feature, the BIOS needs to save some data to non-volatile storage at cold boot stage. +config S3_DATA_SIZE + hex "S3 volatile storage size" + default 0x8000 + depends on HAVE_ACPI_RESUME + help + For a system with S3 feature, the BIOS needs to save some data to + non-volatile storage at cold boot stage. + endif #SOUTHBRIDGE_AMD_CIMX_SB700 diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index f56e017..a065f77 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -130,6 +130,14 @@ config S3_DATA_POS For a system with S3 feature, the BIOS needs to save some data to non-volatile storage at cold boot stage. +config S3_DATA_SIZE + hex "S3 volatile storage size" + default 0x8000 + depends on HAVE_ACPI_RESUME + help + For a system with S3 feature, the BIOS needs to save some data to + non-volatile storage at cold boot stage. + config SB800_IMC_FWM bool "Add IMC firmware" default n diff --git a/src/southbridge/amd/cimx/sb900/Kconfig b/src/southbridge/amd/cimx/sb900/Kconfig index 3cadba1..897f0e6 100755 --- a/src/southbridge/amd/cimx/sb900/Kconfig +++ b/src/southbridge/amd/cimx/sb900/Kconfig @@ -61,5 +61,13 @@ config S3_DATA_POS For a system with S3 feature, the BIOS needs to save some data to non-volatile storage at cold boot stage. +config S3_DATA_SIZE + hex "S3 volatile storage size" + default 0x8000 + depends on HAVE_ACPI_RESUME + help + For a system with S3 feature, the BIOS needs to save some data to + non-volatile storage at cold boot stage. + endif #SOUTHBRIDGE_AMD_CIMX_SB900

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Patch set updated for coreboot: 726b349 AMD S3: Include the s3_resume.h only when S3 is enabled.
by Zheng Bao 17 Feb '13

17 Feb '13

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2384 -gerrit commit 726b3498bf1e72a1bff76e52425bb88d89a6f197 Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Sun Feb 17 16:25:36 2013 +0800 AMD S3: Include the s3_resume.h only when S3 is enabled. Change-Id: I9a6c4f61e5dda6665f92c8526bb26a458ee2b739 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- src/cpu/amd/agesa/family14/model_14_init.c | 2 ++ src/cpu/amd/agesa/family15tn/model_15_init.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c index 9cc36e2..7fac016 100644 --- a/src/cpu/amd/agesa/family14/model_14_init.c +++ b/src/cpu/amd/agesa/family14/model_14_init.c @@ -33,7 +33,9 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/amdfam14.h> #include <arch/acpi.h> +#if CONFIG_HAVE_ACPI_RESUME #include <cpu/amd/agesa/s3_resume.h> +#endif #define MCI_STATUS 0x401 diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c index 39533bb..68cb0d2 100644 --- a/src/cpu/amd/agesa/family15tn/model_15_init.c +++ b/src/cpu/amd/agesa/family15tn/model_15_init.c @@ -33,7 +33,9 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/amdfam15.h> #include <arch/acpi.h> +#if CONFIG_HAVE_ACPI_RESUME #include <cpu/amd/agesa/s3_resume.h> +#endif msr_t rdmsr_amd(u32 index) {

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Patch set updated for coreboot: 9b22639 armv7: init stack to 0xdeadbeef
by David Hendricks 17 Feb '13

17 Feb '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2421 -gerrit commit 9b22639a271f038fef19f150fa589bce84664a6d Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Feb 15 17:50:20 2013 -0800 armv7: init stack to 0xdeadbeef This adds a simple loop which initializes the stack to 0xdeadbeef which is used by checkstack(). Change-Id: I8aecf7bfb1067de68c4080c1fcb7eefa28fd04a7 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/bootblock.inc | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/src/arch/armv7/bootblock.inc b/src/arch/armv7/bootblock.inc index c8cfe5e..da063a6 100644 --- a/src/arch/armv7/bootblock.inc +++ b/src/arch/armv7/bootblock.inc @@ -71,6 +71,21 @@ reset: cmp r1, #0 bne wait_for_interrupt @ If this is not core0, wait + /* + * Initialize the stack to a known value. This is used to check for + * stack overflow later in the boot process. + */ + ldr r0, .Stack + ldr r1, .Stack_size + sub r0, r0, r1 + ldr r1, .Stack + ldr r2, =0xdeadbeef +init_stack_loop: + str r2, [r0] + add r0, #4 + cmp r0, r1 + bne init_stack_loop + /* Set stackpointer in internal RAM to call board_init_f */ call_bootblock: ldr sp, .Stack /* Set up stack pointer */ @@ -95,3 +110,6 @@ wait_for_interrupt: .align 2 .Stack: .word CONFIG_STACK_TOP +.align 2 +.Stack_size: + .word CONFIG_STACK_SIZE

1 0

New patch to review for coreboot: a9f0bff romcc: Don't fail on function prototypes
by Patrick Georgi 16 Feb '13

16 Feb '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2424 -gerrit commit a9f0bffe1c97fe0285c3780ccd0886078705ef9c Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Feb 16 20:16:34 2013 +0100 romcc: Don't fail on function prototypes Instead, ignore them. One is as non-standard as the other and ignoring is more convenient since we don't need to guard prototypes with #ifndef __ROMCC_ all the time. Change-Id: I7be93a2ed0966ba1a86f0294132a204e6c8bf24f Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- util/romcc/romcc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/util/romcc/romcc.c b/util/romcc/romcc.c index 15e950c..d371506 100644 --- a/util/romcc/romcc.c +++ b/util/romcc/romcc.c @@ -13465,7 +13465,8 @@ static struct triple *do_decl(struct compile_state *state, internal_error(state, 0, "Undefined storage class"); } if ((type->type & TYPE_MASK) == TYPE_FUNCTION) { - error(state, 0, "Function prototypes not supported"); + // ignore function prototypes + return def; } if (ident && ((type->type & TYPE_MASK) == TYPE_ARRAY) &&

1 0

Patch set updated for coreboot: d23410b build system: Retire REQUIRES_BLOB
by Patrick Georgi 16 Feb '13

16 Feb '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2418 -gerrit commit d23410bd2647e34a033cfa9dd5acfd48aaa17365 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Feb 16 01:06:57 2013 +0100 build system: Retire REQUIRES_BLOB REQUIRES_BLOB assumes that all blob files come from the 3rdparty directory, builds failed when all files were configured to point to other sources. This change modifies the blob mechanism so that cbfs-files can be tagged as "required" with some specification what is missing. If the configured files can't be found (wrong path, missing file), the build system returns a list of descriptions, then aborts. Change-Id: Icc128e3afcee8acf49bff9409b93af7769db3517 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- Makefile | 3 +++ Makefile.inc | 12 +++++++----- src/Kconfig | 10 ---------- src/cpu/amd/geode_gx2/Makefile.inc | 2 ++ src/cpu/amd/geode_lx/Kconfig | 1 - src/cpu/amd/geode_lx/Makefile.inc | 2 ++ src/southbridge/amd/agesa/hudson/Kconfig | 3 --- src/southbridge/amd/agesa/hudson/Makefile.inc | 4 ++++ 8 files changed, 18 insertions(+), 19 deletions(-) diff --git a/Makefile b/Makefile index 92b4d0b..9aafe7c 100644 --- a/Makefile +++ b/Makefile @@ -232,6 +232,9 @@ evaluate_subdirs= \ # collect all object files eligible for building subdirs:=$(TOPLEVEL) $(eval $(call evaluate_subdirs)) +ifeq ($(FAILBUILD),1) +$(error cannot continue build) +endif # Eliminate duplicate mentions of source files in a class $(foreach class,$(classes),$(eval $(class)-srcs:=$(sort $($(class)-srcs)))) diff --git a/Makefile.inc b/Makefile.inc index 069bdfe..ad97363 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -105,10 +105,6 @@ endif ifeq ($(CONFIG_USE_BLOBS),y) forgetthis:=$(shell git submodule update --init --checkout 3rdparty) -else -ifeq ($(CONFIG_REQUIRES_BLOB),y) -$(error Your current configuration requires binary-only components, but you did not choose to use them) -endif endif bootblock-c-ccopts:=-D__BOOT_BLOCK__ -D__PRE_RAM__ @@ -164,6 +160,11 @@ cbfs-files-handler= \ $(if $(wildcard $(1)$($(2)-file)), \ $(eval tmp-cbfs-file:= $(wildcard $(1)$($(2)-file))), \ $(eval tmp-cbfs-file:= $($(2)-file))) \ + $(if $(strip $($(2)-required)), \ + $(if $(wildcard $(tmp-cbfs-file)),, \ + $(info This build configuration requires $($(2)-required)) \ + $(eval FAILBUILD:=1) \ + )) \ $(if $(tmp-cbfs-method), \ $(eval tmp-old-cbfs-file:=$(tmp-cbfs-file)) \ $(eval tmp-cbfs-file:=$(shell mkdir -p $(obj)/mainboard/$(MAINBOARDDIR); mktemp $(obj)/mainboard/$(MAINBOARDDIR)/cbfs-file.XXXXXX).out) \ @@ -172,7 +173,8 @@ cbfs-files-handler= \ $(eval $(2)-name:=) \ $(eval $(2)-type:=) \ $(eval $(2)-compression:=) \ - $(eval $(2)-position:=) + $(eval $(2)-position:=) \ + $(eval $(2)-required:=) ####################################################################### # a variety of flags for our build diff --git a/src/Kconfig b/src/Kconfig index 4e7957e..2dc251d 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -184,16 +184,6 @@ config USE_BLOBS might be required for some chipsets or boards. This flag ensures that a "Free" option remains available for users. -config REQUIRES_BLOB - bool - default n - help - This option can be configured by boards that require the blobs - repository for the default configuration. It will make the build - fail if USE_BLOBS is disabled. Users that still desire to do a - coreboot build for such a board can override this manually, but - this option serves as warning that it might fail. - config COVERAGE bool "Code coverage support" depends on COMPILER_GCC diff --git a/src/cpu/amd/geode_gx2/Makefile.inc b/src/cpu/amd/geode_gx2/Makefile.inc index b3f3de9..f42f1bd 100644 --- a/src/cpu/amd/geode_gx2/Makefile.inc +++ b/src/cpu/amd/geode_gx2/Makefile.inc @@ -11,3 +11,5 @@ cpu_incs += $(src)/cpu/amd/geode_gx2/cache_as_ram.inc cbfs-files-$(CONFIG_GEODE_VSA_FILE) += vsa vsa-file = $(call strip_quotes,$(CONFIG_VSA_FILENAME)):vsa vsa-type = stage +vsa-required = VSA binary + diff --git a/src/cpu/amd/geode_lx/Kconfig b/src/cpu/amd/geode_lx/Kconfig index 777dc94..7deb100 100644 --- a/src/cpu/amd/geode_lx/Kconfig +++ b/src/cpu/amd/geode_lx/Kconfig @@ -19,7 +19,6 @@ config GEODE_VSA bool default y select PCI_OPTION_ROM_RUN_REALMODE - select REQUIRES_BLOB config GEODE_VSA_FILE bool "Add a VSA image" diff --git a/src/cpu/amd/geode_lx/Makefile.inc b/src/cpu/amd/geode_lx/Makefile.inc index c9df888..29fe0aa 100644 --- a/src/cpu/amd/geode_lx/Makefile.inc +++ b/src/cpu/amd/geode_lx/Makefile.inc @@ -11,3 +11,5 @@ cpu_incs += $(src)/cpu/amd/geode_lx/cache_as_ram.inc cbfs-files-$(CONFIG_GEODE_VSA_FILE) += vsa vsa-file = $(call strip_quotes,$(CONFIG_VSA_FILENAME)):vsa vsa-type = stage +vsa-required = VSA binary + diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index 92e5960..6cbed53 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -46,21 +46,18 @@ if SOUTHBRIDGE_AMD_AGESA_HUDSON config HUDSON_XHCI_FWM bool "Add xhci firmware" default y - select REQUIRES_BLOB help Add Hudson 2/3/4 XHCI Firmware to support the onboard usb3.0 config HUDSON_IMC_FWM bool "Add imc firmware" default y - select REQUIRES_BLOB help Add Hudson 2/3/4 IMC Firmware to support the onboard fan control config HUDSON_GEC_FWM bool "Add gec firmware" default n - select REQUIRES_BLOB help Add Hudson 2/3/4 GEC Firmware diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index c9a1731..a5b1231 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -74,6 +74,7 @@ cbfs-files-y += hudson/xhci hudson/xhci-file := $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) hudson/xhci-position := $(HUDSON_XHCI_POSITION) hudson/xhci-type := raw +hudson/xhci-required := Hudson XHCI firmware endif ifeq ($(CONFIG_HUDSON_IMC_FWM), y) @@ -81,6 +82,7 @@ cbfs-files-y += hudson/imc hudson/imc-file := $(call strip_quotes, $(CONFIG_HUDSON_IMC_FWM_FILE)) hudson/imc-position := $(HUDSON_IMC_POSITION) hudson/imc-type := raw +hudson/imc-required := Hudson IMC Firmware endif ifeq ($(CONFIG_HUDSON_GEC_FWM), y) @@ -88,6 +90,7 @@ cbfs-files-y += hudson/gec hudson/gec-file := $(call strip_quotes, $(CONFIG_HUDSON_GEC_FWM_FILE)) hudson/gec-position := $(HUDSON_GEC_POSITION) hudson/gec-type := raw +hudson/gec-required := Hudson Gigabit Ethernet Controller Firmware (Contact your AMD representative) endif #ifeq ($(CONFIG_HUDSON_SATA_AHCI), y) @@ -96,5 +99,6 @@ stripped_ahci_rom_id = $(call strip_quotes,$(CONFIG_AHCI_ROM_ID)) cbfs-files-y += pci$(stripped_ahci_rom_id).rom pci$(stripped_ahci_rom_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_ROM_FILE)) pci$(stripped_ahci_rom_id).rom-type := optionrom +pci$(stripped_ahci_rom_id).rom-required := Hudson AHCI Option ROM (Contact your AMD representative) #endif endif

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coreboot February 2013