coreboot February 2013

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790 discussions

ACPI: Implementation of the _WAK method in e. g. Google Butterfly
by Paul Menzel 19 Feb '13

19 Feb '13

Dear coreboot folks, looking into the patch »Persimmon FWTS update: Fix FWTS S3 test.« [1] I read up on the ACPI `_WAK` (System Wake) method (section 7.3.7 in ACPI 4.0a specification [2]). ### Return Value: A Package containing two Integers containing status and the power supply S-state ### Return Value Information _WAK returns a package with the following format: • Element 0 – An Integer containing a bitfield that represents conditions that occurred during sleep. 0x00000000 – Wake was signaled and was successful 0x00000001 – Wake was signaled but failed due to lack of power 0x00000002 – Wake was signaled but failed due to thermal condition Other values – Reserved • Element 1 – An Integer containing the power supply S-state. If non-zero, this is the effective S-state the power supply that was actually entered. This value is used to detect when the targeted S-state was not entered because of too much current being drawn from the power supply. For example, this might occur when some active device’s current consumption pushes the system’s power requirements over the low power supply mark, thus preventing the lower power mode from being entered as desired. So first question is, what is, when Element 1 is set to 0? I was surprised to see, that the recent-Intel chip based boards like Google Parrot or Butterfly just return a package with both elements set to zero without any further checks. The AMD boards did the same(?), but according to the above patch [1] this causes issues with Ubuntu’s Firmware Test Suite [3]. $ more src/mainboard/google/butterfly/acpi/platform.asl […] /* The _WAK method is called on system wake-up */ Method(_WAK,1) { /* Update in case state changed while asleep */ /* Update AC status */ Store (\_SB.PCI0.LPCB.EC0.ADPT, Local0) if (LNotEqual (Local0, \PWRS)) { Store (Local0, \PWRS) Notify (\_SB.PCI0.LPCB.EC0.AC, 0x80) } /* Update LID status */ Store (\_SB.PCI0.LPCB.EC0.LIDF, Local0) if (LNotEqual (Local0, \LIDS)) { Store (Local0, \LIDS) Notify (\_SB.LID0, 0x80) } Return(Package(){0,0}) } If I am not mistaken that contradicts the ACPI specification. Errors during resume (Element 0) are not considered and neither is the power supply. I guess it is not deemed to be worth it to implement that. But could such assumptions (and consequences(?)) please be documented in the code? Or what am I missing? Thanks, Paul [1] http://review.coreboot.org/#/c/2444/ [2] http://www.acpi.info/spec40a.htm [3] https://wiki.ubuntu.com/Kernel/Reference/fwts/

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Patch set updated for coreboot: 3431a9c armv7: init stack to 0xdeadbeef to detect stack overflows
by David Hendricks 18 Feb '13

18 Feb '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2421 -gerrit commit 3431a9c39c8d3fab3b7f94a085545fa79251accf Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Feb 15 17:50:20 2013 -0800 armv7: init stack to 0xdeadbeef to detect stack overflows This adds a simple loop which initializes the stack to 0xdeadbeef which is used by checkstack(). Change-Id: I8aecf7bfb1067de68c4080c1fcb7eefa28fd04a7 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/bootblock.inc | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/src/arch/armv7/bootblock.inc b/src/arch/armv7/bootblock.inc index c8cfe5e..da063a6 100644 --- a/src/arch/armv7/bootblock.inc +++ b/src/arch/armv7/bootblock.inc @@ -71,6 +71,21 @@ reset: cmp r1, #0 bne wait_for_interrupt @ If this is not core0, wait + /* + * Initialize the stack to a known value. This is used to check for + * stack overflow later in the boot process. + */ + ldr r0, .Stack + ldr r1, .Stack_size + sub r0, r0, r1 + ldr r1, .Stack + ldr r2, =0xdeadbeef +init_stack_loop: + str r2, [r0] + add r0, #4 + cmp r0, r1 + bne init_stack_loop + /* Set stackpointer in internal RAM to call board_init_f */ call_bootblock: ldr sp, .Stack /* Set up stack pointer */ @@ -95,3 +110,6 @@ wait_for_interrupt: .align 2 .Stack: .word CONFIG_STACK_TOP +.align 2 +.Stack_size: + .word CONFIG_STACK_SIZE

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Patch merged into coreboot/master: 384ee9f Persimmon: drop useless DDR3 voltage code copied from Inagua
by gerrit＠coreboot.org 18 Feb '13

18 Feb '13

the following patch was just integrated into master: commit 384ee9f1429db8543724e868b7ffd5fc7e2aa915 Author: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Date: Mon Feb 18 20:26:50 2013 +0100 Persimmon: drop useless DDR3 voltage code copied from Inagua Inagua can use GPIOs 178,179 to switch VMEM to 1.5, 1.35 or 1.25 V, which it does according to data read from the SO-DIMM's SPD EEPROM. On Persimmon (according to DB-FT1 rev. D schematics) both GPIOs are unconnected, there is no way to change the 1.5 V DDR3 voltage (save unsoldering a resistor). The whole code copied over from Inagua is useless. Removed the code, instead a comment hints at Inagua, for people who do designs based on Persimmon but do have a way to change VMEM. The line ...->DDR3Voltage = VOLT1_5; is supposed to make the AGESA DDR3 code select the RAM timings for the actually supplied voltage instead of the hoped-for but unavailable lower voltage. I have no idea how to test this, but in any case it can't hurt. Change-Id: Id098e09418b665645814a6ee2d41a3bff72238ba Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Reviewed-on: http://review.coreboot.org/2448 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter(a)stuge.se> Build-Tested: build bot (Jenkins) at Mon Feb 18 20:57:47 2013, giving +1 Reviewed-By: Peter Stuge <peter(a)stuge.se> at Mon Feb 18 22:49:59 2013, giving +2 See http://review.coreboot.org/2448 for details. -gerrit

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Patch merged into coreboot/master: 9fba303 Persimmon: disable APU PCIe port 3
by gerrit＠coreboot.org 18 Feb '13

18 Feb '13

the following patch was just integrated into master: commit 9fba303435be16d5eb66ef11ed52ad71cc00c459 Author: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Date: Mon Feb 18 20:13:27 2013 +0100 Persimmon: disable APU PCIe port 3 According to DB-FT1 rev. D schematics the APU PCIe lane 3 is unconnected. Reflect this fact in the mainboard code. Change-Id: Ic98f4a63ef971628df7fbf97f56b80ebe7cb8517 Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Reviewed-on: http://review.coreboot.org/2447 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter(a)stuge.se> Build-Tested: build bot (Jenkins) at Mon Feb 18 20:29:50 2013, giving +1 Reviewed-By: Peter Stuge <peter(a)stuge.se> at Mon Feb 18 22:49:45 2013, giving +2 See http://review.coreboot.org/2447 for details. -gerrit

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Patch merged into coreboot/master: fa8702c Persimmon: adapt PCIe reset code copied from Inagua to actually match Persimmon
by gerrit＠coreboot.org 18 Feb '13

18 Feb '13

the following patch was just integrated into master: commit fa8702cf2a30f32a2d9918548276e1b7b6ec0d2a Author: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Date: Mon Feb 18 19:40:33 2013 +0100 Persimmon: adapt PCIe reset code copied from Inagua to actually match Persimmon Comparing Persimmon and Inagua schematics and Coreboot code show the PCIe reset code has been blindly copied even though it doesn't suit the Persimmon at all. The Inagua can employ GPIOs 21, 25, 02 to manually reset devices on APU PCIe lanes 0/1, 2, 3 respectively. (Appearently the motivation for this is to revive buggy PCIe gen1 devices which got confused by PCIe gen2 signal training.) However the Persimmon not only doesn't support this, it even needs these 3 pins for the PCI interface! Instead it uses GPIO50 to reset devices on lanes 0-2 all at once. Lane 3 is unconnected anyway. This patch adapts the Persimmon mainboard code according to the DB-FT1 rev. D schematics. Change-Id: I05a657d9bf8cc59acc4f5174eb20375165c860c7 Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Reviewed-on: http://review.coreboot.org/2446 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter(a)stuge.se> Build-Tested: build bot (Jenkins) at Mon Feb 18 20:20:21 2013, giving +1 Reviewed-By: Peter Stuge <peter(a)stuge.se> at Mon Feb 18 22:49:38 2013, giving +2 See http://review.coreboot.org/2446 for details. -gerrit

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coreboot 2013 Google Summer of Code: Call for mentors and project ideas
by Marc Jones 18 Feb '13

18 Feb '13

coreboot community, Google has announced the 2013 GSoC program. coreboot had been a GSoC participant in the past, but was not accepted in 2012 and we would like to change that this year. The GSoC project acceptance has become much more competitive and the project ideas and student recruitment pages has become key in getting accepted. Our project ideas were not flushed out enough in the application process and we didn't have a complete mentors list/assignment for those projects. I think that coreboot has some extremely talented people involved in the project and students should be attracted to the experience of working with our mentors as much as the potential projects. What we need to apply for GSoC 2013: Project Admins - We need a person or two to be the main liaison between coreboot and GSoC. This person(s) register the project, fills out the application, leads and organizes the projects and mentors. Mentors - We need a pool of mentors willing to support students on a number of levels; Helping them from the very beginning with project ideas and writing their applications, project and development time management, research, communication, documentation, drive deadlines. Mentor biographies - To improve out GSoC recruitment, i would like to have a one paragraph biography for each of our mentors. It should contain what your coreboot experience and contributions. Something about your work and/or education experience and maybe some other personal information. Maybe where you are located. It helps to have mentors can be matched with the students culture. Project ideas - We also need complete project ideas with pointers to background data and what the expected outcome would be. We need a list of potential mentors for each project idea. coreboot GSoC support roles - Even if you can't commit to being a full time mentor, we could use your help with the coreboot promotion, student recruitment, wiki, project ideas, blog postings, and code reviews , and encouragement and advice to students and mentors. Important dates: March18 - 29 - Org applications. We should have a list of mentors and suitable project ideas, policies, etc by this date. April 1 - 5- GSoC application review April 8 - Org acceptance April 22 - May 5 - student applications If you are interested in helping, please feel free to contact me and/or start updating the wiki and add yourself and/or project ideas. http://www.coreboot.org/GSoC Regards, Marc -- http://se-eng.com

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New patch to review for coreboot: 02a1c7b Persimmon: drop useless DDR3 voltage code copied from Inagua
by Jens Rottmann 18 Feb '13

18 Feb '13

Jens Rottmann (JRottmann(a)LiPPERTembedded.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2448 -gerrit commit 02a1c7b40fd5b41cd8360162c55e5df71c33db87 Author: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Date: Mon Feb 18 20:26:50 2013 +0100 Persimmon: drop useless DDR3 voltage code copied from Inagua Inagua can use GPIOs 178,179 to switch VMEM to 1.5, 1.35 or 1.25 V, which it does according to data read from the SO-DIMM's SPD EEPROM. On Persimmon (according to DB-FT1 rev. D schematics) both GPIOs are unconnected, there is no way to change the 1.5 V DDR3 voltage (save unsoldering a resistor). The whole code copied over from Inagua is useless. Removed the code, instead a comment hints at Inagua, for people who do designs based on Persimmon but do have a way to change VMEM. The line ...->DDR3Voltage = VOLT1_5; is supposed to make the AGESA DDR3 code select the RAM timings for the actually supplied voltage instead of the hoped-for but unavailable lower voltage. I have no idea how to test this, but in any case it can't hurt. Change-Id: Id098e09418b665645814a6ee2d41a3bff72238ba Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> --- src/mainboard/amd/persimmon/BiosCallOuts.c | 82 ++---------------------------- 1 file changed, 4 insertions(+), 78 deletions(-) diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.c b/src/mainboard/amd/persimmon/BiosCallOuts.c index 52eb9dd..b355278 100644 --- a/src/mainboard/amd/persimmon/BiosCallOuts.c +++ b/src/mainboard/amd/persimmon/BiosCallOuts.c @@ -445,84 +445,10 @@ AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPt /* Call the host environment interface to provide a user hook opportunity. */ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - AGESA_STATUS Status; - UINTN FcnData; - MEM_DATA_STRUCT *MemData; - UINT32 AcpiMmioAddr; - UINT32 GpioMmioAddr; - UINT8 Data8; - UINT16 Data16; - UINT8 TempData8; - - FcnData = Data; - MemData = ConfigPtr; - - Status = AGESA_SUCCESS; - /* Get SB MMIO Base (AcpiMmioAddr) */ - WriteIo8 (0xCD6, 0x27); - Data8 = ReadIo8(0xCD7); - Data16 = Data8<<8; - WriteIo8 (0xCD6, 0x26); - Data8 = ReadIo8(0xCD7); - Data16 |= Data8; - AcpiMmioAddr = (UINT32)Data16 << 16; - GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; - - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178); - Data8 &= ~BIT5; - TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); - TempData8 &= 0x03; - TempData8 |= Data8; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8); - - Data8 |= BIT2+BIT3; - Data8 &= ~BIT4; - TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); - TempData8 &= 0x23; - TempData8 |= Data8; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8); - - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179); - Data8 &= ~BIT5; - TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); - TempData8 &= 0x03; - TempData8 |= Data8; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8); - - Data8 |= BIT2+BIT3; - Data8 &= ~BIT4; - TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); - TempData8 &= 0x23; - TempData8 |= Data8; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8); - - switch(MemData->ParameterListPtr->DDR3Voltage){ - case VOLT1_35: - Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); - Data8 &= ~(UINT8)BIT6; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8); - Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); - Data8 |= (UINT8)BIT6; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8); - break; - case VOLT1_25: - Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); - Data8 &= ~(UINT8)BIT6; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8); - Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); - Data8 &= ~(UINT8)BIT6; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8); - break; - case VOLT1_5: - default: - Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); - Data8 |= (UINT8)BIT6; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8); - Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); - Data8 &= ~(UINT8)BIT6; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8); - } - return Status; + // Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage. + // Make sure the right speed settings are selected. + ((MEM_DATA_STRUCT*)ConfigPtr)->ParameterListPtr->DDR3Voltage = VOLT1_5; + return AGESA_SUCCESS; } /* Call the host environment interface to provide a user hook opportunity. */

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New patch to review for coreboot: 970e7cd Persimmon: disable APU PCIe port 3
by Jens Rottmann 18 Feb '13

18 Feb '13

Jens Rottmann (JRottmann(a)LiPPERTembedded.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2447 -gerrit commit 970e7cddf1d81e03569c092651c46f4f70e1cd14 Author: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Date: Mon Feb 18 20:13:27 2013 +0100 Persimmon: disable APU PCIe port 3 According to DB-FT1 rev. D schematics the APU PCIe lane 3 is unconnected. Reflect this fact in the mainboard code. Change-Id: Ic98f4a63ef971628df7fbf97f56b80ebe7cb8517 Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> --- src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h b/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h index a49be62..89334d9 100644 --- a/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h @@ -50,7 +50,7 @@ #define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced //GNB GPP Port7 -#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT7_PORT_PRESENT 0 //0:Disable 1:Enable #define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 #define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 #define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)

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AMD S3: Experiences with ACPI 2.0 method _BFS (Back From Sleep)
by Paul Menzel 18 Feb '13

18 Feb '13

Dear coreboot folks, searching for ACPI in the output of `dmesg` I noticed the following message. $ uname -v #1 SMP Debian 3.2.35-2 $ dmesg | grep -i acpi [ 0.154063] ACPI: BIOS offers _BFS [ 0.154067] ACPI: If "acpi.bfs=1" improves resume, please notify linux-acpi(a)vger.kernel.org Doing $ git grep _GTA reveals that it is only implemented in the DSDT of AMD based boards. As resuming currently does not work on the ASRock E350M1 [1], I cannot test that. Was this ever tested by adding `acpi.bfs=1` to the Linux kernel command line and what was the outcome? A test on AMD Persimmon would be very interesting. It looks like support for this has been removed in the meantime though commit 3f6f49c7854c9294119437a82c5b35be78f9cea6 Author: Len Brown <len.brown(a)intel.com> Date: Thu Jul 26 20:08:54 2012 -0400 ACPI: delete _GTS/_BFS support since Linux Git tag v3.6-rc2. Thanks, Paul [1] http://www.coreboot.org/ASRock_E350M1 [2] https://patchwork.kernel.org/patch/1246671/

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New patch to review for coreboot: 33723e7 Persimmon: adapt PCIe reset code copied from Inagua to actually match Persimmon
by Jens Rottmann 18 Feb '13

18 Feb '13

Jens Rottmann (JRottmann(a)LiPPERTembedded.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2446 -gerrit commit 33723e752be6e890e3edeb8c24f7d4d251ae90a1 Author: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Date: Mon Feb 18 19:40:33 2013 +0100 Persimmon: adapt PCIe reset code copied from Inagua to actually match Persimmon Comparing Persimmon and Inagua schematics and Coreboot code show the PCIe reset code has been blindly copied even though it doesn't suit the Persimmon at all. The Inagua can employ GPIOs 21, 25, 02 to manually reset devices on APU PCIe lanes 0/1, 2, 3 respectively. (Appearently the motivation for this is to revive buggy PCIe gen1 devices which got confused by PCIe gen2 signal training.) However the Persimmon not only doesn't support this, it even needs these 3 pins for the PCI interface! Instead it uses GPIO50 to reset devices on lanes 0-2 all at once. Lane 3 is unconnected anyway. This patch adapts the Persimmon mainboard code according to the DB-FT1 rev. D schematics. Change-Id: I05a657d9bf8cc59acc4f5174eb20375165c860c7 Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> --- src/mainboard/amd/persimmon/BiosCallOuts.c | 42 ++++----------------------- src/mainboard/amd/persimmon/BiosCallOuts.h | 11 ++----- src/mainboard/amd/persimmon/PlatformGnbPcie.c | 10 +++---- 3 files changed, 12 insertions(+), 51 deletions(-) diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.c b/src/mainboard/amd/persimmon/BiosCallOuts.c index 52eb9dd..0711d96 100644 --- a/src/mainboard/amd/persimmon/BiosCallOuts.c +++ b/src/mainboard/amd/persimmon/BiosCallOuts.c @@ -562,50 +562,18 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; switch (ResetInfo->ResetId) { - case 4: + case 46: // GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot switch (ResetInfo->ResetControl) { case AssertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); Data8 &= ~(UINT8)BIT6 ; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 + Write64Mem8(GpioMmioAddr+SB_GPIO_REG50, Data8); Status = AGESA_SUCCESS; break; case DeassertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 - Status = AGESA_SUCCESS; - break; - } - break; - case 6: - switch (ResetInfo->ResetControl) { - case AssertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); - Data8 &= ~(UINT8)BIT6 ; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 - Status = AGESA_SUCCESS; - break; - case DeassertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); - Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 - Status = AGESA_SUCCESS; - break; - } - break; - case 7: - switch (ResetInfo->ResetControl) { - case AssertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); - Data8 &= ~(UINT8)BIT6 ; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 - Status = AGESA_SUCCESS; - break; - case DeassertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); - Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG50, Data8); Status = AGESA_SUCCESS; break; } diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.h b/src/mainboard/amd/persimmon/BiosCallOuts.h index cd23110..09dc436 100644 --- a/src/mainboard/amd/persimmon/BiosCallOuts.h +++ b/src/mainboard/amd/persimmon/BiosCallOuts.h @@ -69,12 +69,7 @@ AGESA_STATUS BiosHookBeforeDramInitRecovery (UINT32 Func, UINT32 Data, VOID *Con AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr); /* PCIE slot reset control */ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -#define SB_GPIO_REG02 2 -#define SB_GPIO_REG09 9 -#define SB_GPIO_REG10 10 -#define SB_GPIO_REG15 15 -#define SB_GPIO_REG17 17 -#define SB_GPIO_REG21 21 -#define SB_GPIO_REG25 25 -#define SB_GPIO_REG28 28 + +#define SB_GPIO_REG50 50 + #endif //_BIOS_CALLOUT_H_ diff --git a/src/mainboard/amd/persimmon/PlatformGnbPcie.c b/src/mainboard/amd/persimmon/PlatformGnbPcie.c index a5b075e..f75d258 100644 --- a/src/mainboard/amd/persimmon/PlatformGnbPcie.c +++ b/src/mainboard/amd/persimmon/PlatformGnbPcie.c @@ -60,28 +60,26 @@ PCIe_PORT_DESCRIPTOR PortList [] = { { 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4) + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 46) }, - #if 1 // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) { 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 5) + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 46) }, // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) { 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6) + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 46) }, // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7) + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0) }, - #endif // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) { DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array

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coreboot February 2013