coreboot February 2013

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Patch merged into coreboot/master: 510171e Tyan S8226: Fix integer truncated warning
by gerrit＠coreboot.org 19 Feb '13

19 Feb '13

the following patch was just integrated into master: commit 510171e23bc6beaf502b0549e6ee446e47860715 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Mon Feb 18 21:42:18 2013 -0700 Tyan S8226: Fix integer truncated warning Fix Warning: sb700_cfg.c:129, GNU Compiler 4 (gcc), Priority: Normal large integer implicitly truncated to unsigned type [-Woverflow] The issue here was that an 8 bit value was being placed into a 2-bit bitfield. $ more src/vendorcode/amd/cimx/sb700/SBTYPE.h […] UINT32 AzaliaSdin0 :2; //6 UINT32 AzaliaSdin1 :2; //8 UINT32 AzaliaSdin2 :2; //10 UINT32 AzaliaSdin3 :2; //12 $ more src/mainboard/tyan/s8226/sb700_cfg.h […] * SDIN0 is define at BIT0 & BIT1 * 00 - GPIO PIN * 01 - Reserved * 10 - As a Azalia SDIN pin * SDIN1 is define at BIT2 & BIT3 * SDIN2 is define at BIT4 & BIT5 * SDIN3 is define at BIT6 & BIT7 */ #ifndef AZALIA_SDIN_PIN #define AZALIA_SDIN_PIN 0x2A #endif […] $ more src/mainboard/tyan/s8226/sb700_cfg.c […] sb_config->AzaliaSdin0 = AZALIA_SDIN_PIN; […] The 8 bit value 0x2A (binary 00 10 10 10), was being used incorrectly – I believe the original intent of this value was to enable the SDIN pins 0, 1, & 2. Because it was getting truncated as it was put into AzaliaSdin0, this wasn't happening and only SDIN0 was being enabled. I am leaving only SDIN0 enabled at this point to as not change the actual behavior on the platform. Change-Id: Icaeb956926309dbfb5af25a36ccb842877e17a34 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> Reviewed-on: http://review.coreboot.org/2452 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin(a)se-eng.com> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Tue Feb 19 12:01:31 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Tue Feb 19 23:44:48 2013, giving +2 See http://review.coreboot.org/2452 for details. -gerrit

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Patch merged into coreboot/master: ddff32e Tyan S8226: Fix printk warnings
by gerrit＠coreboot.org 19 Feb '13

19 Feb '13

the following patch was just integrated into master: commit ddff32eb8cc8271d486537a085ed64eff5de5365 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Mon Feb 18 21:33:04 2013 -0700 Tyan S8226: Fix printk warnings Fix 84 warnings all like this one: agesawrapper.c:289, GNU Compiler 4 (gcc), Priority: Normal format '%lu' expects argument of type 'long unsigned int', but argument 3 has type 'UINT32' [-Wformat] Fixed by getting rid of the l length specifier and casting to unsigned int. Change-Id: Ic143c1034f760fa5efb2220aa33861e399ddd708 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> Reviewed-on: http://review.coreboot.org/2451 Tested-by: build bot (Jenkins) Reviewed-by: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Dave Frodin <dave.frodin(a)se-eng.com> Build-Tested: build bot (Jenkins) at Tue Feb 19 05:47:44 2013, giving +1 See http://review.coreboot.org/2451 for details. -gerrit

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Patch set updated for coreboot: a20c9dd AMD SB800: don't switch clock from 14 to 48 MHz for smscsuperio
by Jens Rottmann 19 Feb '13

19 Feb '13

Jens Rottmann (JRottmann(a)LiPPERTembedded.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2454 -gerrit commit a20c9dd8ab5980f7ca55a4fb4c5c4dac4c46ee3d Author: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Date: Tue Feb 19 15:01:06 2013 +0100 AMD SB800: don't switch clock from 14 to 48 MHz for smscsuperio The power up default for 14M_25M_48M_OSC is 14 MHz. sb800/bootblock.c changes this to 48 MHz, which is the correct value for almost all SIOs. However, not for 'smscsuperio' (SMSC SCH311x), which needs the original 14 MHz. We could switch back to 14 in the mainboard's romstage.c, but then the clock frequency would change twice. This patch skips the SB800 clock switch if the SIO Kconfig requests 14 MHz. This does not affect any boards currently in the repository (yet). Change-Id: Icff41fd88dc41c08f3700ab4f786852f04eff2a4 Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> --- src/southbridge/amd/cimx/sb800/bootblock.c | 13 ++++++++++--- src/superio/Kconfig | 3 +++ src/superio/smsc/Kconfig | 1 + 3 files changed, 14 insertions(+), 3 deletions(-) diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c index 0a339b0..d9a04f0 100644 --- a/src/southbridge/amd/cimx/sb800/bootblock.c +++ b/src/southbridge/amd/cimx/sb800/bootblock.c @@ -97,10 +97,17 @@ static void enable_clocks(void) reg8 &= ~(1 << 1); outb(reg8, 0xCD7); - // Program SB800 MiscCntrl Device_CLK1_sel for 48 MHz (default is 14 MHz) + // Program SB800 MiscClkCntrl register to configure clock output on the + // 14M_25M_48M_OSC ball usually used for the Super-I/O. + // Almost all SIOs need 48 MHz, only the SMSC SCH311x wants 14 MHz, + // which is the SB800's power up default. We could switch back to 14 + // in the mainboard's romstage.c, but then the clock frequency would + // change twice. reg32 = *acpi_mmio; - reg32 &= ~((1 << 0) | (1 << 2)); - reg32 |= 1 << 1; + reg32 &= ~((1 << 2) | (3 << 0)); // enable, 14 MHz (power up default) +#ifndef CONFIG_SUPERIO_WANTS_14MHZ_CLOCK + reg32 |= 2 << 0; // Device_CLK1_sel = 48 MHz +#endif *acpi_mmio = reg32; } diff --git a/src/superio/Kconfig b/src/superio/Kconfig index 00fee97..d0ca249 100644 --- a/src/superio/Kconfig +++ b/src/superio/Kconfig @@ -17,6 +17,9 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +config SUPERIO_WANTS_14MHZ_CLOCK + bool + source src/superio/fintek/Kconfig source src/superio/intel/Kconfig source src/superio/ite/Kconfig diff --git a/src/superio/smsc/Kconfig b/src/superio/smsc/Kconfig index 8d66fc5..1a3b709 100644 --- a/src/superio/smsc/Kconfig +++ b/src/superio/smsc/Kconfig @@ -44,6 +44,7 @@ config SUPERIO_SMSC_MEC1308 bool config SUPERIO_SMSC_SMSCSUPERIO bool + select SUPERIO_WANTS_14MHZ_CLOCK config SUPERIO_SMSC_SIO1036 bool config SUPERIO_SMSC_SCH4037

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Patch merged into coreboot/master: f87855c Inagua+children: fix simple copy & paste error in code to reset PCIe slots
by gerrit＠coreboot.org 19 Feb '13

19 Feb '13

the following patch was just integrated into master: commit f87855ceab7e735221c1b85ed405a0b47e329125 Author: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Date: Mon Feb 18 18:56:48 2013 +0100 Inagua+children: fix simple copy & paste error in code to reset PCIe slots Looking at AssertSlotReset, the comments and all other case's it's obvious this is a simple copy & paste error where someone just forgot to change one occurrance of the GPIO nr. Also the AMD Inagua schematics show that GPIO02 is what they really meant. Also forward the fix to boards copied from Inagua (AMD South Station, Union Station, Asrock E350M1). Change-Id: I6b9a3d473245fa27604b2f148a730290277a88ed Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Reviewed-on: http://review.coreboot.org/2445 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter(a)stuge.se> Build-Tested: build bot (Jenkins) at Tue Feb 19 15:55:18 2013, giving +1 Reviewed-By: Peter Stuge <peter(a)stuge.se> at Tue Feb 19 19:50:33 2013, giving +2 See http://review.coreboot.org/2445 for details. -gerrit

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Patch merged into coreboot/master: 46cb96b libpayload: libcbfs: Fix legacy CBFS API, typos
by gerrit＠coreboot.org 19 Feb '13

19 Feb '13

the following patch was just integrated into master: commit 46cb96bb887c88ab0c03dc83ebd6ba107a5d908c Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Tue Feb 19 17:59:21 2013 +0100 libpayload: libcbfs: Fix legacy CBFS API, typos get_cbfs_header expects CBFS_HEADER_INVALID_ADDRESS (0xffffffff) instead of NULL when something is wrong. Also, fix typo. Change-Id: Ibe56c9eab3b9fdfc6d0b14bc848ca75f3a4fc2f1 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/2455 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter(a)stuge.se> Build-Tested: build bot (Jenkins) at Tue Feb 19 18:08:11 2013, giving +1 Reviewed-By: Peter Stuge <peter(a)stuge.se> at Tue Feb 19 19:44:57 2013, giving +2 See http://review.coreboot.org/2455 for details. -gerrit

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Patch set updated for coreboot: e685c0c AMD SB800: don't switch clock from 14 to 48 MHz for smscsuperio
by Jens Rottmann 19 Feb '13

19 Feb '13

Jens Rottmann (JRottmann(a)LiPPERTembedded.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2454 -gerrit commit e685c0cc2b4f2f69735ec5b8bdae0e0271bc02e6 Author: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Date: Tue Feb 19 15:01:06 2013 +0100 AMD SB800: don't switch clock from 14 to 48 MHz for smscsuperio The power up default for 14M_25M_48M_OSC is 14 MHz. sb800/bootblock.c changes this to 48 MHz, which is the correct value for almost all SIOs. However, not for 'smscsuperio' (SMSC SCH311x), which needs the original 14 MHz. We could switch back to 14 in the mainboard's romstage.c, but then the clock frequency would change twice. This patch skips the SB800 clock switch if the SIO is smscsuperio. This does not affect any boards currently in the repository (yet). Change-Id: Icff41fd88dc41c08f3700ab4f786852f04eff2a4 Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> --- src/southbridge/amd/cimx/sb800/bootblock.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c index 0a339b0..ac92c05 100644 --- a/src/southbridge/amd/cimx/sb800/bootblock.c +++ b/src/southbridge/amd/cimx/sb800/bootblock.c @@ -97,10 +97,17 @@ static void enable_clocks(void) reg8 &= ~(1 << 1); outb(reg8, 0xCD7); - // Program SB800 MiscCntrl Device_CLK1_sel for 48 MHz (default is 14 MHz) + // Program SB800 MiscClkCntrl register to configure clock output on the + // 14M_25M_48M_OSC ball usually used for the Super-I/O. + // Almost all SIOs need 48 MHz, only the SMSC SCH311x wants 14 MHz, + // which is the SB800's power up default. We could switch back to 14 + // in the mainboard's romstage.c, but then the clock frequency would + // change twice. reg32 = *acpi_mmio; - reg32 &= ~((1 << 0) | (1 << 2)); - reg32 |= 1 << 1; + reg32 &= ~((1 << 2) | (3 << 0)); // enable, 14 MHz (power up default) +#ifndef CONFIG_SUPERIO_SMSC_SMSCSUPERIO + reg32 |= 2 << 0; // Device_CLK1_sel = 48 MHz +#endif *acpi_mmio = reg32; }

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Patch merged into coreboot/master: 82682d5 exynos5250: add uartmem_getbaseaddr() in uart driver
by gerrit＠coreboot.org 19 Feb '13

19 Feb '13

the following patch was just integrated into master: commit 82682d50ec8d0850020a57db1911f91748811a2e Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Feb 15 19:32:01 2013 -0800 exynos5250: add uartmem_getbaseaddr() in uart driver Change-Id: I76545ad3fca3cc0997050253be77ea83b5d74cb2 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/2423 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Sat Feb 16 05:17:55 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Tue Feb 19 19:01:51 2013, giving +2 See http://review.coreboot.org/2423 for details. -gerrit

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Patch merged into coreboot/master: fdcef1a move uartmem_getbaseaddr() to generic uart header
by gerrit＠coreboot.org 19 Feb '13

19 Feb '13

the following patch was just integrated into master: commit fdcef1ace9ee75f7db50fabcf200f9e699bfbba0 Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Feb 15 19:29:12 2013 -0800 move uartmem_getbaseaddr() to generic uart header This moves uartmem_getbaseaddr() from an 8250-specific header to the generic uart header. This is to accomodate non-8250 memory-mapped UARTs. Change-Id: Id25e7dab12b33bdd928f2aa4611d720aa79f3dee Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/2422 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Sat Feb 16 05:10:03 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Tue Feb 19 19:01:29 2013, giving +2 See http://review.coreboot.org/2422 for details. -gerrit

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Patch merged into coreboot/master: 6802dc8 armv7/snow: add CPU and RAM resources via allocator
by gerrit＠coreboot.org 19 Feb '13

19 Feb '13

the following patch was just integrated into master: commit 6802dc8abe250abbe1b89532a9895b7c5d3f77f7 Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Feb 15 16:18:28 2013 -0800 armv7/snow: add CPU and RAM resources via allocator This adds necessary device operations to add CPU and RAM resources. Change-Id: Ief8f66627ef37f4fa786bfc3f7899529d3e5b037 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/2419 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Sat Feb 16 01:34:40 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Tue Feb 19 19:00:54 2013, giving +2 See http://review.coreboot.org/2419 for details. -gerrit

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New patch to review for coreboot: 51c61cd libpayload: libcbfs: Fix legacy CBFS API, typos
by Patrick Georgi 19 Feb '13

19 Feb '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2455 -gerrit commit 51c61cdd4f9a7d5d3a01d42a986564b2ccff6df8 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Tue Feb 19 17:59:21 2013 +0100 libpayload: libcbfs: Fix legacy CBFS API, typos get_cbfs_header expects CBFS_HEADER_INVALID_ADDRESS (0xffffffff) instead of NULL when something is wrong. Also, fix typo. Change-Id: Ibe56c9eab3b9fdfc6d0b14bc848ca75f3a4fc2f1 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- payloads/libpayload/libcbfs/cbfs_core.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/payloads/libpayload/libcbfs/cbfs_core.c b/payloads/libpayload/libcbfs/cbfs_core.c index 4fecd40..9bae188 100644 --- a/payloads/libpayload/libcbfs/cbfs_core.c +++ b/payloads/libpayload/libcbfs/cbfs_core.c @@ -62,8 +62,8 @@ const struct cbfs_header *cbfs_get_header(struct cbfs_media *media) if (media == CBFS_DEFAULT_MEDIA) { media = &default_media; if (init_default_cbfs_media(media) != 0) { - ERROR("Failed to initializee default media.\n"); - return NULL; + ERROR("Failed to initialize default media.\n"); + return CBFS_HEADER_INVALID_ADDRESS; } } @@ -103,7 +103,7 @@ struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name) if (media == CBFS_DEFAULT_MEDIA) { media = &default_media; if (init_default_cbfs_media(media) != 0) { - ERROR("Failed to initializee default media.\n"); + ERROR("Failed to initialize default media.\n"); return NULL; } }

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coreboot February 2013