coreboot February 2013

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New patch to review for coreboot: 5b18ca3 google/now: enable GPIO entries and CHROMEOS in building
by Ronald G. Minnich 20 Feb '13

20 Feb '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2467 -gerrit commit 5b18ca38a90a013cbe216844f3d09edb0bcc9e8e Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Wed Feb 20 15:46:46 2013 -0800 google/now: enable GPIO entries and CHROMEOS in building These were not separable or it would have been two CLs. Enable CHROMEOS on snow. Write gpio support code for the mainboard. Right now the GPIO just returns hard-wired values for "virtual" GPIOs. This is tested and creates gpio table entries that our hardware can use. Lots still missing but we can now start to fill in the blanks, since we have enabled CHROMEOS for this board. Change-Id: I5fdc68b0b76f9b2172271e991e11bef16f5adb27 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/armv7/boot/coreboot_table.c | 10 ++++------ src/arch/armv7/include/arch/coreboot_tables.h | 2 ++ src/mainboard/google/snow/Kconfig | 2 +- src/mainboard/google/snow/Makefile.inc | 1 + src/vendorcode/google/chromeos/Makefile.inc | 6 +++--- 5 files changed, 11 insertions(+), 10 deletions(-) diff --git a/src/arch/armv7/boot/coreboot_table.c b/src/arch/armv7/boot/coreboot_table.c index 2810a5e..55610ac 100644 --- a/src/arch/armv7/boot/coreboot_table.c +++ b/src/arch/armv7/boot/coreboot_table.c @@ -23,7 +23,6 @@ #include <console/console.h> #include <ip_checksum.h> #include <boot/tables.h> -#include <boot/coreboot_tables.h> #include <arch/coreboot_tables.h> #include <string.h> #include <version.h> @@ -35,7 +34,7 @@ #include <option_table.h> #endif #if CONFIG_CHROMEOS -#include <arch/acpi.h> +//#include <arch/acpi.h> #include <vendorcode/google/chromeos/gnvs.h> #endif @@ -183,11 +182,10 @@ static void lb_gpios(struct lb_header *header) struct lb_gpios *gpios; gpios = (struct lb_gpios *)lb_new_record(header); gpios->tag = LB_TAG_GPIO; - gpios->size = sizeof(*gpios); - gpios->count = 0; fill_lb_gpios(gpios); } +#if 0 static void lb_vdat(struct lb_header *header) { struct lb_vdat* vdat; @@ -209,6 +207,7 @@ static void lb_vbnv(struct lb_header *header) vbnv->vbnv_size = CONFIG_VBNV_SIZE; } #endif +#endif static void add_cbmem_pointers(struct lb_header *header) { @@ -656,12 +655,11 @@ unsigned long write_coreboot_table( lb_strings(head); /* Record our framebuffer */ lb_framebuffer(head); - -#if 0 #if CONFIG_CHROMEOS /* Record our GPIO settings (ChromeOS specific) */ lb_gpios(head); +#if 0 /* pass along the VDAT buffer adress */ lb_vdat(head); diff --git a/src/arch/armv7/include/arch/coreboot_tables.h b/src/arch/armv7/include/arch/coreboot_tables.h index ab20866..4c2a013 100644 --- a/src/arch/armv7/include/arch/coreboot_tables.h +++ b/src/arch/armv7/include/arch/coreboot_tables.h @@ -12,6 +12,8 @@ unsigned long write_coreboot_table( void lb_memory_range(struct lb_memory *mem, uint32_t type, uint64_t start, uint64_t size); +void fill_lb_gpios(struct lb_gpios *gpios); + /* Routines to extract part so the coreboot table or information * from the coreboot table. */ diff --git a/src/mainboard/google/snow/Kconfig b/src/mainboard/google/snow/Kconfig index bee987d..6face94 100644 --- a/src/mainboard/google/snow/Kconfig +++ b/src/mainboard/google/snow/Kconfig @@ -29,7 +29,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DRIVER_MAXIM_MAX77686 # select HAVE_ACPI_TABLES # select MMCONF_SUPPORT -# select CHROMEOS + select CHROMEOS config MAINBOARD_DIR string diff --git a/src/mainboard/google/snow/Makefile.inc b/src/mainboard/google/snow/Makefile.inc index b56a1a4..668e3b7 100644 --- a/src/mainboard/google/snow/Makefile.inc +++ b/src/mainboard/google/snow/Makefile.inc @@ -23,6 +23,7 @@ romstage-y += romstage.c # ramstage-y += ec.c ramstage-y += ramstage.c +ramstage-y += chromeos.c # romstage-$(CONFIG_CHROMEOS) += chromeos.c diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index 967db96..8ae14fd 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -19,9 +19,9 @@ romstage-y += chromeos.c ramstage-y += chromeos.c -romstage-y += vbnv.c -ramstage-y += vbnv.c -romstage-y += vboot.c +romstage-$(CONFIG_ARCH_X86) += vbnv.c +ramstage-$(CONFIG_ARCH_X86) += vbnv.c +romstage-$(CONFIG_ARCH_X86) += vboot.c ramstage-y += gnvs.c romstage-y += fmap.c ramstage-y += fmap.c

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Patch set updated for coreboot: 745fd21 ARMV7: create a correct LB_SERIAL table entry
by Ronald G. Minnich 20 Feb '13

20 Feb '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2466 -gerrit commit 745fd2106df5ed950e1ab05768fc2e14e6fdface Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Wed Feb 20 14:13:01 2013 -0800 ARMV7: create a correct LB_SERIAL table entry If CONFIG_CONSOLE_SERIAL is set, and we can call the standard function and get a non-zero uart address, then we create an lb table entry. The code was mostly right, just needed a tweak. Change-Id: I5b36c7b4e580a23319b7ba92cc8ad61592b1757a Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/armv7/boot/coreboot_table.c | 13 +------------ src/mainboard/emulation/qemu-armv7/Kconfig | 1 + src/mainboard/emulation/qemu-armv7/uart.c | 4 ++++ 3 files changed, 6 insertions(+), 12 deletions(-) diff --git a/src/arch/armv7/boot/coreboot_table.c b/src/arch/armv7/boot/coreboot_table.c index 044f3d5..2810a5e 100644 --- a/src/arch/armv7/boot/coreboot_table.c +++ b/src/arch/armv7/boot/coreboot_table.c @@ -110,18 +110,7 @@ static struct lb_memory *lb_memory(struct lb_header *header) static struct lb_serial *lb_serial(struct lb_header *header) { -#if CONFIG_CONSOLE_SERIAL8250 - struct lb_record *rec; - struct lb_serial *serial; - rec = lb_new_record(header); - serial = (struct lb_serial *)rec; - serial->tag = LB_TAG_SERIAL; - serial->size = sizeof(*serial); - serial->type = LB_SERIAL_TYPE_IO_MAPPED; - serial->baseaddr = CONFIG_TTYS0_BASE; - serial->baud = CONFIG_TTYS0_BAUD; - return serial; -#elif CONFIG_CONSOLE_SERIAL8250MEM +#if CONFIG_CONSOLE_SERIAL if (uartmem_getbaseaddr()) { struct lb_record *rec; struct lb_serial *serial; diff --git a/src/mainboard/emulation/qemu-armv7/Kconfig b/src/mainboard/emulation/qemu-armv7/Kconfig index 38b1da2..b66761d 100644 --- a/src/mainboard/emulation/qemu-armv7/Kconfig +++ b/src/mainboard/emulation/qemu-armv7/Kconfig @@ -25,6 +25,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_ARMV7 select CPU_ARMLTD_CORTEX_A9 + select HAVE_UART_MEMORY_MAPPED select DEFAULT_EARLY_CONSOLE select HAVE_UART_SPECIAL select BOARD_ROMSIZE_KB_4096 diff --git a/src/mainboard/emulation/qemu-armv7/uart.c b/src/mainboard/emulation/qemu-armv7/uart.c index 2988777..dfe5d0a 100644 --- a/src/mainboard/emulation/qemu-armv7/uart.c +++ b/src/mainboard/emulation/qemu-armv7/uart.c @@ -39,6 +39,10 @@ static const struct console_driver pl011_uart_console __console = { .tx_flush = pl011_uart_tx_flush, }; +uint32_t uartmem_getbaseaddr(void) +{ + return VEXPRESS_UART0_IO_ADDRESS; +} #else void uart_init(void) {

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Patch set updated for coreboot: 69b4d77 ARMV7: create a correct LB_SERIAL table entry
by Ronald G. Minnich 20 Feb '13

20 Feb '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2466 -gerrit commit 69b4d774f7546a969986ee011d57d5e294cff41c Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Wed Feb 20 14:13:01 2013 -0800 ARMV7: create a correct LB_SERIAL table entry If CONFIG_CONSOLE_SERIAL is set, and we can call the standard function and get a non-zero uart address, then we create an lb table entry. The code was mostly right, just needed a tweak. Change-Id: I5b36c7b4e580a23319b7ba92cc8ad61592b1757a Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/armv7/boot/coreboot_table.c | 13 +------------ src/mainboard/emulation/qemu-armv7/uart.c | 4 ++++ 2 files changed, 5 insertions(+), 12 deletions(-) diff --git a/src/arch/armv7/boot/coreboot_table.c b/src/arch/armv7/boot/coreboot_table.c index 044f3d5..2810a5e 100644 --- a/src/arch/armv7/boot/coreboot_table.c +++ b/src/arch/armv7/boot/coreboot_table.c @@ -110,18 +110,7 @@ static struct lb_memory *lb_memory(struct lb_header *header) static struct lb_serial *lb_serial(struct lb_header *header) { -#if CONFIG_CONSOLE_SERIAL8250 - struct lb_record *rec; - struct lb_serial *serial; - rec = lb_new_record(header); - serial = (struct lb_serial *)rec; - serial->tag = LB_TAG_SERIAL; - serial->size = sizeof(*serial); - serial->type = LB_SERIAL_TYPE_IO_MAPPED; - serial->baseaddr = CONFIG_TTYS0_BASE; - serial->baud = CONFIG_TTYS0_BAUD; - return serial; -#elif CONFIG_CONSOLE_SERIAL8250MEM +#if CONFIG_CONSOLE_SERIAL if (uartmem_getbaseaddr()) { struct lb_record *rec; struct lb_serial *serial; diff --git a/src/mainboard/emulation/qemu-armv7/uart.c b/src/mainboard/emulation/qemu-armv7/uart.c index 2988777..dfe5d0a 100644 --- a/src/mainboard/emulation/qemu-armv7/uart.c +++ b/src/mainboard/emulation/qemu-armv7/uart.c @@ -39,6 +39,10 @@ static const struct console_driver pl011_uart_console __console = { .tx_flush = pl011_uart_tx_flush, }; +uint32_t uartmem_getbaseaddr(void) +{ + return VEXPRESS_UART0_IO_ADDRESS; +} #else void uart_init(void) {

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Patch merged into coreboot/master: a8ae1c6 Whitespace: Replace tab character in license text with two spaces
by gerrit＠coreboot.org 20 Feb '13

20 Feb '13

the following patch was just integrated into master: commit a8ae1c66f919a41c8756d0cdb09a77243d1121eb Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Wed Feb 20 13:21:20 2013 +0100 Whitespace: Replace tab character in license text with two spaces For whatever reason tabs got inserted in the license header text. Remove one occurrence of that with the following command [1]. $ git grep -l 'MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.'$'\t' | xargs sed -i 's,MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.[ ]*,MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\ \ ,' [1] http://sed.sourceforge.net/grabbag/tutorials/sedfaq.txt Change-Id: Iaf4ed32c32600c3b23c08f8754815b959b304882 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2460 Tested-by: build bot (Jenkins) Reviewed-by: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Reviewed-by: Cristian Măgherușan-Stanciu <cristi.magherusan(a)gmail.com> Build-Tested: build bot (Jenkins) at Wed Feb 20 13:42:16 2013, giving +1 See http://review.coreboot.org/2460 for details. -gerrit

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Patch set updated for coreboot: d073e5e ARMV7: create a correct LB_SERIAL table entry
by Ronald G. Minnich 20 Feb '13

20 Feb '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2466 -gerrit commit d073e5ece474947833dae41188a651e5a53994b1 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Wed Feb 20 14:13:01 2013 -0800 ARMV7: create a correct LB_SERIAL table entry If CONFIG_CONSOLE_SERIAL is set, and we can call the standard function and get a non-zero uart address, then we create an lb table entry. The code was mostly right, just needed a tweak. Change-Id: I5b36c7b4e580a23319b7ba92cc8ad61592b1757a Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/armv7/boot/coreboot_table.c | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) diff --git a/src/arch/armv7/boot/coreboot_table.c b/src/arch/armv7/boot/coreboot_table.c index 044f3d5..2810a5e 100644 --- a/src/arch/armv7/boot/coreboot_table.c +++ b/src/arch/armv7/boot/coreboot_table.c @@ -110,18 +110,7 @@ static struct lb_memory *lb_memory(struct lb_header *header) static struct lb_serial *lb_serial(struct lb_header *header) { -#if CONFIG_CONSOLE_SERIAL8250 - struct lb_record *rec; - struct lb_serial *serial; - rec = lb_new_record(header); - serial = (struct lb_serial *)rec; - serial->tag = LB_TAG_SERIAL; - serial->size = sizeof(*serial); - serial->type = LB_SERIAL_TYPE_IO_MAPPED; - serial->baseaddr = CONFIG_TTYS0_BASE; - serial->baud = CONFIG_TTYS0_BAUD; - return serial; -#elif CONFIG_CONSOLE_SERIAL8250MEM +#if CONFIG_CONSOLE_SERIAL if (uartmem_getbaseaddr()) { struct lb_record *rec; struct lb_serial *serial;

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New patch to review for coreboot: 6a83bf3 RMV7: create a correct LB_SERIAL table entry
by Ronald G. Minnich 20 Feb '13

20 Feb '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2466 -gerrit commit 6a83bf3f1b2ca4c8caa451b79f45c1cb81684e64 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Wed Feb 20 14:13:01 2013 -0800 RMV7: create a correct LB_SERIAL table entry If CONFIG_CONSOLE_SERIAL is set, and we can call the standard function and get a non-zero uart address, then we create an lb table entry. The code was mostly right, just needed a tweak. Change-Id: I5b36c7b4e580a23319b7ba92cc8ad61592b1757a Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/armv7/boot/coreboot_table.c | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) diff --git a/src/arch/armv7/boot/coreboot_table.c b/src/arch/armv7/boot/coreboot_table.c index 044f3d5..2810a5e 100644 --- a/src/arch/armv7/boot/coreboot_table.c +++ b/src/arch/armv7/boot/coreboot_table.c @@ -110,18 +110,7 @@ static struct lb_memory *lb_memory(struct lb_header *header) static struct lb_serial *lb_serial(struct lb_header *header) { -#if CONFIG_CONSOLE_SERIAL8250 - struct lb_record *rec; - struct lb_serial *serial; - rec = lb_new_record(header); - serial = (struct lb_serial *)rec; - serial->tag = LB_TAG_SERIAL; - serial->size = sizeof(*serial); - serial->type = LB_SERIAL_TYPE_IO_MAPPED; - serial->baseaddr = CONFIG_TTYS0_BASE; - serial->baud = CONFIG_TTYS0_BAUD; - return serial; -#elif CONFIG_CONSOLE_SERIAL8250MEM +#if CONFIG_CONSOLE_SERIAL if (uartmem_getbaseaddr()) { struct lb_record *rec; struct lb_serial *serial;

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Patch merged into coreboot/master: 7d75fbd Persimmon: Replace tab with space in address in license header
by gerrit＠coreboot.org 20 Feb '13

20 Feb '13

the following patch was just integrated into master: commit 7d75fbd223d097886dd441acb2ef0f7a4c3db36f Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Wed Feb 20 13:40:14 2013 +0100 Persimmon: Replace tab with space in address in license header The following commit was too eager replacing spaces with tabs. commit 36abff1dc8e74beafa47ad83de17416681970916 Author: Marc Jones <marcj303(a)gmail.com> Date: Mon Nov 7 23:26:14 2011 -0700 Cleanup Persimmon mainboard whitespace. Reviewed-on: http://review.coreboot.org/427 Fix that with the following command. $ git grep -l 'Floor, Boston, MA'$'\t''02110-1301 USA' | xargs sed -i 's/Boston, MA[ ]*02110-1301 USA/Boston, MA 02110-1301 USA/' Change-Id: Ia118a8c19d94ce1f1048280a0f1d49d447cfa2a7 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2461 Tested-by: build bot (Jenkins) Reviewed-by: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Reviewed-by: Cristian Măgherușan-Stanciu <cristi.magherusan(a)gmail.com> Build-Tested: build bot (Jenkins) at Wed Feb 20 14:00:02 2013, giving +1 See http://review.coreboot.org/2461 for details. -gerrit

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Patch merged into coreboot/master: 836fd19 armv7: Don't let users set ram parameters that are fixed in hardware.
by gerrit＠coreboot.org 20 Feb '13

20 Feb '13

the following patch was just integrated into master: commit 836fd19aa812388ba78de7c330f7c0bd1b6788a8 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Wed Feb 20 13:24:35 2013 -0800 armv7: Don't let users set ram parameters that are fixed in hardware. The SDRAM base is fixed in hardware. It makes no sense to make it configurable. The TEXT start is a magic number that should also be fixed, not settable. Change-Id: Ie44cc5c8da1dc38fc00eb602c4a295b045ca5364 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-on: http://review.coreboot.org/2465 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Wed Feb 20 22:33:47 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Wed Feb 20 23:13:41 2013, giving +2 See http://review.coreboot.org/2465 for details. -gerrit

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New patch to review for coreboot: 5827eb8 armv7: Don't let users set ram parameters that are fixed in hardware.
by Ronald G. Minnich 20 Feb '13

20 Feb '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2465 -gerrit commit 5827eb80a3f784c998042db411967cbf7009f08f Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Wed Feb 20 13:24:35 2013 -0800 armv7: Don't let users set ram parameters that are fixed in hardware. The SDRAM base is fixed in hardware. It makes no sense to make it configurable. The TEXT start is a magic number that should also be fixed, not settable. Change-Id: Ie44cc5c8da1dc38fc00eb602c4a295b045ca5364 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/cpu/samsung/exynos5250/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig index 1b8b23f..ca306b6 100644 --- a/src/cpu/samsung/exynos5250/Kconfig +++ b/src/cpu/samsung/exynos5250/Kconfig @@ -87,11 +87,11 @@ config XIP_ROM_SIZE default ROMSTAGE_SIZE config SYS_SDRAM_BASE - hex "SDRAM base address" + hex default 0x40000000 config SYS_TEXT_BASE - hex "Executable code section" + hex default 0x43e00000 config COREBOOT_TABLES_SIZE

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Patch set updated for coreboot: d9ab1b5 Persimmon, Inagua: PCI devs 12.1, 13.1 (USB) don't exist, but 14.6 (GEC) does
by Paul Menzel 20 Feb '13

20 Feb '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2463 -gerrit commit d9ab1b5d6ab02e2d92e314217a3e275f929ce23e Author: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Date: Wed Feb 20 21:12:37 2013 +0100 Persimmon, Inagua: PCI devs 12.1, 13.1 (USB) don't exist, but 14.6 (GEC) does USB ports 0-4 are handled by PCI devices 12.0 (OHCI) and 12.2 (EHCI). 12.1 simply does not exist, so remove it from devicetree.cb. While at it make the comment more detailed. Likewise for all USB ports. USB device 14.6 is the Broadcom GbE MAC integrated in the Hudson-E1. Add it to devicetree.cb. It's used on Inagua (on), but not on Persimmon (off). Change-Id: Idea27b3390fa4470f2592e79fdd633d5a218b97b Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> --- src/mainboard/amd/inagua/devicetree.cb | 17 ++++++++--------- src/mainboard/amd/persimmon/devicetree.cb | 17 ++++++++--------- 2 files changed, 16 insertions(+), 18 deletions(-) diff --git a/src/mainboard/amd/inagua/devicetree.cb b/src/mainboard/amd/inagua/devicetree.cb index f003704..6ce73bb 100644 --- a/src/mainboard/amd/inagua/devicetree.cb +++ b/src/mainboard/amd/inagua/devicetree.cb @@ -39,12 +39,10 @@ chip northbridge/amd/agesa/family14/root_complex chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.1 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.1 on end # USB - device pci 13.2 on end # USB + device pci 12.0 on end # OHCI USB 0-4 + device pci 12.2 on end # EHCI USB 0-4 + device pci 13.0 on end # OHCI USB 5-9 + device pci 13.2 on end # EHCI USB 5-9 device pci 14.0 on # SM chip drivers/generic/generic #dimm 0-0-0 device i2c 50 on end @@ -66,13 +64,14 @@ chip northbridge/amd/agesa/family14/root_complex end # kbc1100 end #LPC device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} - device pci 14.5 on end # USB 2 + device pci 14.5 on end # OHCI FS/LS USB + device pci 14.6 on end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699) device pci 15.0 on end # PCIe PortA Express Card device pci 15.1 on end # PCIe PortB NEC USB3.0 device pci 15.2 on end # PCIe PortC MINIPCIE SLOT2 device pci 15.3 on end # PCIe PortD PCIE X1 SLOT - device pci 16.0 on end # OHCI USB3 - device pci 16.2 on end # EHCI USB3 + device pci 16.0 on end # OHCI USB 10-13 + device pci 16.2 on end # EHCI USB 10-13 register "gpp_configuration" = "4" #1:1:1:1 register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE end #southbridge/amd/cimx/sb800 diff --git a/src/mainboard/amd/persimmon/devicetree.cb b/src/mainboard/amd/persimmon/devicetree.cb index fce7d10..196327c 100644 --- a/src/mainboard/amd/persimmon/devicetree.cb +++ b/src/mainboard/amd/persimmon/devicetree.cb @@ -39,12 +39,10 @@ chip northbridge/amd/agesa/family14/root_complex chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.1 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.1 on end # USB - device pci 13.2 on end # USB + device pci 12.0 on end # OHCI USB 0-4 + device pci 12.2 on end # EHCI USB 0-4 + device pci 13.0 on end # OHCI USB 5-9 + device pci 13.2 on end # EHCI USB 5-9 device pci 14.0 on # SM chip drivers/generic/generic #dimm 0-0-0 device i2c 50 on end @@ -82,13 +80,14 @@ chip northbridge/amd/agesa/family14/root_complex end # f81865f end #LPC device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} - device pci 14.5 off end # USB 2 + device pci 14.5 off end # OHCI FS/LS USB + device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699) device pci 15.0 off end # PCIe PortA device pci 15.1 off end # PCIe PortB device pci 15.2 off end # PCIe PortC device pci 15.3 off end # PCIe PortD - device pci 16.0 off end # OHCI USB3 - device pci 16.2 off end # EHCI USB3 + device pci 16.0 off end # OHCI USB 10-13 + device pci 16.2 off end # EHCI USB 10-13 register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow) register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE

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coreboot February 2013