coreboot February 2013

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New patch to review for coreboot: 3de5255 Persimmon: dimmSpd.c: Use spaces for alignment of if-predicate
by Paul Menzel 21 Feb '13

21 Feb '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2471 -gerrit commit 3de525502e8e92c4556d1dc9957b5e5f218aa97b Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu Feb 21 14:01:39 2013 +0100 Persimmon: dimmSpd.c: Use spaces for alignment of if-predicate The relational operators in the if-predicate are aligned in all `dimmSpd.c` files so revert part of the change in commit 36abff1dc8e74beafa47ad83de17416681970916 Author: Marc Jones <marcj303(a)gmail.com> Date: Mon Nov 7 23:26:14 2011 -0700 Cleanup Persimmon mainboard whitespace. Reviewed-on: http://review.coreboot.org/427 to remove the incorrectly introduced tabs and to unify that. It might contradict the current coding style but it is even used in the latest code as seen in the following file. src/northbridge/amd/agesa/family15tn/dimmSpd.c Change-Id: Ib611267f99090d0830bdc2319527389f193ea1eb Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/amd/persimmon/dimmSpd.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mainboard/amd/persimmon/dimmSpd.c b/src/mainboard/amd/persimmon/dimmSpd.c index 4aaa682..a021cc2 100644 --- a/src/mainboard/amd/persimmon/dimmSpd.c +++ b/src/mainboard/amd/persimmon/dimmSpd.c @@ -152,9 +152,9 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA { int spdAddress, ioBase; - if (info->SocketId >= DIMENSION (spdAddressLookup )) return AGESA_ERROR; - if (info->MemChannelId >= DIMENSION (spdAddressLookup[0] )) return AGESA_ERROR; - if (info->DimmId >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR; + if (info->SocketId >= DIMENSION (spdAddressLookup )) return AGESA_ERROR; + if (info->MemChannelId >= DIMENSION (spdAddressLookup[0] )) return AGESA_ERROR; + if (info->DimmId >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR; spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId]; if (spdAddress == 0) return AGESA_ERROR;

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New patch to review for coreboot: 9ce97ea AMD Fam14 boards: Unify `acpi_table.c` by mainly using Inagua’s one
by Paul Menzel 21 Feb '13

21 Feb '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2470 -gerrit commit 9ce97ea510141247ab63f5b1948331fa1039ac1c Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu Feb 21 13:10:24 2013 +0100 AMD Fam14 boards: Unify `acpi_table.c` by mainly using Inagua’s one There were just whitespace differences and three boards did not contain printk(BIOS_DEBUG, "alib\n"); dump_mem(ssdt, ((void *)alib) + alib->length); which is enclosed `#if DUMP_ACPI_TABLES == 1` to dump the ACPI tables. Basically the whitespace in the license header in Inagua’s file was fixed and then the file copied over to the other directories. Change-Id: I23f73acad427b5ec14cf51651af67240871f7488 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/amd/inagua/acpi_tables.c | 2 +- src/mainboard/amd/persimmon/acpi_tables.c | 12 ++++++------ src/mainboard/amd/south_station/acpi_tables.c | 7 +++++-- src/mainboard/amd/union_station/acpi_tables.c | 7 +++++-- src/mainboard/asrock/e350m1/acpi_tables.c | 7 +++++-- 5 files changed, 22 insertions(+), 13 deletions(-) diff --git a/src/mainboard/amd/inagua/acpi_tables.c b/src/mainboard/amd/inagua/acpi_tables.c index 0b8732a..43ee9c9 100644 --- a/src/mainboard/amd/inagua/acpi_tables.c +++ b/src/mainboard/amd/inagua/acpi_tables.c @@ -14,7 +14,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <console/console.h> diff --git a/src/mainboard/amd/persimmon/acpi_tables.c b/src/mainboard/amd/persimmon/acpi_tables.c index 81936da..43ee9c9 100644 --- a/src/mainboard/amd/persimmon/acpi_tables.c +++ b/src/mainboard/amd/persimmon/acpi_tables.c @@ -14,7 +14,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <console/console.h> @@ -39,10 +39,10 @@ static void dump_mem(u32 start, u32 end) u32 i; print_debug("dump_mem:"); for (i = start; i < end; i++) { - if ((i & 0xf) == 0) { - printk(BIOS_DEBUG, "\n%08x:", i); - } - printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i)); + if ((i & 0xf) == 0) { + printk(BIOS_DEBUG, "\n%08x:", i); + } + printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i)); } print_debug("\n"); } @@ -86,7 +86,7 @@ unsigned long acpi_fill_madt(unsigned long current) /* Write SB800 IOAPIC, only one */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - CONFIG_MAX_CPUS, IO_APIC_ADDR, 0); + CONFIG_MAX_CPUS, IO_APIC_ADDR, 0); current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 0); diff --git a/src/mainboard/amd/south_station/acpi_tables.c b/src/mainboard/amd/south_station/acpi_tables.c index 92da9fc..43ee9c9 100644 --- a/src/mainboard/amd/south_station/acpi_tables.c +++ b/src/mainboard/amd/south_station/acpi_tables.c @@ -14,7 +14,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <console/console.h> @@ -86,7 +86,7 @@ unsigned long acpi_fill_madt(unsigned long current) /* Write SB800 IOAPIC, only one */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - CONFIG_MAX_CPUS, IO_APIC_ADDR, 0); + CONFIG_MAX_CPUS, IO_APIC_ADDR, 0); current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 0); @@ -300,6 +300,9 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "slit\n"); dump_mem(slit, ((void *)slit) + slit->header.length); + printk(BIOS_DEBUG, "alib\n"); + dump_mem(ssdt, ((void *)alib) + alib->length); + printk(BIOS_DEBUG, "ssdt\n"); dump_mem(ssdt, ((void *)ssdt) + ssdt->length); diff --git a/src/mainboard/amd/union_station/acpi_tables.c b/src/mainboard/amd/union_station/acpi_tables.c index 92da9fc..43ee9c9 100644 --- a/src/mainboard/amd/union_station/acpi_tables.c +++ b/src/mainboard/amd/union_station/acpi_tables.c @@ -14,7 +14,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <console/console.h> @@ -86,7 +86,7 @@ unsigned long acpi_fill_madt(unsigned long current) /* Write SB800 IOAPIC, only one */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - CONFIG_MAX_CPUS, IO_APIC_ADDR, 0); + CONFIG_MAX_CPUS, IO_APIC_ADDR, 0); current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 0); @@ -300,6 +300,9 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "slit\n"); dump_mem(slit, ((void *)slit) + slit->header.length); + printk(BIOS_DEBUG, "alib\n"); + dump_mem(ssdt, ((void *)alib) + alib->length); + printk(BIOS_DEBUG, "ssdt\n"); dump_mem(ssdt, ((void *)ssdt) + ssdt->length); diff --git a/src/mainboard/asrock/e350m1/acpi_tables.c b/src/mainboard/asrock/e350m1/acpi_tables.c index 92da9fc..43ee9c9 100644 --- a/src/mainboard/asrock/e350m1/acpi_tables.c +++ b/src/mainboard/asrock/e350m1/acpi_tables.c @@ -14,7 +14,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <console/console.h> @@ -86,7 +86,7 @@ unsigned long acpi_fill_madt(unsigned long current) /* Write SB800 IOAPIC, only one */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - CONFIG_MAX_CPUS, IO_APIC_ADDR, 0); + CONFIG_MAX_CPUS, IO_APIC_ADDR, 0); current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 0); @@ -300,6 +300,9 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "slit\n"); dump_mem(slit, ((void *)slit) + slit->header.length); + printk(BIOS_DEBUG, "alib\n"); + dump_mem(ssdt, ((void *)alib) + alib->length); + printk(BIOS_DEBUG, "ssdt\n"); dump_mem(ssdt, ((void *)ssdt) + ssdt->length);

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New patch to review for coreboot: ccf74f6 ASRock E350M1: Unify `dimmSpd.c` with the one from Persimmon
by Paul Menzel 21 Feb '13

21 Feb '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2469 -gerrit commit ccf74f677f47a1d3924080904659ee961fc86427 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Wed Feb 20 12:42:46 2013 +0100 ASRock E350M1: Unify `dimmSpd.c` with the one from Persimmon The whitespace cleanup in the following commit was not done the ASRock E350M1. commit 36abff1dc8e74beafa47ad83de17416681970916 Author: Marc Jones <marcj303(a)gmail.com> Date: Mon Nov 7 23:26:14 2011 -0700 Cleanup Persimmon mainboard whitespace. Reviewed-on: http://review.coreboot.org/427 Do this now for `dimmSpd.c`. $ diff --suppress-common-lines -U0 src/mainboard/asrock/e350m1/dimmSpd.c src/mainboard/amd/persimmon/dimmSpd.c | grep ^- | wc -l 106 $ diff -u -w src/mainboard/asrock/e350m1/dimmSpd.c src/mainboard/amd/persimmon/dimmSpd.c --- src/mainboard/asrock/e350m1/dimmSpd.c 2013-02-20 12:05:15.096240632 +0100 +++ src/mainboard/amd/persimmon/dimmSpd.c 2013-02-20 12:05:15.084240614 +0100 @@ -35,7 +35,7 @@ { // socket 0 { - {0xA0, 0xA4}, // channel 0 dimms + {0xA0, 0xA2}, // channel 0 dimms {0x00, 0x00}, // channel 1 dimms }, // socket 1 @@ -65,8 +65,7 @@ // time limit to avoid hanging for unexpected error status (should never happen) limit = __rdtsc () + 2000000000 / 10; - for (;;) - { + for (;;) { status = __inbyte (iobase); if (__rdtsc () > limit) break; if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting @@ -95,8 +94,7 @@ // time limit to avoid hanging for unexpected error status limit = __rdtsc () + 2000000000 / 10; - for (;;) - { + for (;;) { status = __inbyte (iobase); if (__rdtsc () > limit) break; if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting @@ -127,8 +125,7 @@ if (error) return error; /* read the remaining bytes using auto-increment for speed */ - for (index = 1; index < count; index++) - { + for (index = 1; index < count; index++) { error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]); if (error) return error; } After: $ diff -u -w src/mainboard/asrock/e350m1/dimmSpd.c src/mainboard/amd/persimmon/dimmSpd.c --- src/mainboard/asrock/e350m1/dimmSpd.c 2013-02-20 14:04:44.002009899 +0100 +++ src/mainboard/amd/persimmon/dimmSpd.c 2013-02-20 13:56:49.633790834 +0100 @@ -35,7 +35,7 @@ { // socket 0 { - {0xA0, 0xA4}, // channel 0 dimms + {0xA0, 0xA2}, // channel 0 dimms {0x00, 0x00}, // channel 1 dimms }, // socket 1 Change-Id: Iecb146895a266fd62995ddb7ac716343d7bde26d Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/asrock/e350m1/dimmSpd.c | 207 +++++++++++++++++----------------- 1 file changed, 102 insertions(+), 105 deletions(-) diff --git a/src/mainboard/asrock/e350m1/dimmSpd.c b/src/mainboard/asrock/e350m1/dimmSpd.c index 62aedd2..7883a4a 100644 --- a/src/mainboard/asrock/e350m1/dimmSpd.c +++ b/src/mainboard/asrock/e350m1/dimmSpd.c @@ -14,7 +14,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include "Porting.h" @@ -31,19 +31,19 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA * SPD address table - porting required */ -static const UINT8 spdAddressLookup [2] [2] [4] = // socket, channel, dimm - { - // socket 0 - { - {0xA0, 0xA4}, // channel 0 dimms - {0x00, 0x00}, // channel 1 dimms - }, - // socket 1 - { - {0x00, 0x00}, // channel 0 dimms - {0x00, 0x00}, // channel 1 dimms - }, - }; +static const UINT8 spdAddressLookup [2] [2] [4] = // socket, channel, dimm +{ + // socket 0 + { + {0xA0, 0xA4}, // channel 0 dimms + {0x00, 0x00}, // channel 1 dimms + }, + // socket 1 + { + {0x00, 0x00}, // channel 0 dimms + {0x00, 0x00}, // channel 1 dimms + }, +}; /*----------------------------------------------------------------------------- * @@ -51,117 +51,114 @@ static const UINT8 spdAddressLookup [2] [2] [4] = // socket, channel, dimm */ static int readSmbusByteData (int iobase, int address, char *buffer, int offset) - { - unsigned int status; - UINT64 limit; - - address |= 1; // set read bit - - __outbyte (iobase + 0, 0xFF); // clear error status - __outbyte (iobase + 1, 0x1F); // clear error status - __outbyte (iobase + 3, offset); // offset in eeprom - __outbyte (iobase + 4, address); // slave address and read bit - __outbyte (iobase + 2, 0x48); // read byte command - - // time limit to avoid hanging for unexpected error status (should never happen) - limit = __rdtsc () + 2000000000 / 10; - for (;;) - { - status = __inbyte (iobase); - if (__rdtsc () > limit) break; - if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting - if ((status & 1) == 1) continue; // HostBusy set, keep waiting - break; - } - - buffer [0] = __inbyte (iobase + 5); - if (status == 2) status = 0; // check for done with no errors - return status; - } +{ + unsigned int status; + UINT64 limit; + + address |= 1; // set read bit + + __outbyte (iobase + 0, 0xFF); // clear error status + __outbyte (iobase + 1, 0x1F); // clear error status + __outbyte (iobase + 3, offset); // offset in eeprom + __outbyte (iobase + 4, address); // slave address and read bit + __outbyte (iobase + 2, 0x48); // read byte command + + // time limit to avoid hanging for unexpected error status (should never happen) + limit = __rdtsc () + 2000000000 / 10; + for (;;) { + status = __inbyte (iobase); + if (__rdtsc () > limit) break; + if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting + if ((status & 1) == 1) continue; // HostBusy set, keep waiting + break; + } + + buffer [0] = __inbyte (iobase + 5); + if (status == 2) status = 0; // check for done with no errors + return status; +} /*----------------------------------------------------------------------------- * * readSmbusByte - read a single SPD byte from the default offset - * this function is faster function readSmbusByteData + * this function is faster function readSmbusByteData */ static int readSmbusByte (int iobase, int address, char *buffer) - { - unsigned int status; - UINT64 limit; - - __outbyte (iobase + 0, 0xFF); // clear error status - __outbyte (iobase + 2, 0x44); // read command - - // time limit to avoid hanging for unexpected error status - limit = __rdtsc () + 2000000000 / 10; - for (;;) - { - status = __inbyte (iobase); - if (__rdtsc () > limit) break; - if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting - if ((status & 1) == 1) continue; // HostBusy set, keep waiting - break; - } - - buffer [0] = __inbyte (iobase + 5); - if (status == 2) status = 0; // check for done with no errors - return status; - } +{ + unsigned int status; + UINT64 limit; + + __outbyte (iobase + 0, 0xFF); // clear error status + __outbyte (iobase + 2, 0x44); // read command + + // time limit to avoid hanging for unexpected error status + limit = __rdtsc () + 2000000000 / 10; + for (;;) { + status = __inbyte (iobase); + if (__rdtsc () > limit) break; + if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting + if ((status & 1) == 1) continue; // HostBusy set, keep waiting + break; + } + + buffer [0] = __inbyte (iobase + 5); + if (status == 2) status = 0; // check for done with no errors + return status; +} /*--------------------------------------------------------------------------- * * readspd - Read one or more SPD bytes from a DIMM. - * Start with offset zero and read sequentially. - * Optimization relies on autoincrement to avoid - * sending offset for every byte. - * Reads 128 bytes in 7-8 ms at 400 KHz. + * Start with offset zero and read sequentially. + * Optimization relies on autoincrement to avoid + * sending offset for every byte. + * Reads 128 bytes in 7-8 ms at 400 KHz. */ static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count) - { - int index, error; +{ + int index, error; - /* read the first byte using offset zero */ - error = readSmbusByteData (iobase, SmbusSlaveAddress, buffer, 0); - if (error) return error; + /* read the first byte using offset zero */ + error = readSmbusByteData (iobase, SmbusSlaveAddress, buffer, 0); + if (error) return error; - /* read the remaining bytes using auto-increment for speed */ - for (index = 1; index < count; index++) - { - error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]); - if (error) return error; - } + /* read the remaining bytes using auto-increment for speed */ + for (index = 1; index < count; index++) { + error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]); + if (error) return error; + } - return 0; - } + return 0; +} static void writePmReg (int reg, int data) - { - __outbyte (0xCD6, reg); - __outbyte (0xCD7, data); - } + { + __outbyte (0xCD6, reg); + __outbyte (0xCD7, data); + } static void setupFch (int ioBase) - { - writePmReg (0x2D, ioBase >> 8); - writePmReg (0x2C, ioBase | 1); - writePmReg (0x29, 0x80); - writePmReg (0x28, 0x61); - __outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz - } +{ + writePmReg (0x2D, ioBase >> 8); + writePmReg (0x2C, ioBase | 1); + writePmReg (0x29, 0x80); + writePmReg (0x28, 0x61); + __outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz +} AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info) - { - int spdAddress, ioBase; - - if (info->SocketId >= DIMENSION (spdAddressLookup )) return AGESA_ERROR; - if (info->MemChannelId >= DIMENSION (spdAddressLookup[0] )) return AGESA_ERROR; - if (info->DimmId >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR; - - spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId]; - if (spdAddress == 0) return AGESA_ERROR; - ioBase = SMBUS0_BASE_ADDRESS; - setupFch (ioBase); - return readspd (ioBase, spdAddress, (void *) info->Buffer, 128); - } +{ + int spdAddress, ioBase; + + if (info->SocketId >= DIMENSION (spdAddressLookup )) return AGESA_ERROR; + if (info->MemChannelId >= DIMENSION (spdAddressLookup[0] )) return AGESA_ERROR; + if (info->DimmId >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR; + + spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId]; + if (spdAddress == 0) return AGESA_ERROR; + ioBase = SMBUS0_BASE_ADDRESS; + setupFch (ioBase); + return readspd (ioBase, spdAddress, (void *) info->Buffer, 128); +}

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Patch merged into coreboot/master: cec4cfd Persimmon: Indent comment
by gerrit＠coreboot.org 21 Feb '13

21 Feb '13

the following patch was just integrated into master: commit cec4cfdb138dc87d2ef69d330d659e75636b51c7 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Wed Feb 20 12:45:01 2013 +0100 Persimmon: Indent comment This was overlooked in the following commit. commit 36abff1dc8e74beafa47ad83de17416681970916 Author: Marc Jones <marcj303(a)gmail.com> Date: Mon Nov 7 23:26:14 2011 -0700 Cleanup Persimmon mainboard whitespace. Reviewed-on: http://review.coreboot.org/427 Change-Id: If6bf4836b46077614a04c1e106c241a4f97da166 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2468 Tested-by: build bot (Jenkins) Reviewed-by: Alvaro G. <andor(a)pierdelacabeza.com> Build-Tested: build bot (Jenkins) at Thu Feb 21 11:41:37 2013, giving +1 Reviewed-By: Paul Menzel <paulepanter(a)users.sourceforge.net> at Thu Feb 21 12:08:51 2013, giving +2 See http://review.coreboot.org/2468 for details. -gerrit

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Patch merged into coreboot/master: df729d7 AMD Fam14 boards: dimmSpd.c: Set `iobase` to `SMBUS0_BASE_ADDRESS` instead of `0xB00`
by gerrit＠coreboot.org 21 Feb '13

21 Feb '13

the following patch was just integrated into master: commit df729d7778a7e5878fac5545883f68e42372456a Author: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Date: Tue Feb 19 14:46:31 2013 +0100 AMD Fam14 boards: dimmSpd.c: Set `iobase` to `SMBUS0_BASE_ADDRESS` instead of `0xB00` For AMD Inagua, the following two commits commit 01f7ab93359ae0fee5784d35effbcbe0b596df18 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Thu Jan 19 13:18:36 2012 +0800 Inagua: Synchronize AMD/inagua mainboard. Reviewed-on: http://review.coreboot.org/542 and commit d91c9b7e3cb9fdaeb9399a21907996130f3120bb Author: efdesign98 <efdesign98(a)gmail.com> Date: Thu Sep 15 10:59:55 2011 -0600 AMD Inagua platform updates Reviewed-on: http://review.coreboot.org/136 replaced the constant `iobase` is set to by the define `SMBUS0_BASE_ADDRESS` from `OEM.h`. Do the same for AMD Persimmon, South Station, Union station and ASRock E350M1. Change-Id: If095cd9d9b28b118b4072c7c9d345bf620b774c9 Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2453 Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Wed Feb 20 11:31:35 2013, giving +1 Reviewed-By: Paul Menzel <paulepanter(a)users.sourceforge.net> at Thu Feb 21 12:01:35 2013, giving +2 See http://review.coreboot.org/2453 for details. -gerrit

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New patch to review for coreboot: dc1d220 Persimmon: Indent comment
by Paul Menzel 21 Feb '13

21 Feb '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2468 -gerrit commit dc1d2203fdf03ceab2203a5ace0996783db614e8 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Wed Feb 20 12:45:01 2013 +0100 Persimmon: Indent comment This was overlooked in the following commit. commit 36abff1dc8e74beafa47ad83de17416681970916 Author: Marc Jones <marcj303(a)gmail.com> Date: Mon Nov 7 23:26:14 2011 -0700 Cleanup Persimmon mainboard whitespace. Reviewed-on: http://review.coreboot.org/427 Change-Id: If6bf4836b46077614a04c1e106c241a4f97da166 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/amd/persimmon/dimmSpd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/amd/persimmon/dimmSpd.c b/src/mainboard/amd/persimmon/dimmSpd.c index fb85d39..c95aea8 100644 --- a/src/mainboard/amd/persimmon/dimmSpd.c +++ b/src/mainboard/amd/persimmon/dimmSpd.c @@ -32,7 +32,7 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA static const UINT8 spdAddressLookup [2] [2] [4] = // socket, channel, dimm { -// socket 0 + // socket 0 { {0xA0, 0xA2}, // channel 0 dimms {0x00, 0x00}, // channel 1 dimms

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Some questions about SeaBIOS's native VGA drivers.
by Denis 'GNUtoo' Carikli 21 Feb '13

21 Feb '13

Hi, I'd like to replace the lenovo x60(supported by coreboot) non-free VGA option rom: I don't use it right now but that has serious drawbacks: * No graphics at all until the i915 kernel module is loaded (really user unfriendly), my main motivation to replace it... * No backlight control * nvramtool doesn't work anymore without using the -y option (not really important). I've created stub in SeaBIOS(there is an attached patch for that) for the i915 driver(it will be filled in later), however I don't know how to run the code: * I guess it creates an option rom that is in out/vgabios.bin and that I've to include it trough one of the various ways(let seabios pick it, run it in coreboot, run it in coreboot trough YABEL for debugging etc...)? right? romheaders seem to think that the option rom is valid(more on it later). I guess YABEL also thinks it's valid. I guess SeaBIOS out/bios.bin.elf doesn't link that option rom inside SeaBIOS... * it doesn't print a thing, I've CONFIG_DEBUG_LEVEL=2 and there is the following in the driver stub: dprintf(1, "i915vga_setup: VGA init...\n"); So I've tried the YABEL way with debugging enabled and here's the result: [...] Normal boot. PCI: 00:02.0 init CBFS: Looking for 'pci8086,27a2.rom' starting from 0x0. CBFS: (unmatched file @0x0: cmos_layout.bin) CBFS: (unmatched file @0x640: fallback/romstage) CBFS: (unmatched file @0xb500: fallback/coreboot_ram) CBFS: (unmatched file @0x2d200: fallback/payload) CBFS: (unmatched file @0x39a80: config) CBFS: (unmatched file @0x3a9c0: ) CBFS: (unmatched file @0x3ff80: normal/romstage) CBFS: (unmatched file @0x4ae80: normal/coreboot_ram) CBFS: (unmatched file @0x6cb80: normal/payload) CBFS: Found file (offset=0x79af8, len=33280). In CBFS, ROM address for PCI: 00:02.0 = ffe79af8 PCI expansion ROM, signature 0xaa55, INIT size 0x8200, data ptr 0x4930 PCI ROM image, vendor ID 8086, device ID 27a2, PCI ROM image, Class Code 030000, Code Type 00 Copying VGA ROM Image from ffe79af8 to 0xc0000, 0x8200 bytes [long wait] PCI: 00:02.1 init CBFS: Looking for 'cmos_layout.bin' starting from 0x0. CBFS: Found file (offset=0x28, len=1560). PCI: 00:1b.0 init [...] It doesn't seem to print a thing...and YABEL is pretty silent and should really not be that silent according to the YABEL debug options: CONFIG_X86EMU_DEBUG=y CONFIG_X86EMU_DEBUG_JMP=y # CONFIG_X86EMU_DEBUG_TRACE is not set CONFIG_X86EMU_DEBUG_PNP=y CONFIG_X86EMU_DEBUG_DISK=y CONFIG_X86EMU_DEBUG_PMM=y CONFIG_X86EMU_DEBUG_VBE=y CONFIG_X86EMU_DEBUG_INT10=y CONFIG_X86EMU_DEBUG_INTERRUPTS=y CONFIG_X86EMU_DEBUG_CHECK_VMEM_ACCESS=y CONFIG_X86EMU_DEBUG_MEM=y CONFIG_X86EMU_DEBUG_IO=y Denis.

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Patch merged into coreboot/master: 22ec9f9 AMD S3: Introduce Kconfig variable 'S3_DATA_SIZE'
by gerrit＠coreboot.org 21 Feb '13

21 Feb '13

the following patch was just integrated into master: commit 22ec9f9a72955d2364061db72520b85602077414 Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Mon Feb 18 16:56:09 2013 +0800 AMD S3: Introduce Kconfig variable 'S3_DATA_SIZE' Currently the size of the volatile storage for S3 reserved in the image is hardcoded to 32768 bytes. Make that configurable by introducing the Kconfig 'S3_DATA_SIZE'. As the storage space is needed for storing non-volatile, volatile and MTRR data, add a check if the size is big enough. Change-Id: I9152797cf0045c8da48109a9d760e417717686db Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: http://review.coreboot.org/2383 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Build-Tested: build bot (Jenkins) at Wed Feb 20 05:34:12 2013, giving +1 Reviewed-By: Zheng Bao <zheng.bao(a)amd.com> at Thu Feb 21 05:57:11 2013, giving +2 See http://review.coreboot.org/2383 for details. -gerrit

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Patch set updated for coreboot: 9811262 google/now: enable GPIO entries and CHROMEOS in building
by Ronald G. Minnich 20 Feb '13

20 Feb '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2467 -gerrit commit 9811262ffee3d6d774eb61f607ab1e59b247715d Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Wed Feb 20 15:46:46 2013 -0800 google/now: enable GPIO entries and CHROMEOS in building These were not separable or it would have been two CLs. Enable CHROMEOS on snow. Write gpio support code for the mainboard. Right now the GPIO just returns hard-wired values for "virtual" GPIOs. This is tested and creates gpio table entries that our hardware can use. Lots still missing but we can now start to fill in the blanks, since we have enabled CHROMEOS for this board. Change-Id: I5fdc68b0b76f9b2172271e991e11bef16f5adb27 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/armv7/boot/coreboot_table.c | 10 ++++------ src/arch/armv7/include/arch/coreboot_tables.h | 2 ++ src/mainboard/google/snow/Kconfig | 2 +- src/mainboard/google/snow/Makefile.inc | 1 + src/vendorcode/google/chromeos/Makefile.inc | 6 +++--- 5 files changed, 11 insertions(+), 10 deletions(-) diff --git a/src/arch/armv7/boot/coreboot_table.c b/src/arch/armv7/boot/coreboot_table.c index 2810a5e..55610ac 100644 --- a/src/arch/armv7/boot/coreboot_table.c +++ b/src/arch/armv7/boot/coreboot_table.c @@ -23,7 +23,6 @@ #include <console/console.h> #include <ip_checksum.h> #include <boot/tables.h> -#include <boot/coreboot_tables.h> #include <arch/coreboot_tables.h> #include <string.h> #include <version.h> @@ -35,7 +34,7 @@ #include <option_table.h> #endif #if CONFIG_CHROMEOS -#include <arch/acpi.h> +//#include <arch/acpi.h> #include <vendorcode/google/chromeos/gnvs.h> #endif @@ -183,11 +182,10 @@ static void lb_gpios(struct lb_header *header) struct lb_gpios *gpios; gpios = (struct lb_gpios *)lb_new_record(header); gpios->tag = LB_TAG_GPIO; - gpios->size = sizeof(*gpios); - gpios->count = 0; fill_lb_gpios(gpios); } +#if 0 static void lb_vdat(struct lb_header *header) { struct lb_vdat* vdat; @@ -209,6 +207,7 @@ static void lb_vbnv(struct lb_header *header) vbnv->vbnv_size = CONFIG_VBNV_SIZE; } #endif +#endif static void add_cbmem_pointers(struct lb_header *header) { @@ -656,12 +655,11 @@ unsigned long write_coreboot_table( lb_strings(head); /* Record our framebuffer */ lb_framebuffer(head); - -#if 0 #if CONFIG_CHROMEOS /* Record our GPIO settings (ChromeOS specific) */ lb_gpios(head); +#if 0 /* pass along the VDAT buffer adress */ lb_vdat(head); diff --git a/src/arch/armv7/include/arch/coreboot_tables.h b/src/arch/armv7/include/arch/coreboot_tables.h index ab20866..4c2a013 100644 --- a/src/arch/armv7/include/arch/coreboot_tables.h +++ b/src/arch/armv7/include/arch/coreboot_tables.h @@ -12,6 +12,8 @@ unsigned long write_coreboot_table( void lb_memory_range(struct lb_memory *mem, uint32_t type, uint64_t start, uint64_t size); +void fill_lb_gpios(struct lb_gpios *gpios); + /* Routines to extract part so the coreboot table or information * from the coreboot table. */ diff --git a/src/mainboard/google/snow/Kconfig b/src/mainboard/google/snow/Kconfig index bee987d..6face94 100644 --- a/src/mainboard/google/snow/Kconfig +++ b/src/mainboard/google/snow/Kconfig @@ -29,7 +29,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DRIVER_MAXIM_MAX77686 # select HAVE_ACPI_TABLES # select MMCONF_SUPPORT -# select CHROMEOS + select CHROMEOS config MAINBOARD_DIR string diff --git a/src/mainboard/google/snow/Makefile.inc b/src/mainboard/google/snow/Makefile.inc index b56a1a4..668e3b7 100644 --- a/src/mainboard/google/snow/Makefile.inc +++ b/src/mainboard/google/snow/Makefile.inc @@ -23,6 +23,7 @@ romstage-y += romstage.c # ramstage-y += ec.c ramstage-y += ramstage.c +ramstage-y += chromeos.c # romstage-$(CONFIG_CHROMEOS) += chromeos.c diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index 967db96..8ae14fd 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -19,9 +19,9 @@ romstage-y += chromeos.c ramstage-y += chromeos.c -romstage-y += vbnv.c -ramstage-y += vbnv.c -romstage-y += vboot.c +romstage-$(CONFIG_ARCH_X86) += vbnv.c +ramstage-$(CONFIG_ARCH_X86) += vbnv.c +romstage-$(CONFIG_ARCH_X86) += vboot.c ramstage-y += gnvs.c romstage-y += fmap.c ramstage-y += fmap.c

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Patch merged into coreboot/master: c8fadd9 ARMV7: create a correct LB_SERIAL table entry
by gerrit＠coreboot.org 20 Feb '13

20 Feb '13

the following patch was just integrated into master: commit c8fadd9f465428cb2470d78c72b77766acb058d9 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Wed Feb 20 14:13:01 2013 -0800 ARMV7: create a correct LB_SERIAL table entry If CONFIG_CONSOLE_SERIAL is set, and we can call the standard function and get a non-zero uart address, then we create an lb table entry. The code was mostly right, just needed a tweak. Change-Id: I5b36c7b4e580a23319b7ba92cc8ad61592b1757a Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-on: http://review.coreboot.org/2466 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Build-Tested: build bot (Jenkins) at Thu Feb 21 00:52:07 2013, giving +1 Reviewed-By: David Hendricks <dhendrix(a)chromium.org> at Thu Feb 21 01:05:30 2013, giving +2 See http://review.coreboot.org/2466 for details. -gerrit

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coreboot February 2013