coreboot February 2013

coreboot@coreboot.org

27 participants
790 discussions

New patch to review for coreboot: 52e3ac4 AMD/Persimmon: Add RTC init to CIMX SB800
by Mike Loptien 22 Feb '13

22 Feb '13

Mike Loptien (mike.loptien(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2488 -gerrit commit 52e3ac4bacae29ca444c9f750e133774b0b5aa2a Author: Mike Loptien <mike.loptien(a)se-eng.com> Date: Fri Feb 22 13:18:31 2013 -0700 AMD/Persimmon: Add RTC init to CIMX SB800 Adding RTC init code to the Southbridge initialization code in 'late.c'. This initializes the RTC so that the Date Alarm register is set to a valid value (0x00) at startup. By setting the Date Alarm register to 0x00, it does not get evaluated along with the seconds, minutes, and hours when running fwts s3. This was tested on a Persimmon but will apply to other mainboards as well. Change-Id: I9a11bc3f9e3f53c46e7a4d72e62ebb0a4ba1bfe4 Signed-off-by: Mike Loptien <mike.loptien(a)se-eng.com> --- src/southbridge/amd/cimx/sb800/late.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index ef3a34b..0d9b5ef 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -128,6 +128,13 @@ static void lpc_init(device_t dev) rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY); + /* Initialize the real time clock. + * The 0 argument tells rtc_init not to + * update CMOS unless it is invalid. + * 1 tells rtc_init to always initialize the CMOS. + */ + rtc_init(0); + printk(BIOS_DEBUG, "SB800 - Late.c - lpc_init - End.\n"); }

1 0

Patch set updated for coreboot: 8ec0db8 AMD Fam14 boards: Set P_BLK length to 6 for all processors
by Paul Menzel 22 Feb '13

22 Feb '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2189 -gerrit commit 8ec0db849fa195c187280d25815a9389164ce724 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Mon Jan 21 18:43:12 2013 +0100 AMD Fam14 boards: Set P_BLK length to 6 for all processors Currently on for example on AMD Persimmon and ASRock E350M1 Linux complains, that the PBLK length is invalid [1]. ACPI: Invalid PBLK length [0] Consequently, frequency scaling might not work correctly, though for these two boards it seems to work according to PowerTOP. Indeed, according to the ACPI specification [2], setting PBlockLength to 0 is only allowed if there is no PBlockAddress. Otherwise it has to be set to 6. 18.5.93 Processor (Declare Processor) […] PBlockAddress provides the system I/O address for the processors register block. Each processor can supply a different such address. PBlockLength is the length of the processor register block, in bytes and is either 0 (for no P_BLK) or 6. With one exception, all processors are required to have the same PBlockLength. The exception is that the boot processor can have a non-zero PBlockLength when all other processors have a zero PBlockLength. It is valid for every processor to have a PBlockLength of 0. And that is exactly what Linux is checking in `drivers/acpi/processor_driver.c` [3]. static int acpi_processor_get_info(struct acpi_device *device) { […] /* * On some boxes several processors use the same processor bus id. * But they are located in different scope. For example: * \_SB.SCK0.CPU0 * \_SB.SCK1.CPU0 * Rename the processor device bus id. And the new bus id will be * generated as the following format: * CPU+CPU ID. */ sprintf(acpi_device_bid(device), "CPU%X", pr->id); ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Processor [%d:%d]\n", pr->id, pr->acpi_id)); if (!object.processor.pblk_address) ACPI_DEBUG_PRINT((ACPI_DB_INFO, "No PBLK (NULL address)\n")); else if (object.processor.pblk_length != 6) printk(KERN_ERR PREFIX "Invalid PBLK length [%d]\n", object.processor.pblk_length); else { pr->throttling.address = object.processor.pblk_address; pr->throttling.duty_offset = acpi_gbl_FADT.duty_offset; pr->throttling.duty_width = acpi_gbl_FADT.duty_width; pr->pblk = object.processor.pblk_address; /* * We don't care about error returns - we just try to mark * these reserved so that nobody else is confused into thinking * that this region might be unused.. * * (In particular, allocating the IO range for Cardbus) */ request_region(pr->throttling.address, 6, "ACPI CPU throttle"); } […] } This issue has proliferated to all AMD based boards so fix it for all of them by setting P_BLK length to 6. The DSDT of for example AMD Parmer and AMD Thatcher also set it to 6 everywhere so this solution is taken instead of setting the P_BLK system I/O base to 0 for all but the first processor which is how it is done for earlier AMD based boards. As note having to set this manually should not be needed and this should be autogenerated as done for most of the Intel boards and the AMD K8 based boards (`src/cpu/amd/model_fxx/powernow_acpi.c`). [1] http://www.coreboot.org/pipermail/coreboot/2013-January/073636.html [2] http://acpi.info/DOWNLOADS/ACPIspec40a.pdf [3] http://git.kernel.org/?p=linux/kernel/git/torvalds/linux.git;a=blob;f=drive… Tested-by: Paul Menzel <paulepanter(a)users.sourceforge.net> • ASRock E350M1: Tested-by: Paul Menzel <paulepanter(a)users.sourceforge.net> • AMD Persimmon: Tested-by: Martin Roth <martin.roth(a)se-eng.com> Change-Id: Ie79fe4812532d124cc81747c75a4f3d88d00531c Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/amd/dinar/dsdt.asl | 14 +++++++------- src/mainboard/amd/inagua/dsdt.asl | 6 +++--- src/mainboard/amd/persimmon/dsdt.asl | 6 +++--- src/mainboard/amd/south_station/dsdt.asl | 6 +++--- src/mainboard/amd/torpedo/dsdt.asl | 6 +++--- src/mainboard/amd/union_station/dsdt.asl | 6 +++--- src/mainboard/asrock/e350m1/dsdt.asl | 6 +++--- 7 files changed, 25 insertions(+), 25 deletions(-) diff --git a/src/mainboard/amd/dinar/dsdt.asl b/src/mainboard/amd/dinar/dsdt.asl index 7df090f..0611fd3 100644 --- a/src/mainboard/amd/dinar/dsdt.asl +++ b/src/mainboard/amd/dinar/dsdt.asl @@ -61,49 +61,49 @@ DefinitionBlock ( C001, /* name space name */ 1, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ - 0x0 /* PBLKLEN for boot processor */ + 0x06 /* PBLKLEN for boot processor */ ) { } Processor( C002, /* name space name */ 2, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ + 0x06 /* PBLKLEN for boot processor */ ) { } Processor( C003, /* name space name */ 3, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ + 0x06 /* PBLKLEN for boot processor */ ) { } Processor( C004, /* name space name */ 4, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ + 0x06 /* PBLKLEN for boot processor */ ) { } Processor( C005, /* name space name */ 5, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ + 0x06 /* PBLKLEN for boot processor */ ) { } Processor( C006, /* name space name */ 6, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ + 0x06 /* PBLKLEN for boot processor */ ) { } Processor( C007, /* name space name */ 7, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ + 0x06 /* PBLKLEN for boot processor */ ) { } } /* End _PR scope */ diff --git a/src/mainboard/amd/inagua/dsdt.asl b/src/mainboard/amd/inagua/dsdt.asl index 46b92f1..819bb32 100644 --- a/src/mainboard/amd/inagua/dsdt.asl +++ b/src/mainboard/amd/inagua/dsdt.asl @@ -75,21 +75,21 @@ DefinitionBlock ( C001, /* name space name */ 1, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ + 0x06 /* PBLKLEN for boot processor */ ) { } Processor( C002, /* name space name */ 2, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ + 0x06 /* PBLKLEN for boot processor */ ) { } Processor( C003, /* name space name */ 3, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ + 0x06 /* PBLKLEN for boot processor */ ) { } } /* End _PR scope */ diff --git a/src/mainboard/amd/persimmon/dsdt.asl b/src/mainboard/amd/persimmon/dsdt.asl index dd7b4b1..22c0295 100644 --- a/src/mainboard/amd/persimmon/dsdt.asl +++ b/src/mainboard/amd/persimmon/dsdt.asl @@ -75,21 +75,21 @@ DefinitionBlock ( C001, /* name space name */ 1, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ + 0x06 /* PBLKLEN for boot processor */ ) { } Processor( C002, /* name space name */ 2, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ + 0x06 /* PBLKLEN for boot processor */ ) { } Processor( C003, /* name space name */ 3, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ + 0x06 /* PBLKLEN for boot processor */ ) { } } /* End _PR scope */ diff --git a/src/mainboard/amd/south_station/dsdt.asl b/src/mainboard/amd/south_station/dsdt.asl index 958295b..77e1aab 100644 --- a/src/mainboard/amd/south_station/dsdt.asl +++ b/src/mainboard/amd/south_station/dsdt.asl @@ -75,21 +75,21 @@ DefinitionBlock ( C001, /* name space name */ 1, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ + 0x06 /* PBLKLEN for boot processor */ ) { } Processor( C002, /* name space name */ 2, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ + 0x06 /* PBLKLEN for boot processor */ ) { } Processor( C003, /* name space name */ 3, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ + 0x06 /* PBLKLEN for boot processor */ ) { } } /* End _PR scope */ diff --git a/src/mainboard/amd/torpedo/dsdt.asl b/src/mainboard/amd/torpedo/dsdt.asl index 61ceca0..17e0deb 100755 --- a/src/mainboard/amd/torpedo/dsdt.asl +++ b/src/mainboard/amd/torpedo/dsdt.asl @@ -61,21 +61,21 @@ DefinitionBlock ( C001, /* name space name */ 1, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ + 0x06 /* PBLKLEN for boot processor */ ) { } Processor( C002, /* name space name */ 2, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ + 0x06 /* PBLKLEN for boot processor */ ) { } Processor( C003, /* name space name */ 3, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ + 0x06 /* PBLKLEN for boot processor */ ) { } } /* End _PR scope */ diff --git a/src/mainboard/amd/union_station/dsdt.asl b/src/mainboard/amd/union_station/dsdt.asl index 0752640..818cc18 100644 --- a/src/mainboard/amd/union_station/dsdt.asl +++ b/src/mainboard/amd/union_station/dsdt.asl @@ -75,21 +75,21 @@ DefinitionBlock ( C001, /* name space name */ 1, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ + 0x06 /* PBLKLEN for boot processor */ ) { } Processor( C002, /* name space name */ 2, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ + 0x06 /* PBLKLEN for boot processor */ ) { } Processor( C003, /* name space name */ 3, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ + 0x06 /* PBLKLEN for boot processor */ ) { } } /* End _PR scope */ diff --git a/src/mainboard/asrock/e350m1/dsdt.asl b/src/mainboard/asrock/e350m1/dsdt.asl index 1cd88b8..e34f161 100644 --- a/src/mainboard/asrock/e350m1/dsdt.asl +++ b/src/mainboard/asrock/e350m1/dsdt.asl @@ -75,21 +75,21 @@ DefinitionBlock ( C001, /* name space name */ 1, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ + 0x06 /* PBLKLEN for boot processor */ ) { } Processor( C002, /* name space name */ 2, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ + 0x06 /* PBLKLEN for boot processor */ ) { } Processor( C003, /* name space name */ 3, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ + 0x06 /* PBLKLEN for boot processor */ ) { } } /* End _PR scope */

1 0

Patch set updated for coreboot: 615a10b AMD/Persimmon: Add RTC init to CIMX SB800
by Mike Loptien 22 Feb '13

22 Feb '13

Mike Loptien (mike.loptien(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2444 -gerrit commit 615a10be4efd0213cd6383506e4c63adf309031d Author: Mike Loptien <mike.loptien(a)se-eng.com> Date: Fri Feb 22 13:18:31 2013 -0700 AMD/Persimmon: Add RTC init to CIMX SB800 Adding RTC init code to the Southbridge initialization code in 'late.c'. This initializes the RTC so that the Date Alarm register is set to a valid value (0x00) at startup. By setting the Date Alarm register to 0x00, it does not get evaluated along with the seconds, minutes, and hours when running fwts s3. This was tested on a Persimmon but will apply to other mainboards as well. Change-Id: Ica01572c23efa6d1c0fc422b5b2abf1b0f6eba71 Signed-off-by: Mike Loptien <mike.loptien(a)se-eng.com> --- src/southbridge/amd/cimx/sb800/late.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index ef3a34b..0d9b5ef 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -128,6 +128,13 @@ static void lpc_init(device_t dev) rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY); + /* Initialize the real time clock. + * The 0 argument tells rtc_init not to + * update CMOS unless it is invalid. + * 1 tells rtc_init to always initialize the CMOS. + */ + rtc_init(0); + printk(BIOS_DEBUG, "SB800 - Late.c - lpc_init - End.\n"); }

1 0

New patch to review for coreboot: 7520e4a */acpi_tables.c: Use ALIGN macro
by Patrick Georgi 22 Feb '13

22 Feb '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2487 -gerrit commit 7520e4a6f817f15af9e5e942e2f15dd8ceffdbb5 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Fri Feb 22 20:19:20 2013 +0100 */acpi_tables.c: Use ALIGN macro At the request of Paul Menzel, I reran an old classic of a coccinelle script: @@ expression E; @@ -(E + 7) & -8 +ALIGN(E, 8) @@ expression E; @@ -(E + 15) & -16 +ALIGN(E, 16) Change-Id: I01da31b241585e361380f75aacf3deddb13d11c3 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/mainboard/amd/parmer/acpi_tables.c | 24 ++++++++++++------------ src/mainboard/amd/thatcher/acpi_tables.c | 24 ++++++++++++------------ src/mainboard/google/butterfly/acpi_tables.c | 2 +- src/mainboard/google/parrot/acpi_tables.c | 2 +- src/mainboard/supermicro/h8scm/acpi_tables.c | 16 ++++++++-------- src/mainboard/tyan/s8226/acpi_tables.c | 16 ++++++++-------- 6 files changed, 42 insertions(+), 42 deletions(-) diff --git a/src/mainboard/amd/parmer/acpi_tables.c b/src/mainboard/amd/parmer/acpi_tables.c index 0cdea2d..550d477 100644 --- a/src/mainboard/amd/parmer/acpi_tables.c +++ b/src/mainboard/amd/parmer/acpi_tables.c @@ -155,7 +155,7 @@ unsigned long write_acpi_tables(unsigned long start) get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ /* Align ACPI tables to 16 bytes */ - start = (start + 0x0f) & -0x10; + start = ALIGN(start, 16); current = start; printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); @@ -173,7 +173,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_write_rsdt(rsdt); /* DSDT */ - current = (current + 0x07) & -0x08; + current = ALIGN(current, 8); printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); dsdt = (acpi_header_t *)current; /* it will used by fadt */ memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); @@ -182,14 +182,14 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); /* FACS */ /* it needs 64 bit alignment */ - current = (current + 0x07) & -0x08; + current = ALIGN(current, 8); printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); facs = (acpi_facs_t *) current; /* it will be used by fadt */ current += sizeof(acpi_facs_t); acpi_create_facs(facs); /* FADT */ - current = (current + 0x07) & -0x08; + current = ALIGN(current, 8); printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); fadt = (acpi_fadt_t *) current; current += sizeof(acpi_fadt_t); @@ -200,7 +200,7 @@ unsigned long write_acpi_tables(unsigned long start) /* * We explicitly add these tables later on: */ - current = (current + 0x07) & -0x08; + current = ALIGN(current, 8); printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); hpet = (acpi_hpet_t *) current; current += sizeof(acpi_hpet_t); @@ -208,7 +208,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, hpet); /* If we want to use HPET Timers Linux wants an MADT */ - current = (current + 0x07) & -0x08; + current = ALIGN(current, 8); printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); madt = (acpi_madt_t *) current; acpi_create_madt(madt); @@ -216,13 +216,13 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, madt); /* HEST */ - current = (current + 0x07) & -0x08; + current = ALIGN(current, 8); hest = (acpi_hest_t *)current; acpi_write_hest((void *)current); acpi_add_table(rsdp, (void *)current); current += ((acpi_header_t *)current)->length; - current = (current + 0x07) & -0x08; + current = ALIGN(current, 8); printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current); ivrs = agesawrapper_getlateinitptr(PICK_IVRS); if (ivrs != NULL) { @@ -235,7 +235,7 @@ unsigned long write_acpi_tables(unsigned long start) } /* SRAT */ - current = (current + 0x07) & -0x08; + current = ALIGN(current, 8); printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); if (srat != NULL) { @@ -248,7 +248,7 @@ unsigned long write_acpi_tables(unsigned long start) } /* SLIT */ - current = (current + 0x07) & -0x08; + current = ALIGN(current, 8); printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); if (slit != NULL) { @@ -261,7 +261,7 @@ unsigned long write_acpi_tables(unsigned long start) } /* ALIB */ - current = (current + 0x0f) & -0x10; + current = ALIGN(current, 16); printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { @@ -276,7 +276,7 @@ unsigned long write_acpi_tables(unsigned long start) /* this pstate ssdt may cause Blue Screen: Fixed: Keep this comment for a while. */ /* SSDT */ - current = ( current + 0x0f) & -0x10; + current = ALIGN(current, 16); printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); if (ssdt != NULL) { diff --git a/src/mainboard/amd/thatcher/acpi_tables.c b/src/mainboard/amd/thatcher/acpi_tables.c index 0cdea2d..550d477 100644 --- a/src/mainboard/amd/thatcher/acpi_tables.c +++ b/src/mainboard/amd/thatcher/acpi_tables.c @@ -155,7 +155,7 @@ unsigned long write_acpi_tables(unsigned long start) get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ /* Align ACPI tables to 16 bytes */ - start = (start + 0x0f) & -0x10; + start = ALIGN(start, 16); current = start; printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); @@ -173,7 +173,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_write_rsdt(rsdt); /* DSDT */ - current = (current + 0x07) & -0x08; + current = ALIGN(current, 8); printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); dsdt = (acpi_header_t *)current; /* it will used by fadt */ memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); @@ -182,14 +182,14 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); /* FACS */ /* it needs 64 bit alignment */ - current = (current + 0x07) & -0x08; + current = ALIGN(current, 8); printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); facs = (acpi_facs_t *) current; /* it will be used by fadt */ current += sizeof(acpi_facs_t); acpi_create_facs(facs); /* FADT */ - current = (current + 0x07) & -0x08; + current = ALIGN(current, 8); printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); fadt = (acpi_fadt_t *) current; current += sizeof(acpi_fadt_t); @@ -200,7 +200,7 @@ unsigned long write_acpi_tables(unsigned long start) /* * We explicitly add these tables later on: */ - current = (current + 0x07) & -0x08; + current = ALIGN(current, 8); printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); hpet = (acpi_hpet_t *) current; current += sizeof(acpi_hpet_t); @@ -208,7 +208,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, hpet); /* If we want to use HPET Timers Linux wants an MADT */ - current = (current + 0x07) & -0x08; + current = ALIGN(current, 8); printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); madt = (acpi_madt_t *) current; acpi_create_madt(madt); @@ -216,13 +216,13 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, madt); /* HEST */ - current = (current + 0x07) & -0x08; + current = ALIGN(current, 8); hest = (acpi_hest_t *)current; acpi_write_hest((void *)current); acpi_add_table(rsdp, (void *)current); current += ((acpi_header_t *)current)->length; - current = (current + 0x07) & -0x08; + current = ALIGN(current, 8); printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current); ivrs = agesawrapper_getlateinitptr(PICK_IVRS); if (ivrs != NULL) { @@ -235,7 +235,7 @@ unsigned long write_acpi_tables(unsigned long start) } /* SRAT */ - current = (current + 0x07) & -0x08; + current = ALIGN(current, 8); printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); if (srat != NULL) { @@ -248,7 +248,7 @@ unsigned long write_acpi_tables(unsigned long start) } /* SLIT */ - current = (current + 0x07) & -0x08; + current = ALIGN(current, 8); printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); if (slit != NULL) { @@ -261,7 +261,7 @@ unsigned long write_acpi_tables(unsigned long start) } /* ALIB */ - current = (current + 0x0f) & -0x10; + current = ALIGN(current, 16); printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { @@ -276,7 +276,7 @@ unsigned long write_acpi_tables(unsigned long start) /* this pstate ssdt may cause Blue Screen: Fixed: Keep this comment for a while. */ /* SSDT */ - current = ( current + 0x0f) & -0x10; + current = ALIGN(current, 16); printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); if (ssdt != NULL) { diff --git a/src/mainboard/google/butterfly/acpi_tables.c b/src/mainboard/google/butterfly/acpi_tables.c index ca4f949..95b45db 100644 --- a/src/mainboard/google/butterfly/acpi_tables.c +++ b/src/mainboard/google/butterfly/acpi_tables.c @@ -130,7 +130,7 @@ unsigned long acpi_fill_srat(unsigned long current) return current; } -#define ALIGN_CURRENT current = ((current + 0x0f) & -0x10) +#define ALIGN_CURRENT current = (ALIGN(current, 16)) unsigned long write_acpi_tables(unsigned long start) { unsigned long current; diff --git a/src/mainboard/google/parrot/acpi_tables.c b/src/mainboard/google/parrot/acpi_tables.c index 8308c01..45a9948 100644 --- a/src/mainboard/google/parrot/acpi_tables.c +++ b/src/mainboard/google/parrot/acpi_tables.c @@ -127,7 +127,7 @@ unsigned long acpi_fill_srat(unsigned long current) return current; } -#define ALIGN_CURRENT current = ((current + 0x0f) & -0x10) +#define ALIGN_CURRENT current = (ALIGN(current, 16)) unsigned long write_acpi_tables(unsigned long start) { unsigned long current; diff --git a/src/mainboard/supermicro/h8scm/acpi_tables.c b/src/mainboard/supermicro/h8scm/acpi_tables.c index 6f10a00..7a1dd58 100644 --- a/src/mainboard/supermicro/h8scm/acpi_tables.c +++ b/src/mainboard/supermicro/h8scm/acpi_tables.c @@ -176,7 +176,7 @@ unsigned long write_acpi_tables(unsigned long start) get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ /* Align ACPI tables to 16 bytes */ - start = (start + 0x0f) & -0x10; + start = ALIGN(start, 16); current = start; printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); @@ -218,7 +218,7 @@ unsigned long write_acpi_tables(unsigned long start) * We explicitly add these tables later on: */ #ifdef UNUSED_CODE // Don't need HPET table. we have one in dsdt - current = ( current + 0x07) & -0x08; + current = ALIGN(current, 8); printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); hpet = (acpi_hpet_t *) current; current += sizeof(acpi_hpet_t); @@ -227,7 +227,7 @@ unsigned long write_acpi_tables(unsigned long start) #endif /* If we want to use HPET Timers Linux wants an MADT */ - current = ( current + 0x07) & -0x08; + current = ALIGN(current, 8); printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); madt = (acpi_madt_t *) current; acpi_create_madt(madt); @@ -235,7 +235,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, madt); /* SRAT */ - current = ( current + 0x07) & -0x08; + current = ALIGN(current, 8); printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); if (srat != NULL) { @@ -247,7 +247,7 @@ unsigned long write_acpi_tables(unsigned long start) } /* SLIT */ - current = ( current + 0x07) & -0x08; + current = ALIGN(current, 8); printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); if (slit != NULL) { @@ -259,7 +259,7 @@ unsigned long write_acpi_tables(unsigned long start) } /* SSDT */ - current = (current + 0x0f) & -0x10; + current = ALIGN(current, 16); printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { @@ -272,7 +272,7 @@ unsigned long write_acpi_tables(unsigned long start) } /* The DSDT needs additional work for the AGESA SSDT Pstate table */ - current = ( current + 0x0f) & -0x10; + current = ALIGN(current, 16); printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); if (ssdt != NULL) { @@ -284,7 +284,7 @@ unsigned long write_acpi_tables(unsigned long start) } acpi_add_table(rsdp,ssdt); - current = ( current + 0x0f) & -0x10; + current = ALIGN(current, 16); printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); ssdt2 = (acpi_header_t *) current; acpi_create_ssdt_generator(ssdt2, ACPI_TABLE_CREATOR); diff --git a/src/mainboard/tyan/s8226/acpi_tables.c b/src/mainboard/tyan/s8226/acpi_tables.c index 3e8f014..4b97844 100644 --- a/src/mainboard/tyan/s8226/acpi_tables.c +++ b/src/mainboard/tyan/s8226/acpi_tables.c @@ -176,7 +176,7 @@ unsigned long write_acpi_tables(unsigned long start) get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ /* Align ACPI tables to 16 bytes */ - start = (start + 0x0f) & -0x10; + start = ALIGN(start, 16); current = start; printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); @@ -218,7 +218,7 @@ unsigned long write_acpi_tables(unsigned long start) * We explicitly add these tables later on: */ #ifdef UNUSED_CODE // Don't need HPET table. we have one in dsdt - current = ( current + 0x07) & -0x08; + current = ALIGN(current, 8); printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); hpet = (acpi_hpet_t *) current; current += sizeof(acpi_hpet_t); @@ -227,7 +227,7 @@ unsigned long write_acpi_tables(unsigned long start) #endif /* If we want to use HPET Timers Linux wants an MADT */ - current = ( current + 0x07) & -0x08; + current = ALIGN(current, 8); printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); madt = (acpi_madt_t *) current; acpi_create_madt(madt); @@ -235,7 +235,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, madt); /* SRAT */ - current = ( current + 0x07) & -0x08; + current = ALIGN(current, 8); printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); if (srat != NULL) { @@ -247,7 +247,7 @@ unsigned long write_acpi_tables(unsigned long start) } /* SLIT */ - current = ( current + 0x07) & -0x08; + current = ALIGN(current, 8); printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); if (slit != NULL) { @@ -259,7 +259,7 @@ unsigned long write_acpi_tables(unsigned long start) } /* SSDT */ - current = (current + 0x0f) & -0x10; + current = ALIGN(current, 16); printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { @@ -272,7 +272,7 @@ unsigned long write_acpi_tables(unsigned long start) } /* The DSDT needs additional work for the AGESA SSDT Pstate table */ - current = ( current + 0x0f) & -0x10; + current = ALIGN(current, 16); printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); if (ssdt != NULL) { @@ -284,7 +284,7 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, " AGESA SSDT table NULL. Skipping.\n"); } - current = ( current + 0x0f) & -0x10; + current = ALIGN(current, 16); printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); ssdt2 = (acpi_header_t *) current; acpi_create_ssdt_generator(ssdt2, ACPI_TABLE_CREATOR);

2 1

Patch merged into coreboot/master: 50f313c */acpi_tables.c: Use ALIGN macro
by gerrit＠coreboot.org 22 Feb '13

22 Feb '13

the following patch was just integrated into master: commit 50f313c8b2cae372d3d3868940c445aeb221ec1e Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Fri Feb 22 20:19:20 2013 +0100 */acpi_tables.c: Use ALIGN macro At the request of Paul Menzel, I reran an old classic of a coccinelle script: @@ expression E; @@ -(E + 7) & -8 +ALIGN(E, 8) @@ expression E; @@ -(E + 15) & -16 +ALIGN(E, 16) Change-Id: I01da31b241585e361380f75aacf3deddb13d11c3 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/2487 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth(a)se-eng.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Build-Tested: build bot (Jenkins) at Fri Feb 22 20:31:16 2013, giving +1 Reviewed-By: Martin Roth <martin.roth(a)se-eng.com> at Fri Feb 22 21:47:07 2013, giving +2 Reviewed-By: Paul Menzel <paulepanter(a)users.sourceforge.net> at Fri Feb 22 22:38:49 2013, giving +2 See http://review.coreboot.org/2487 for details. -gerrit

1 0

Patch set updated for coreboot: f769f44 google/snow: enable GPIO entries and CHROMEOS in building
by Ronald G. Minnich 22 Feb '13

22 Feb '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2467 -gerrit commit f769f440135d83781e17e63bf301a14c68b36670 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Wed Feb 20 15:46:46 2013 -0800 google/snow: enable GPIO entries and CHROMEOS in building These were not separable or it would have been two CLs. Enable CHROMEOS configure option on snow. Write gpio support code for the mainboard. Right now the GPIO just returns hard-wired values for "virtual" GPIOs. This is tested and creates gpio table entries that our hardware can use. Lots still missing but we can now start to fill in the blanks, since we have enabled CHROMEOS for this board. We are getting further into the process of actually booting a real kernel. Add a FLASHMAP_OFFSET entry of 0 for now, to make sure jenkins won't hang. Change-Id: I5fdc68b0b76f9b2172271e991e11bef16f5adb27 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/armv7/boot/coreboot_table.c | 10 ++++------ src/arch/armv7/include/arch/coreboot_tables.h | 2 ++ src/mainboard/google/snow/Kconfig | 2 +- src/mainboard/google/snow/Makefile.inc | 1 + src/vendorcode/google/chromeos/Kconfig | 1 + src/vendorcode/google/chromeos/Makefile.inc | 6 +++--- 6 files changed, 12 insertions(+), 10 deletions(-) diff --git a/src/arch/armv7/boot/coreboot_table.c b/src/arch/armv7/boot/coreboot_table.c index 2810a5e..55610ac 100644 --- a/src/arch/armv7/boot/coreboot_table.c +++ b/src/arch/armv7/boot/coreboot_table.c @@ -23,7 +23,6 @@ #include <console/console.h> #include <ip_checksum.h> #include <boot/tables.h> -#include <boot/coreboot_tables.h> #include <arch/coreboot_tables.h> #include <string.h> #include <version.h> @@ -35,7 +34,7 @@ #include <option_table.h> #endif #if CONFIG_CHROMEOS -#include <arch/acpi.h> +//#include <arch/acpi.h> #include <vendorcode/google/chromeos/gnvs.h> #endif @@ -183,11 +182,10 @@ static void lb_gpios(struct lb_header *header) struct lb_gpios *gpios; gpios = (struct lb_gpios *)lb_new_record(header); gpios->tag = LB_TAG_GPIO; - gpios->size = sizeof(*gpios); - gpios->count = 0; fill_lb_gpios(gpios); } +#if 0 static void lb_vdat(struct lb_header *header) { struct lb_vdat* vdat; @@ -209,6 +207,7 @@ static void lb_vbnv(struct lb_header *header) vbnv->vbnv_size = CONFIG_VBNV_SIZE; } #endif +#endif static void add_cbmem_pointers(struct lb_header *header) { @@ -656,12 +655,11 @@ unsigned long write_coreboot_table( lb_strings(head); /* Record our framebuffer */ lb_framebuffer(head); - -#if 0 #if CONFIG_CHROMEOS /* Record our GPIO settings (ChromeOS specific) */ lb_gpios(head); +#if 0 /* pass along the VDAT buffer adress */ lb_vdat(head); diff --git a/src/arch/armv7/include/arch/coreboot_tables.h b/src/arch/armv7/include/arch/coreboot_tables.h index ab20866..4c2a013 100644 --- a/src/arch/armv7/include/arch/coreboot_tables.h +++ b/src/arch/armv7/include/arch/coreboot_tables.h @@ -12,6 +12,8 @@ unsigned long write_coreboot_table( void lb_memory_range(struct lb_memory *mem, uint32_t type, uint64_t start, uint64_t size); +void fill_lb_gpios(struct lb_gpios *gpios); + /* Routines to extract part so the coreboot table or information * from the coreboot table. */ diff --git a/src/mainboard/google/snow/Kconfig b/src/mainboard/google/snow/Kconfig index bee987d..6face94 100644 --- a/src/mainboard/google/snow/Kconfig +++ b/src/mainboard/google/snow/Kconfig @@ -29,7 +29,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DRIVER_MAXIM_MAX77686 # select HAVE_ACPI_TABLES # select MMCONF_SUPPORT -# select CHROMEOS + select CHROMEOS config MAINBOARD_DIR string diff --git a/src/mainboard/google/snow/Makefile.inc b/src/mainboard/google/snow/Makefile.inc index b56a1a4..668e3b7 100644 --- a/src/mainboard/google/snow/Makefile.inc +++ b/src/mainboard/google/snow/Makefile.inc @@ -23,6 +23,7 @@ romstage-y += romstage.c # ramstage-y += ec.c ramstage-y += ramstage.c +ramstage-y += chromeos.c # romstage-$(CONFIG_CHROMEOS) += chromeos.c diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index 6242147..f34eaa4 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -61,6 +61,7 @@ config FLASHMAP_OFFSET hex "Flash Map Offset" default 0x00670000 if NORTHBRIDGE_INTEL_SANDYBRIDGE default 0x00610000 if NORTHBRIDGE_INTEL_IVYBRIDGE + default 0 if BOARD_GOOGLE_SNOW help Offset of flash map in firmware image diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index 967db96..8ae14fd 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -19,9 +19,9 @@ romstage-y += chromeos.c ramstage-y += chromeos.c -romstage-y += vbnv.c -ramstage-y += vbnv.c -romstage-y += vboot.c +romstage-$(CONFIG_ARCH_X86) += vbnv.c +ramstage-$(CONFIG_ARCH_X86) += vbnv.c +romstage-$(CONFIG_ARCH_X86) += vboot.c ramstage-y += gnvs.c romstage-y += fmap.c ramstage-y += fmap.c

1 0

Patch merged into coreboot/master: 1278142 nvramtool: reduce memory mapping
by gerrit＠coreboot.org 22 Feb '13

22 Feb '13

the following patch was just integrated into master: commit 12781422d5ee2afcfe8da6a3f1b4f6c9d257dec8 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Thu Feb 21 14:03:47 2013 +0100 nvramtool: reduce memory mapping Instead of trying to map the first megabyte, only map what is required to read the tables. Change-Id: I9139dbc8fd1dd768bef7ab85c27cd4c18e2931b3 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Reviewed-on: http://review.coreboot.org/2485 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter(a)stuge.se> Build-Tested: build bot (Jenkins) at Fri Feb 22 15:05:00 2013, giving +1 Reviewed-By: Peter Stuge <peter(a)stuge.se> at Fri Feb 22 16:04:03 2013, giving +2 See http://review.coreboot.org/2485 for details. -gerrit

1 0

New patch to review for coreboot: 97b58e8 nvramtool: reduce memory mapping
by Patrick Georgi 22 Feb '13

22 Feb '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2485 -gerrit commit 97b58e84dfcf4b3b543ac3d75f77c5d66c91fe30 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Thu Feb 21 14:03:47 2013 +0100 nvramtool: reduce memory mapping Instead of trying to map the first megabyte, only map what is required to read the tables. Change-Id: I9139dbc8fd1dd768bef7ab85c27cd4c18e2931b3 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- util/nvramtool/lbtable.c | 90 +++++++++++++++++++++++++----------------------- 1 file changed, 47 insertions(+), 43 deletions(-) diff --git a/util/nvramtool/lbtable.c b/util/nvramtool/lbtable.c index 7a968b7..5f1f22d 100644 --- a/util/nvramtool/lbtable.c +++ b/util/nvramtool/lbtable.c @@ -200,19 +200,15 @@ static const mem_range_t mem_ranges[NUM_MEM_RANGES] = {0x000f0000, 0x000fffff} }; -/* This is the number of bytes of physical memory to map, starting at physical - * address 0. This value must be large enough to contain all memory ranges - * specified in mem_ranges above plus the maximum possible size of the - * coreboot table (since the start of the table could potentially occur at - * the end of the last memory range). - */ -static const size_t BYTES_TO_MAP = (1024 * 1024); - /* Pointer to low physical memory that we access by calling mmap() on * /dev/mem. */ static const void *low_phys_mem; -static unsigned long low_phys_base = 0; +/* impossible value since not page aligned: first map request will happen */ +static unsigned long low_phys_base = 0x1; + +/* count of mapped pages */ +static unsigned long mapped_pages = 0; /* Pointer to coreboot table. */ static const struct lb_header *lbtable = NULL; @@ -243,6 +239,37 @@ static const hexdump_format_t format = ((unsigned long) paddr) - low_phys_base) /**************************************************************************** + * map_pages + * + * Maps just enough pages to cover base_address + length + * and updates affected variables + ****************************************************************************/ +static void map_pages(unsigned long base_address, unsigned long length) +{ + unsigned long num_pages = (length + + (base_address & (getpagesize() - 1)) + + getpagesize() - 1) >> 12; + base_address &= ~(getpagesize() - 1); + + /* no need to do anything */ + if ((low_phys_base == base_address) && (mapped_pages == num_pages)) { + return; + } + + if (low_phys_mem) { + munmap((void *)low_phys_mem, mapped_pages << 12); + } + if ((low_phys_mem = mmap(NULL, num_pages << 12, PROT_READ, MAP_SHARED, fd, + (off_t) base_address)) == MAP_FAILED) { + fprintf(stderr, + "%s: Failed to mmap /dev/mem at %lx: %s\n", + prog_name, base_address, strerror(errno)); + exit(1); + } + low_phys_base = base_address; +} + +/**************************************************************************** * get_lbtable * * Find the coreboot table and set global variable lbtable to point to it. @@ -264,20 +291,11 @@ void get_lbtable(void) exit(1); } - if ((low_phys_mem = - mmap(NULL, BYTES_TO_MAP, PROT_READ, MAP_SHARED, fd, 0)) - == MAP_FAILED) { - fprintf(stderr, "%s: Failed to mmap /dev/mem: %s\n", prog_name, - strerror(errno)); - exit(1); - } - bad_header_count = 0; bad_table_count = 0; for (i = 0; i < NUM_MEM_RANGES; i++) { - lbtable = lbtable_scan(phystov(mem_ranges[i].start), - phystov(mem_ranges[i].end), + lbtable = lbtable_scan(mem_ranges[i].start, mem_ranges[i].end, &bad_headers, &bad_tables); if (lbtable != NULL) @@ -421,8 +439,7 @@ void list_lbtable_item(const char item[]) * first and last bytes of the chunk of memory to be scanned. For instance, * values of 0x10000000 and 0x1000ffff for 'start' and 'end' specify a 64k * chunk of memory starting at address 0x10000000. 'start' and 'end' are - * virtual addresses in the address space of the current process. They - * represent a chunk of memory obtained by calling mmap() on /dev/mem. + * physical addresses. * * If a coreboot table is found, return a pointer to it. Otherwise return * NULL. On return, *bad_header_count and *bad_table_count are set as @@ -444,7 +461,7 @@ static const struct lb_header *lbtable_scan(unsigned long start, static const char signature[4] = { 'L', 'B', 'I', 'O' }; const struct lb_header *table; const struct lb_forward *forward; - const uint32_t *p; + unsigned long p; uint32_t sig; assert(end >= start); @@ -459,14 +476,15 @@ static const struct lb_header *lbtable_scan(unsigned long start, * for 'start' and 'end': even weird boundary cases like 0x00000000 and * 0xffffffff on a 32-bit architecture. */ - for (p = (const uint32_t *)start; - (((unsigned long)p) <= end) && - ((end - (unsigned long)p) >= (sizeof(uint32_t) - 1)); p += 4) { - if (*p != sig) + map_pages(start, end - start); + for (p = start; + (p <= end) && + (end - p >= (sizeof(uint32_t) - 1)); p += 4) { + if (*(uint32_t*)phystov(p) != sig) continue; /* We found a valid signature. */ - table = (const struct lb_header *)p; + table = (const struct lb_header *)phystov(p); /* validate header checksum */ if (compute_ip_checksum((void *)table, sizeof(*table))) { @@ -474,6 +492,7 @@ static const struct lb_header *lbtable_scan(unsigned long start, continue; } + map_pages(p, table->table_bytes + sizeof(*table)); /* validate table checksum */ if (table->table_checksum != compute_ip_checksum(((char *)table) + sizeof(*table), @@ -490,22 +509,7 @@ static const struct lb_header *lbtable_scan(unsigned long start, if (forward) { uint64_t new_phys = forward->forward; - - new_phys &= ~(getpagesize() - 1); - - munmap((void *)low_phys_mem, BYTES_TO_MAP); - if ((low_phys_mem = - mmap(NULL, BYTES_TO_MAP, PROT_READ, MAP_SHARED, fd, - (off_t) new_phys)) == MAP_FAILED) { - fprintf(stderr, - "%s: Failed to mmap /dev/mem: %s\n", - prog_name, strerror(errno)); - exit(1); - } - low_phys_base = new_phys; - table = - lbtable_scan(phystov(low_phys_base), - phystov(low_phys_base + BYTES_TO_MAP), + table = lbtable_scan(new_phys, new_phys + getpagesize(), bad_header_count, bad_table_count); } return table;

1 0

Patch set updated for coreboot: b00a042 AMD Fam14 boards: Set P_BLK length to 6 for all processors
by Paul Menzel 22 Feb '13

22 Feb '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2189 -gerrit commit b00a042319821812ee1e1e8b7f567caa218a4ccf Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Mon Jan 21 18:43:12 2013 +0100 AMD Fam14 boards: Set P_BLK length to 6 for all processors Currently on for example on AMD Persimmon and ASRock E350M1 Linux complains, that the PBLK length is invalid [1]. ACPI: Invalid PBLK length [0] Consequently, frequency scaling might not work correctly, though for these two boards it seems to work according to PowerTOP. Indeed, according to the ACPI specification [2], setting PBlockLength to 0 is only allowed if there is no PBlockAddress. Otherwise it has to be set to 6. 18.5.93 Processor (Declare Processor) […] PBlockAddress provides the system I/O address for the processors register block. Each processor can supply a different such address. PBlockLength is the length of the processor register block, in bytes and is either 0 (for no P_BLK) or 6. With one exception, all processors are required to have the same PBlockLength. The exception is that the boot processor can have a non-zero PBlockLength when all other processors have a zero PBlockLength. It is valid for every processor to have a PBlockLength of 0. And that is exactly what Linux is checking in `drivers/acpi/processor_driver.c` [3]. static int acpi_processor_get_info(struct acpi_device *device) { […] /* * On some boxes several processors use the same processor bus id. * But they are located in different scope. For example: * \_SB.SCK0.CPU0 * \_SB.SCK1.CPU0 * Rename the processor device bus id. And the new bus id will be * generated as the following format: * CPU+CPU ID. */ sprintf(acpi_device_bid(device), "CPU%X", pr->id); ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Processor [%d:%d]\n", pr->id, pr->acpi_id)); if (!object.processor.pblk_address) ACPI_DEBUG_PRINT((ACPI_DB_INFO, "No PBLK (NULL address)\n")); else if (object.processor.pblk_length != 6) printk(KERN_ERR PREFIX "Invalid PBLK length [%d]\n", object.processor.pblk_length); else { pr->throttling.address = object.processor.pblk_address; pr->throttling.duty_offset = acpi_gbl_FADT.duty_offset; pr->throttling.duty_width = acpi_gbl_FADT.duty_width; pr->pblk = object.processor.pblk_address; /* * We don't care about error returns - we just try to mark * these reserved so that nobody else is confused into thinking * that this region might be unused.. * * (In particular, allocating the IO range for Cardbus) */ request_region(pr->throttling.address, 6, "ACPI CPU throttle"); } […] } This issue has proliferated to all AMD based boards so fix it for all of them by setting P_BLK length to 6. The DSDT of for example AMD Parmer and AMD Thatcher also set it to 6 everywhere so this solution is taken instead of setting the P_BLK system I/O base to 0 for all but the first processor which is how it is done for earlier AMD based boards. As note having to set this manually should not be needed and this should be autogenerated as done for most of the Intel boards and the AMD K8 based boards (`src/cpu/amd/model_fxx/powernow_acpi.c`). [1] http://www.coreboot.org/pipermail/coreboot/2013-January/073636.html [2] http://acpi.info/DOWNLOADS/ACPIspec40a.pdf [3] http://git.kernel.org/?p=linux/kernel/git/torvalds/linux.git;a=blob;f=drive… Tested-by: Paul Menzel <paulepanter(a)users.sourceforge.net> • ASRock E350M1: Tested-by: Paul Menzel <paulepanter(a)users.sourceforge.net> • AMD Persimmon: Tested-by: Martin Roth <martin.roth(a)se-eng.com> Change-Id: Ie79fe4812532d124cc81747c75a4f3d88d00531c Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- 3rdparty | 2 +- src/mainboard/amd/dinar/dsdt.asl | 14 +++++++------- src/mainboard/amd/inagua/dsdt.asl | 6 +++--- src/mainboard/amd/persimmon/dsdt.asl | 6 +++--- src/mainboard/amd/south_station/dsdt.asl | 6 +++--- src/mainboard/amd/torpedo/dsdt.asl | 6 +++--- src/mainboard/amd/union_station/dsdt.asl | 6 +++--- src/mainboard/asrock/e350m1/dsdt.asl | 6 +++--- 8 files changed, 26 insertions(+), 26 deletions(-) diff --git a/3rdparty b/3rdparty index dcd1ca7..dac1a18 160000 --- a/3rdparty +++ b/3rdparty @@ -1 +1 @@ -Subproject commit dcd1ca72bbef1c53b54282e1c77633f0f1876325 +Subproject commit dac1a18d184976e4447b98479f0b7a172054b98f diff --git a/src/mainboard/amd/dinar/dsdt.asl b/src/mainboard/amd/dinar/dsdt.asl index 7df090f..0611fd3 100644 --- a/src/mainboard/amd/dinar/dsdt.asl +++ b/src/mainboard/amd/dinar/dsdt.asl @@ -61,49 +61,49 @@ DefinitionBlock ( C001, /* name space name */ 1, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ - 0x0 /* PBLKLEN for boot processor */ + 0x06 /* PBLKLEN for boot processor */ ) { } Processor( C002, /* name space name */ 2, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ + 0x06 /* PBLKLEN for boot processor */ ) { } Processor( C003, /* name space name */ 3, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ + 0x06 /* PBLKLEN for boot processor */ ) { } Processor( C004, /* name space name */ 4, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ + 0x06 /* PBLKLEN for boot processor */ ) { } Processor( C005, /* name space name */ 5, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ + 0x06 /* PBLKLEN for boot processor */ ) { } Processor( C006, /* name space name */ 6, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ + 0x06 /* PBLKLEN for boot processor */ ) { } Processor( C007, /* name space name */ 7, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ + 0x06 /* PBLKLEN for boot processor */ ) { } } /* End _PR scope */ diff --git a/src/mainboard/amd/inagua/dsdt.asl b/src/mainboard/amd/inagua/dsdt.asl index 46b92f1..819bb32 100644 --- a/src/mainboard/amd/inagua/dsdt.asl +++ b/src/mainboard/amd/inagua/dsdt.asl @@ -75,21 +75,21 @@ DefinitionBlock ( C001, /* name space name */ 1, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ + 0x06 /* PBLKLEN for boot processor */ ) { } Processor( C002, /* name space name */ 2, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ + 0x06 /* PBLKLEN for boot processor */ ) { } Processor( C003, /* name space name */ 3, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ + 0x06 /* PBLKLEN for boot processor */ ) { } } /* End _PR scope */ diff --git a/src/mainboard/amd/persimmon/dsdt.asl b/src/mainboard/amd/persimmon/dsdt.asl index dd7b4b1..22c0295 100644 --- a/src/mainboard/amd/persimmon/dsdt.asl +++ b/src/mainboard/amd/persimmon/dsdt.asl @@ -75,21 +75,21 @@ DefinitionBlock ( C001, /* name space name */ 1, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ + 0x06 /* PBLKLEN for boot processor */ ) { } Processor( C002, /* name space name */ 2, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ + 0x06 /* PBLKLEN for boot processor */ ) { } Processor( C003, /* name space name */ 3, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ + 0x06 /* PBLKLEN for boot processor */ ) { } } /* End _PR scope */ diff --git a/src/mainboard/amd/south_station/dsdt.asl b/src/mainboard/amd/south_station/dsdt.asl index 958295b..77e1aab 100644 --- a/src/mainboard/amd/south_station/dsdt.asl +++ b/src/mainboard/amd/south_station/dsdt.asl @@ -75,21 +75,21 @@ DefinitionBlock ( C001, /* name space name */ 1, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ + 0x06 /* PBLKLEN for boot processor */ ) { } Processor( C002, /* name space name */ 2, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ + 0x06 /* PBLKLEN for boot processor */ ) { } Processor( C003, /* name space name */ 3, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ + 0x06 /* PBLKLEN for boot processor */ ) { } } /* End _PR scope */ diff --git a/src/mainboard/amd/torpedo/dsdt.asl b/src/mainboard/amd/torpedo/dsdt.asl index 61ceca0..17e0deb 100755 --- a/src/mainboard/amd/torpedo/dsdt.asl +++ b/src/mainboard/amd/torpedo/dsdt.asl @@ -61,21 +61,21 @@ DefinitionBlock ( C001, /* name space name */ 1, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ + 0x06 /* PBLKLEN for boot processor */ ) { } Processor( C002, /* name space name */ 2, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ + 0x06 /* PBLKLEN for boot processor */ ) { } Processor( C003, /* name space name */ 3, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ + 0x06 /* PBLKLEN for boot processor */ ) { } } /* End _PR scope */ diff --git a/src/mainboard/amd/union_station/dsdt.asl b/src/mainboard/amd/union_station/dsdt.asl index 0752640..818cc18 100644 --- a/src/mainboard/amd/union_station/dsdt.asl +++ b/src/mainboard/amd/union_station/dsdt.asl @@ -75,21 +75,21 @@ DefinitionBlock ( C001, /* name space name */ 1, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ + 0x06 /* PBLKLEN for boot processor */ ) { } Processor( C002, /* name space name */ 2, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ + 0x06 /* PBLKLEN for boot processor */ ) { } Processor( C003, /* name space name */ 3, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ + 0x06 /* PBLKLEN for boot processor */ ) { } } /* End _PR scope */ diff --git a/src/mainboard/asrock/e350m1/dsdt.asl b/src/mainboard/asrock/e350m1/dsdt.asl index 1cd88b8..e34f161 100644 --- a/src/mainboard/asrock/e350m1/dsdt.asl +++ b/src/mainboard/asrock/e350m1/dsdt.asl @@ -75,21 +75,21 @@ DefinitionBlock ( C001, /* name space name */ 1, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ + 0x06 /* PBLKLEN for boot processor */ ) { } Processor( C002, /* name space name */ 2, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ + 0x06 /* PBLKLEN for boot processor */ ) { } Processor( C003, /* name space name */ 3, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ + 0x06 /* PBLKLEN for boot processor */ ) { } } /* End _PR scope */

1 0

Patch set updated for coreboot: 4109da0 AMD based boards: platform_cfg.h: Replace `_*BOARDNAME*_CFG_H_` with `_PLATFORM_CFG_H_`
by Paul Menzel 22 Feb '13

22 Feb '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2464 -gerrit commit 4109da0b0f9b281f83b64f5cb94c3561e0b2d742 Author: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Date: Wed Feb 20 21:24:20 2013 +0100 AMD based boards: platform_cfg.h: Replace `_*BOARDNAME*_CFG_H_` with `_PLATFORM_CFG_H_` Reduce unnecessary differences between AMD based boards only using the file `platform_cfg.h` for configuration making them a little bit easier to compare. Inagua & co. mention the board name in several places which are really not that board specific. Sometimes people even forget to change it: Union Station’s platform_cfg.h starts with "#ifndef _PERSIMMON_CFG_H_". Funny. Change that to "_PLATFORM_CFG_H_" everywhere. The following command was used. $ find . -name platform_cfg.h | xargs sed -i '/_CFG_H_/s/_.*_/_PLATFORM_CFG_H_/' More boards seem to use that kind of naming (`git grep _CFG_H_`) but it is not certain that this will not break anything as for example the board AMD Dinar also has header files for configuration stuff for the north- and southbridge. $ git grep _CFG_H_ […] src/mainboard/amd/dinar/platform_cfg.h:#ifndef _PLATFORM_CFG_H_ src/mainboard/amd/dinar/platform_cfg.h:#define _PLATFORM_CFG_H_ src/mainboard/amd/dinar/platform_cfg.h:#endif //_PLATFORM_CFG_H_ src/mainboard/amd/dinar/rd890_cfg.h:#ifndef _RD890_CFG_H_ src/mainboard/amd/dinar/rd890_cfg.h:#define _RD890_CFG_H_ src/mainboard/amd/dinar/rd890_cfg.h:#endif //_RD890_CFG_H_ src/mainboard/amd/dinar/sb700_cfg.h:#ifndef _SB700_CFG_H_ src/mainboard/amd/dinar/sb700_cfg.h:#define _SB700_CFG_H_ src/mainboard/amd/dinar/sb700_cfg.h:#endif //_SB700_CFG_H […] Change-Id: Ida15fa6a7adfc770240ac30e795946000dae3f16 Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/advansus/a785e-i/platform_cfg.h | 4 ++-- src/mainboard/amd/inagua/platform_cfg.h | 4 ++-- src/mainboard/amd/persimmon/platform_cfg.h | 4 ++-- src/mainboard/amd/south_station/platform_cfg.h | 4 ++-- src/mainboard/amd/torpedo/platform_cfg.h | 4 ++-- src/mainboard/amd/union_station/platform_cfg.h | 4 ++-- src/mainboard/asrock/e350m1/platform_cfg.h | 4 ++-- src/mainboard/asus/m5a88-v/platform_cfg.h | 4 ++-- src/mainboard/avalue/eax-785e/platform_cfg.h | 4 ++-- 9 files changed, 18 insertions(+), 18 deletions(-) diff --git a/src/mainboard/advansus/a785e-i/platform_cfg.h b/src/mainboard/advansus/a785e-i/platform_cfg.h index 8b90d57..e2d9412 100644 --- a/src/mainboard/advansus/a785e-i/platform_cfg.h +++ b/src/mainboard/advansus/a785e-i/platform_cfg.h @@ -18,8 +18,8 @@ */ -#ifndef _A785E_I_CFG_H_ -#define _A785E_I_CFG_H_ +#ifndef _PLATFORM_CFG_H_ +#define _PLATFORM_CFG_H_ /** * @def BIOS_SIZE_1M diff --git a/src/mainboard/amd/inagua/platform_cfg.h b/src/mainboard/amd/inagua/platform_cfg.h index 88526db..d29a7a5 100644 --- a/src/mainboard/amd/inagua/platform_cfg.h +++ b/src/mainboard/amd/inagua/platform_cfg.h @@ -18,8 +18,8 @@ */ -#ifndef _INAGUA_CFG_H_ -#define _INAGUA_CFG_H_ +#ifndef _PLATFORM_CFG_H_ +#define _PLATFORM_CFG_H_ /** * @def BIOS_SIZE_1M diff --git a/src/mainboard/amd/persimmon/platform_cfg.h b/src/mainboard/amd/persimmon/platform_cfg.h index e773f75..6590e4e 100644 --- a/src/mainboard/amd/persimmon/platform_cfg.h +++ b/src/mainboard/amd/persimmon/platform_cfg.h @@ -18,8 +18,8 @@ */ -#ifndef _PERSIMMON_CFG_H_ -#define _PERSIMMON_CFG_H_ +#ifndef _PLATFORM_CFG_H_ +#define _PLATFORM_CFG_H_ /** * @def BIOS_SIZE_1M diff --git a/src/mainboard/amd/south_station/platform_cfg.h b/src/mainboard/amd/south_station/platform_cfg.h index a5f9838..d712875 100644 --- a/src/mainboard/amd/south_station/platform_cfg.h +++ b/src/mainboard/amd/south_station/platform_cfg.h @@ -18,8 +18,8 @@ */ -#ifndef _PERSIMMON_CFG_H_ -#define _PERSIMMON_CFG_H_ +#ifndef _PLATFORM_CFG_H_ +#define _PLATFORM_CFG_H_ /** * @def BIOS_SIZE_1M diff --git a/src/mainboard/amd/torpedo/platform_cfg.h b/src/mainboard/amd/torpedo/platform_cfg.h index a6d02e8..6c27249 100644 --- a/src/mainboard/amd/torpedo/platform_cfg.h +++ b/src/mainboard/amd/torpedo/platform_cfg.h @@ -18,8 +18,8 @@ */ -#ifndef _SB900_CFG_H_ -#define _SB900_CFG_H_ +#ifndef _PLATFORM_CFG_H_ +#define _PLATFORM_CFG_H_ #include <stdint.h> diff --git a/src/mainboard/amd/union_station/platform_cfg.h b/src/mainboard/amd/union_station/platform_cfg.h index a5f9838..d712875 100644 --- a/src/mainboard/amd/union_station/platform_cfg.h +++ b/src/mainboard/amd/union_station/platform_cfg.h @@ -18,8 +18,8 @@ */ -#ifndef _PERSIMMON_CFG_H_ -#define _PERSIMMON_CFG_H_ +#ifndef _PLATFORM_CFG_H_ +#define _PLATFORM_CFG_H_ /** * @def BIOS_SIZE_1M diff --git a/src/mainboard/asrock/e350m1/platform_cfg.h b/src/mainboard/asrock/e350m1/platform_cfg.h index 7fa9c23..1b09590 100644 --- a/src/mainboard/asrock/e350m1/platform_cfg.h +++ b/src/mainboard/asrock/e350m1/platform_cfg.h @@ -18,8 +18,8 @@ */ -#ifndef _E350M1_CFG_H_ -#define _E350M1_CFG_H_ +#ifndef _PLATFORM_CFG_H_ +#define _PLATFORM_CFG_H_ /** * @def BIOS_SIZE_1M diff --git a/src/mainboard/asus/m5a88-v/platform_cfg.h b/src/mainboard/asus/m5a88-v/platform_cfg.h index 40741d9..e2d9412 100644 --- a/src/mainboard/asus/m5a88-v/platform_cfg.h +++ b/src/mainboard/asus/m5a88-v/platform_cfg.h @@ -18,8 +18,8 @@ */ -#ifndef _M5A88_V_CFG_H_ -#define _M5A88_V_CFG_H_ +#ifndef _PLATFORM_CFG_H_ +#define _PLATFORM_CFG_H_ /** * @def BIOS_SIZE_1M diff --git a/src/mainboard/avalue/eax-785e/platform_cfg.h b/src/mainboard/avalue/eax-785e/platform_cfg.h index fd02f7d..bea852d 100644 --- a/src/mainboard/avalue/eax-785e/platform_cfg.h +++ b/src/mainboard/avalue/eax-785e/platform_cfg.h @@ -18,8 +18,8 @@ */ -#ifndef _EAX_785E_CFG_H_ -#define _EAX_785E_CFG_H_ +#ifndef _PLATFORM_CFG_H_ +#define _PLATFORM_CFG_H_ /** * @def BIOS_SIZE_1M

1 0

← Newer
1
...
13
14
15
16
17
18
19
...
79
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot February 2013