coreboot February 2013

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Patch merged into coreboot/master: 522b556 AMD boards: Fix typo `@brief` in comment
by gerrit＠coreboot.org 21 Feb '13

21 Feb '13

the following patch was just integrated into master: commit 522b55638f98ba773aecd4ccd2b5a424d933aa59 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu Feb 21 17:09:01 2013 +0100 AMD boards: Fix typo `@brief` in comment The following command was used to correct the typo. $ git grep -l @breif | xargs sed -i 's/@breif/@brief/' Change-Id: If0b579279de3c41571b9cda643836f5748a752a2 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2473 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Thu Feb 21 17:18:22 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Thu Feb 21 19:27:10 2013, giving +2 See http://review.coreboot.org/2473 for details. -gerrit

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i915tool
by ron minnich 21 Feb '13

21 Feb '13

I just updated it. https://code.google.com/p/i915tool/ I had to wait, starting some time ago, because there was too much info appearing in it about this: http://techland.time.com/2013/02/21/googles-chomebook-pixel-the-chromebook-… and I got nervous. Status: you'll see in as we upstream the coreboot that we can turn on graphics in coreboot now without a vbios. The code is crude and I'm in the process of creating a replacement. The tool to create the real code is in the i915tool and is called gen915code.c. Note that it does lot of annotation, turning things like this: {W, 1, "", _PIPEACONF, 0x00000040, }, {W, 1, "", _PIPEACONF, (/* PIPECONF_FRAME_START_DELAY_MASK */0x0<<27)| PIPECONF_BPP_6 | PIPECONF_DITHER_TYPE_SP |0x00000 What this means is that moving to other laptops *may* be easier. We've got kernel patches too, and the result is that we've (in an experiment) reduced boot time to a login prompt to less than 4 seconds (after firmware is finished). My goal is to make that better, but we'll see. But we chopped a full 3 seconds off of boot. I am sorry this i915tool is a mess. I really wish it were better. I offer it in the state it is because I'm hoping it can be used, but it's very experimental and represents a lot of lessons learned the hard way. Part of this mess is that my ideas about how to do the work have changed so much since I started it. Here are docs, which are also not very good, sorry! https://docs.google.com/document/d/1g8FMob25VZYxbWri2iFB8YiSL8gwF9vKJH3HGxr… Questions to me. Hope that some part of this is useful. ron

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Patch merged into coreboot/master: 824e192 Persimmon: platform_cfg.h: Declare codec arrays as `static const`
by gerrit＠coreboot.org 21 Feb '13

21 Feb '13

the following patch was just integrated into master: commit 824e192809e021b3cdee947a44b3a18d276bdb35 Author: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Date: Wed Feb 20 21:24:20 2013 +0100 Persimmon: platform_cfg.h: Declare codec arrays as `static const` From ISO C99 standard: »The placement of a storage-class specifier other than at the beginning of the declaration specifiers in a declaration is an obsolescent feature.« Found at <http://www.approxion.com/?p=41>. Change-Id: Iee7878affb2a5d157a94763083689d75e8218b2f Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2474 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Thu Feb 21 17:30:07 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Thu Feb 21 19:21:27 2013, giving +2 See http://review.coreboot.org/2474 for details. -gerrit

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Patch set updated for coreboot: 5bfdb87 google/snow: enable GPIO entries and CHROMEOS in building
by Ronald G. Minnich 21 Feb '13

21 Feb '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2467 -gerrit commit 5bfdb8779d1eda9700156db0b265a64a47a48d37 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Wed Feb 20 15:46:46 2013 -0800 google/snow: enable GPIO entries and CHROMEOS in building These were not separable or it would have been two CLs. Enable CHROMEOS configure option on snow. Write gpio support code for the mainboard. Right now the GPIO just returns hard-wired values for "virtual" GPIOs. This is tested and creates gpio table entries that our hardware can use. Lots still missing but we can now start to fill in the blanks, since we have enabled CHROMEOS for this board. We are getting further into the process of actually booting a real kernel. Change-Id: I5fdc68b0b76f9b2172271e991e11bef16f5adb27 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/armv7/boot/coreboot_table.c | 10 ++++------ src/arch/armv7/include/arch/coreboot_tables.h | 2 ++ src/mainboard/google/snow/Kconfig | 2 +- src/mainboard/google/snow/Makefile.inc | 1 + src/vendorcode/google/chromeos/Makefile.inc | 6 +++--- 5 files changed, 11 insertions(+), 10 deletions(-) diff --git a/src/arch/armv7/boot/coreboot_table.c b/src/arch/armv7/boot/coreboot_table.c index 2810a5e..55610ac 100644 --- a/src/arch/armv7/boot/coreboot_table.c +++ b/src/arch/armv7/boot/coreboot_table.c @@ -23,7 +23,6 @@ #include <console/console.h> #include <ip_checksum.h> #include <boot/tables.h> -#include <boot/coreboot_tables.h> #include <arch/coreboot_tables.h> #include <string.h> #include <version.h> @@ -35,7 +34,7 @@ #include <option_table.h> #endif #if CONFIG_CHROMEOS -#include <arch/acpi.h> +//#include <arch/acpi.h> #include <vendorcode/google/chromeos/gnvs.h> #endif @@ -183,11 +182,10 @@ static void lb_gpios(struct lb_header *header) struct lb_gpios *gpios; gpios = (struct lb_gpios *)lb_new_record(header); gpios->tag = LB_TAG_GPIO; - gpios->size = sizeof(*gpios); - gpios->count = 0; fill_lb_gpios(gpios); } +#if 0 static void lb_vdat(struct lb_header *header) { struct lb_vdat* vdat; @@ -209,6 +207,7 @@ static void lb_vbnv(struct lb_header *header) vbnv->vbnv_size = CONFIG_VBNV_SIZE; } #endif +#endif static void add_cbmem_pointers(struct lb_header *header) { @@ -656,12 +655,11 @@ unsigned long write_coreboot_table( lb_strings(head); /* Record our framebuffer */ lb_framebuffer(head); - -#if 0 #if CONFIG_CHROMEOS /* Record our GPIO settings (ChromeOS specific) */ lb_gpios(head); +#if 0 /* pass along the VDAT buffer adress */ lb_vdat(head); diff --git a/src/arch/armv7/include/arch/coreboot_tables.h b/src/arch/armv7/include/arch/coreboot_tables.h index ab20866..4c2a013 100644 --- a/src/arch/armv7/include/arch/coreboot_tables.h +++ b/src/arch/armv7/include/arch/coreboot_tables.h @@ -12,6 +12,8 @@ unsigned long write_coreboot_table( void lb_memory_range(struct lb_memory *mem, uint32_t type, uint64_t start, uint64_t size); +void fill_lb_gpios(struct lb_gpios *gpios); + /* Routines to extract part so the coreboot table or information * from the coreboot table. */ diff --git a/src/mainboard/google/snow/Kconfig b/src/mainboard/google/snow/Kconfig index bee987d..6face94 100644 --- a/src/mainboard/google/snow/Kconfig +++ b/src/mainboard/google/snow/Kconfig @@ -29,7 +29,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DRIVER_MAXIM_MAX77686 # select HAVE_ACPI_TABLES # select MMCONF_SUPPORT -# select CHROMEOS + select CHROMEOS config MAINBOARD_DIR string diff --git a/src/mainboard/google/snow/Makefile.inc b/src/mainboard/google/snow/Makefile.inc index b56a1a4..668e3b7 100644 --- a/src/mainboard/google/snow/Makefile.inc +++ b/src/mainboard/google/snow/Makefile.inc @@ -23,6 +23,7 @@ romstage-y += romstage.c # ramstage-y += ec.c ramstage-y += ramstage.c +ramstage-y += chromeos.c # romstage-$(CONFIG_CHROMEOS) += chromeos.c diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index 967db96..8ae14fd 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -19,9 +19,9 @@ romstage-y += chromeos.c ramstage-y += chromeos.c -romstage-y += vbnv.c -ramstage-y += vbnv.c -romstage-y += vboot.c +romstage-$(CONFIG_ARCH_X86) += vbnv.c +ramstage-$(CONFIG_ARCH_X86) += vbnv.c +romstage-$(CONFIG_ARCH_X86) += vboot.c ramstage-y += gnvs.c romstage-y += fmap.c ramstage-y += fmap.c

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Patch set updated for coreboot: 9aa4ece AMD Fam14 boards: Replace `_*BOARDNAME*_CFG_H_` to `_PLATFORM_CFG_H_`
by Paul Menzel 21 Feb '13

21 Feb '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2464 -gerrit commit 9aa4ece770b2602220d038effc46079215b04822 Author: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Date: Wed Feb 20 21:24:20 2013 +0100 AMD Fam14 boards: Replace `_*BOARDNAME*_CFG_H_` to `_PLATFORM_CFG_H_` Reduce unnecessary differences between AMD Inagua, Persimmon, Union Station, South Station and Asrock E350M1, making them a little bit easier to compare. Inagua & co. mention the board name in several places which are really not that board specific. Sometimes people even forget to change it: Union Station’s platform_cfg.h starts with "#ifndef _PERSIMMON_CFG_H_". Funny. Change that to "_PLATFORM_CFG_H_" everywhere. Change-Id: Ida15fa6a7adfc770240ac30e795946000dae3f16 Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/amd/inagua/platform_cfg.h | 4 ++-- src/mainboard/amd/south_station/platform_cfg.h | 4 ++-- src/mainboard/amd/union_station/platform_cfg.h | 4 ++-- src/mainboard/asrock/e350m1/platform_cfg.h | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/mainboard/amd/inagua/platform_cfg.h b/src/mainboard/amd/inagua/platform_cfg.h index dd0251f..ded42df 100644 --- a/src/mainboard/amd/inagua/platform_cfg.h +++ b/src/mainboard/amd/inagua/platform_cfg.h @@ -18,8 +18,8 @@ */ -#ifndef _INAGUA_CFG_H_ -#define _INAGUA_CFG_H_ +#ifndef _PLATFORM_CFG_H_ +#define _PLATFORM_CFG_H_ /** * @def BIOS_SIZE_1M diff --git a/src/mainboard/amd/south_station/platform_cfg.h b/src/mainboard/amd/south_station/platform_cfg.h index 1c8506b..3be7b19 100644 --- a/src/mainboard/amd/south_station/platform_cfg.h +++ b/src/mainboard/amd/south_station/platform_cfg.h @@ -18,8 +18,8 @@ */ -#ifndef _PERSIMMON_CFG_H_ -#define _PERSIMMON_CFG_H_ +#ifndef _PLATFORM_CFG_H_ +#define _PLATFORM_CFG_H_ /** * @def BIOS_SIZE_1M diff --git a/src/mainboard/amd/union_station/platform_cfg.h b/src/mainboard/amd/union_station/platform_cfg.h index 1c8506b..3be7b19 100644 --- a/src/mainboard/amd/union_station/platform_cfg.h +++ b/src/mainboard/amd/union_station/platform_cfg.h @@ -18,8 +18,8 @@ */ -#ifndef _PERSIMMON_CFG_H_ -#define _PERSIMMON_CFG_H_ +#ifndef _PLATFORM_CFG_H_ +#define _PLATFORM_CFG_H_ /** * @def BIOS_SIZE_1M diff --git a/src/mainboard/asrock/e350m1/platform_cfg.h b/src/mainboard/asrock/e350m1/platform_cfg.h index 7fa9c23..1b09590 100644 --- a/src/mainboard/asrock/e350m1/platform_cfg.h +++ b/src/mainboard/asrock/e350m1/platform_cfg.h @@ -18,8 +18,8 @@ */ -#ifndef _E350M1_CFG_H_ -#define _E350M1_CFG_H_ +#ifndef _PLATFORM_CFG_H_ +#define _PLATFORM_CFG_H_ /** * @def BIOS_SIZE_1M

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New patch to review for coreboot: acaf9f2 Persimmon: platform_cfg.h: Declare codec arrays as `static const`
by Paul Menzel 21 Feb '13

21 Feb '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2474 -gerrit commit acaf9f24c4280cb8c4f40aaa187b20746fd129bd Author: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Date: Wed Feb 20 21:24:20 2013 +0100 Persimmon: platform_cfg.h: Declare codec arrays as `static const` From ISO C99 standard: »The placement of a storage-class specifier other than at the beginning of the declaration specifiers in a declaration is an obsolescent feature.« Found at <http://www.approxion.com/?p=41>. Change-Id: Iee7878affb2a5d157a94763083689d75e8218b2f Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/amd/persimmon/platform_cfg.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/amd/persimmon/platform_cfg.h b/src/mainboard/amd/persimmon/platform_cfg.h index 7051e7d..81593ca 100644 --- a/src/mainboard/amd/persimmon/platform_cfg.h +++ b/src/mainboard/amd/persimmon/platform_cfg.h @@ -227,7 +227,7 @@ */ #define GEC_CONFIG 0 -const static CODECENTRY persimmon_codec_alc269[] = +static const CODECENTRY persimmon_codec_alc269[] = { /* NID, PinConfig */ {0x12, 0x411111F0}, @@ -244,7 +244,7 @@ const static CODECENTRY persimmon_codec_alc269[] = {0xff, 0xffffffff} /* end of table */ }; -const static CODECTBLLIST persimmon_codec_tablelist[] = +static const CODECTBLLIST persimmon_codec_tablelist[] = { {0x010ec0269, (CODECENTRY*)&persimmon_codec_alc269[0]}, {0x0FFFFFFFFUL, (CODECENTRY*)0x0FFFFFFFFUL}

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New patch to review for coreboot: 40fc6a6 AMD boards: Fix typo `@brief` in comment
by Paul Menzel 21 Feb '13

21 Feb '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2473 -gerrit commit 40fc6a6da8e0f3c9e90375cac05868ef883f6a3f Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu Feb 21 17:09:01 2013 +0100 AMD boards: Fix typo `@brief` in comment The following command was used to correct the typo. $ git grep -l @breif | xargs sed -i 's/@breif/@brief/' Change-Id: If0b579279de3c41571b9cda643836f5748a752a2 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/advansus/a785e-i/platform_cfg.h | 14 +++++++------- src/mainboard/amd/dinar/sb700_cfg.h | 14 +++++++------- src/mainboard/amd/inagua/platform_cfg.h | 14 +++++++------- src/mainboard/amd/persimmon/platform_cfg.h | 14 +++++++------- src/mainboard/amd/south_station/platform_cfg.h | 14 +++++++------- src/mainboard/amd/union_station/platform_cfg.h | 14 +++++++------- src/mainboard/asus/m5a88-v/platform_cfg.h | 14 +++++++------- src/mainboard/avalue/eax-785e/platform_cfg.h | 14 +++++++------- src/mainboard/supermicro/h8qgi/sb700_cfg.h | 14 +++++++------- src/mainboard/supermicro/h8scm/sb700_cfg.h | 14 +++++++------- src/mainboard/tyan/s8226/sb700_cfg.h | 14 +++++++------- 11 files changed, 77 insertions(+), 77 deletions(-) diff --git a/src/mainboard/advansus/a785e-i/platform_cfg.h b/src/mainboard/advansus/a785e-i/platform_cfg.h index 98e2c94..8b90d57 100644 --- a/src/mainboard/advansus/a785e-i/platform_cfg.h +++ b/src/mainboard/advansus/a785e-i/platform_cfg.h @@ -56,7 +56,7 @@ /** * @def SB_HPET_TIMER - * @breif + * @brief * 0 - Disable hpet * 1 - Enable hpet */ @@ -79,7 +79,7 @@ /** * @def PCI_CLOCK_CTRL - * @breif bit[0-4] used for PCI Slots Clock Control, + * @brief bit[0-4] used for PCI Slots Clock Control, * 0 - disable * 1 - enable * PCI SLOT 0 define at BIT0 @@ -92,26 +92,26 @@ /** * @def SATA_CONTROLLER - * @breif INCHIP Sata Controller + * @brief INCHIP Sata Controller */ #define SATA_CONTROLLER CIMX_OPTION_ENABLED /** * @def SATA_MODE - * @breif INCHIP Sata Controller Mode + * @brief INCHIP Sata Controller Mode * NOTE: DO NOT ALLOW SATA & IDE use same mode */ #define SATA_MODE NATIVE_IDE_MODE /** - * @breif INCHIP Sata IDE Controller Mode + * @brief INCHIP Sata IDE Controller Mode */ #define IDE_LEGACY_MODE 0 #define IDE_NATIVE_MODE 1 /** * @def SATA_IDE_MODE - * @breif INCHIP Sata IDE Controller Mode + * @brief INCHIP Sata IDE Controller Mode * NOTE: DO NOT ALLOW SATA & IDE use same mode */ #define SATA_IDE_MODE IDE_LEGACY_MODE @@ -155,7 +155,7 @@ #define AZALIA_ENABLE 2 /** - * @breif INCHIP HDA controller + * @brief INCHIP HDA controller */ #define AZALIA_CONTROLLER AZALIA_AUTO diff --git a/src/mainboard/amd/dinar/sb700_cfg.h b/src/mainboard/amd/dinar/sb700_cfg.h index 038e7e7..0073ecd 100644 --- a/src/mainboard/amd/dinar/sb700_cfg.h +++ b/src/mainboard/amd/dinar/sb700_cfg.h @@ -61,7 +61,7 @@ /** * @def SB_HPET_TIMER - * @breif + * @brief * 0 - Disable hpet * 1 - Enable hpet */ @@ -84,7 +84,7 @@ /** * @def PCI_CLOCK_CTRL - * @breif bit[0-4] used for PCI Slots Clock Control, + * @brief bit[0-4] used for PCI Slots Clock Control, * 0 - disable * 1 - enable * PCI SLOT 0 define at BIT0 @@ -97,7 +97,7 @@ /** * @def SATA_CONTROLLER - * @breif INCHIP Sata Controller + * @brief INCHIP Sata Controller */ #ifndef SATA_CONTROLLER #define SATA_CONTROLLER 1 @@ -105,7 +105,7 @@ /** * @def SATA_MODE - * @breif INCHIP Sata Controller Mode + * @brief INCHIP Sata Controller Mode * NOTE: DO NOT ALLOW SATA & IDE use same mode */ #ifndef SATA_MODE @@ -113,14 +113,14 @@ #endif /** - * @breif INCHIP Sata IDE Controller Mode + * @brief INCHIP Sata IDE Controller Mode */ #define IDE_LEGACY_MODE 0 #define IDE_NATIVE_MODE 1 /** * @def SATA_IDE_MODE - * @breif INCHIP Sata IDE Controller Mode + * @brief INCHIP Sata IDE Controller Mode * NOTE: DO NOT ALLOW SATA & IDE use same mode */ #ifndef SATA_IDE_MODE @@ -163,7 +163,7 @@ #define AZALIA_ENABLE 2 /** - * @breif INCHIP HDA controller + * @brief INCHIP HDA controller */ #ifndef AZALIA_CONTROLLER #define AZALIA_CONTROLLER AZALIA_AUTO diff --git a/src/mainboard/amd/inagua/platform_cfg.h b/src/mainboard/amd/inagua/platform_cfg.h index dd0251f..88526db 100644 --- a/src/mainboard/amd/inagua/platform_cfg.h +++ b/src/mainboard/amd/inagua/platform_cfg.h @@ -58,7 +58,7 @@ /** * @def SB_HPET_TIMER - * @breif + * @brief * 0 - Disable hpet * 1 - Enable hpet */ @@ -81,7 +81,7 @@ /** * @def PCI_CLOCK_CTRL - * @breif bit[0-4] used for PCI Slots Clock Control, + * @brief bit[0-4] used for PCI Slots Clock Control, * 0 - disable * 1 - enable * PCI SLOT 0 define at BIT0 @@ -94,26 +94,26 @@ /** * @def SATA_CONTROLLER - * @breif INCHIP Sata Controller + * @brief INCHIP Sata Controller */ #define SATA_CONTROLLER CIMX_OPTION_ENABLED /** * @def SATA_MODE - * @breif INCHIP Sata Controller Mode + * @brief INCHIP Sata Controller Mode * NOTE: DO NOT ALLOW SATA & IDE use same mode */ #define SATA_MODE CONFIG_SB800_SATA_MODE /** - * @breif INCHIP Sata IDE Controller Mode + * @brief INCHIP Sata IDE Controller Mode */ #define IDE_LEGACY_MODE 0 #define IDE_NATIVE_MODE 1 /** * @def SATA_IDE_MODE - * @breif INCHIP Sata IDE Controller Mode + * @brief INCHIP Sata IDE Controller Mode * NOTE: DO NOT ALLOW SATA & IDE use same mode */ #define SATA_IDE_MODE IDE_LEGACY_MODE @@ -157,7 +157,7 @@ #define AZALIA_ENABLE 2 /** - * @breif INCHIP HDA controller + * @brief INCHIP HDA controller */ #define AZALIA_CONTROLLER AZALIA_AUTO diff --git a/src/mainboard/amd/persimmon/platform_cfg.h b/src/mainboard/amd/persimmon/platform_cfg.h index 7051e7d..8e32894 100644 --- a/src/mainboard/amd/persimmon/platform_cfg.h +++ b/src/mainboard/amd/persimmon/platform_cfg.h @@ -58,7 +58,7 @@ /** * @def SB_HPET_TIMER - * @breif + * @brief * 0 - Disable hpet * 1 - Enable hpet */ @@ -81,7 +81,7 @@ /** * @def PCI_CLOCK_CTRL - * @breif bit[0-4] used for PCI Slots Clock Control, + * @brief bit[0-4] used for PCI Slots Clock Control, * 0 - disable * 1 - enable * PCI SLOT 0 define at BIT0 @@ -94,26 +94,26 @@ /** * @def SATA_CONTROLLER - * @breif INCHIP Sata Controller + * @brief INCHIP Sata Controller */ #define SATA_CONTROLLER CIMX_OPTION_ENABLED /** * @def SATA_MODE - * @breif INCHIP Sata Controller Mode + * @brief INCHIP Sata Controller Mode * NOTE: DO NOT ALLOW SATA & IDE use same mode */ #define SATA_MODE CONFIG_SB800_SATA_MODE /** - * @breif INCHIP Sata IDE Controller Mode + * @brief INCHIP Sata IDE Controller Mode */ #define IDE_LEGACY_MODE 0 #define IDE_NATIVE_MODE 1 /** * @def SATA_IDE_MODE - * @breif INCHIP Sata IDE Controller Mode + * @brief INCHIP Sata IDE Controller Mode * NOTE: DO NOT ALLOW SATA & IDE use same mode */ #define SATA_IDE_MODE IDE_LEGACY_MODE @@ -157,7 +157,7 @@ #define AZALIA_ENABLE 2 /** - * @breif INCHIP HDA controller + * @brief INCHIP HDA controller */ #define AZALIA_CONTROLLER AZALIA_AUTO diff --git a/src/mainboard/amd/south_station/platform_cfg.h b/src/mainboard/amd/south_station/platform_cfg.h index 1c8506b..a5f9838 100644 --- a/src/mainboard/amd/south_station/platform_cfg.h +++ b/src/mainboard/amd/south_station/platform_cfg.h @@ -58,7 +58,7 @@ /** * @def SB_HPET_TIMER - * @breif + * @brief * 0 - Disable hpet * 1 - Enable hpet */ @@ -81,7 +81,7 @@ /** * @def PCI_CLOCK_CTRL - * @breif bit[0-4] used for PCI Slots Clock Control, + * @brief bit[0-4] used for PCI Slots Clock Control, * 0 - disable * 1 - enable * PCI SLOT 0 define at BIT0 @@ -94,26 +94,26 @@ /** * @def SATA_CONTROLLER - * @breif INCHIP Sata Controller + * @brief INCHIP Sata Controller */ #define SATA_CONTROLLER CIMX_OPTION_ENABLED /** * @def SATA_MODE - * @breif INCHIP Sata Controller Mode + * @brief INCHIP Sata Controller Mode * NOTE: DO NOT ALLOW SATA & IDE use same mode */ #define SATA_MODE CONFIG_SB800_SATA_MODE /** - * @breif INCHIP Sata IDE Controller Mode + * @brief INCHIP Sata IDE Controller Mode */ #define IDE_LEGACY_MODE 0 #define IDE_NATIVE_MODE 1 /** * @def SATA_IDE_MODE - * @breif INCHIP Sata IDE Controller Mode + * @brief INCHIP Sata IDE Controller Mode * NOTE: DO NOT ALLOW SATA & IDE use same mode */ #define SATA_IDE_MODE IDE_LEGACY_MODE @@ -157,7 +157,7 @@ #define AZALIA_ENABLE 2 /** - * @breif INCHIP HDA controller + * @brief INCHIP HDA controller */ #define AZALIA_CONTROLLER AZALIA_AUTO diff --git a/src/mainboard/amd/union_station/platform_cfg.h b/src/mainboard/amd/union_station/platform_cfg.h index 1c8506b..a5f9838 100644 --- a/src/mainboard/amd/union_station/platform_cfg.h +++ b/src/mainboard/amd/union_station/platform_cfg.h @@ -58,7 +58,7 @@ /** * @def SB_HPET_TIMER - * @breif + * @brief * 0 - Disable hpet * 1 - Enable hpet */ @@ -81,7 +81,7 @@ /** * @def PCI_CLOCK_CTRL - * @breif bit[0-4] used for PCI Slots Clock Control, + * @brief bit[0-4] used for PCI Slots Clock Control, * 0 - disable * 1 - enable * PCI SLOT 0 define at BIT0 @@ -94,26 +94,26 @@ /** * @def SATA_CONTROLLER - * @breif INCHIP Sata Controller + * @brief INCHIP Sata Controller */ #define SATA_CONTROLLER CIMX_OPTION_ENABLED /** * @def SATA_MODE - * @breif INCHIP Sata Controller Mode + * @brief INCHIP Sata Controller Mode * NOTE: DO NOT ALLOW SATA & IDE use same mode */ #define SATA_MODE CONFIG_SB800_SATA_MODE /** - * @breif INCHIP Sata IDE Controller Mode + * @brief INCHIP Sata IDE Controller Mode */ #define IDE_LEGACY_MODE 0 #define IDE_NATIVE_MODE 1 /** * @def SATA_IDE_MODE - * @breif INCHIP Sata IDE Controller Mode + * @brief INCHIP Sata IDE Controller Mode * NOTE: DO NOT ALLOW SATA & IDE use same mode */ #define SATA_IDE_MODE IDE_LEGACY_MODE @@ -157,7 +157,7 @@ #define AZALIA_ENABLE 2 /** - * @breif INCHIP HDA controller + * @brief INCHIP HDA controller */ #define AZALIA_CONTROLLER AZALIA_AUTO diff --git a/src/mainboard/asus/m5a88-v/platform_cfg.h b/src/mainboard/asus/m5a88-v/platform_cfg.h index 00f9695..40741d9 100644 --- a/src/mainboard/asus/m5a88-v/platform_cfg.h +++ b/src/mainboard/asus/m5a88-v/platform_cfg.h @@ -56,7 +56,7 @@ /** * @def SB_HPET_TIMER - * @breif + * @brief * 0 - Disable hpet * 1 - Enable hpet */ @@ -79,7 +79,7 @@ /** * @def PCI_CLOCK_CTRL - * @breif bit[0-4] used for PCI Slots Clock Control, + * @brief bit[0-4] used for PCI Slots Clock Control, * 0 - disable * 1 - enable * PCI SLOT 0 define at BIT0 @@ -92,26 +92,26 @@ /** * @def SATA_CONTROLLER - * @breif INCHIP Sata Controller + * @brief INCHIP Sata Controller */ #define SATA_CONTROLLER CIMX_OPTION_ENABLED /** * @def SATA_MODE - * @breif INCHIP Sata Controller Mode + * @brief INCHIP Sata Controller Mode * NOTE: DO NOT ALLOW SATA & IDE use same mode */ #define SATA_MODE NATIVE_IDE_MODE /** - * @breif INCHIP Sata IDE Controller Mode + * @brief INCHIP Sata IDE Controller Mode */ #define IDE_LEGACY_MODE 0 #define IDE_NATIVE_MODE 1 /** * @def SATA_IDE_MODE - * @breif INCHIP Sata IDE Controller Mode + * @brief INCHIP Sata IDE Controller Mode * NOTE: DO NOT ALLOW SATA & IDE use same mode */ #define SATA_IDE_MODE IDE_LEGACY_MODE @@ -155,7 +155,7 @@ #define AZALIA_ENABLE 2 /** - * @breif INCHIP HDA controller + * @brief INCHIP HDA controller */ #define AZALIA_CONTROLLER AZALIA_AUTO diff --git a/src/mainboard/avalue/eax-785e/platform_cfg.h b/src/mainboard/avalue/eax-785e/platform_cfg.h index 1ce1c51..fd02f7d 100644 --- a/src/mainboard/avalue/eax-785e/platform_cfg.h +++ b/src/mainboard/avalue/eax-785e/platform_cfg.h @@ -58,7 +58,7 @@ /** * @def SB_HPET_TIMER - * @breif + * @brief * 0 - Disable hpet * 1 - Enable hpet */ @@ -81,7 +81,7 @@ /** * @def PCI_CLOCK_CTRL - * @breif bit[0-4] used for PCI Slots Clock Control, + * @brief bit[0-4] used for PCI Slots Clock Control, * 0 - disable * 1 - enable * PCI SLOT 0 define at BIT0 @@ -94,26 +94,26 @@ /** * @def SATA_CONTROLLER - * @breif INCHIP Sata Controller + * @brief INCHIP Sata Controller */ #define SATA_CONTROLLER CIMX_OPTION_ENABLED /** * @def SATA_MODE - * @breif INCHIP Sata Controller Mode + * @brief INCHIP Sata Controller Mode * NOTE: DO NOT ALLOW SATA & IDE use same mode */ #define SATA_MODE CONFIG_SB800_SATA_MODE /** - * @breif INCHIP Sata IDE Controller Mode + * @brief INCHIP Sata IDE Controller Mode */ #define IDE_LEGACY_MODE 0 #define IDE_NATIVE_MODE 1 /** * @def SATA_IDE_MODE - * @breif INCHIP Sata IDE Controller Mode + * @brief INCHIP Sata IDE Controller Mode * NOTE: DO NOT ALLOW SATA & IDE use same mode */ #define SATA_IDE_MODE IDE_LEGACY_MODE @@ -157,7 +157,7 @@ #define AZALIA_ENABLE 2 /** - * @breif INCHIP HDA controller + * @brief INCHIP HDA controller */ #define AZALIA_CONTROLLER AZALIA_AUTO diff --git a/src/mainboard/supermicro/h8qgi/sb700_cfg.h b/src/mainboard/supermicro/h8qgi/sb700_cfg.h index 42cd363..b01a086 100644 --- a/src/mainboard/supermicro/h8qgi/sb700_cfg.h +++ b/src/mainboard/supermicro/h8qgi/sb700_cfg.h @@ -61,7 +61,7 @@ /** * @def SB_HPET_TIMER - * @breif + * @brief * 0 - Disable hpet * 1 - Enable hpet */ @@ -84,7 +84,7 @@ /** * @def PCI_CLOCK_CTRL - * @breif bit[0-4] used for PCI Slots Clock Control, + * @brief bit[0-4] used for PCI Slots Clock Control, * 0 - disable * 1 - enable * PCI SLOT 0 define at BIT0 @@ -97,7 +97,7 @@ /** * @def SATA_CONTROLLER - * @breif INCHIP Sata Controller + * @brief INCHIP Sata Controller */ #ifndef SATA_CONTROLLER #define SATA_CONTROLLER 1 @@ -105,7 +105,7 @@ /** * @def SATA_MODE - * @breif INCHIP Sata Controller Mode + * @brief INCHIP Sata Controller Mode * NOTE: DO NOT ALLOW SATA & IDE use same mode */ #ifndef SATA_MODE @@ -113,14 +113,14 @@ #endif /** - * @breif INCHIP Sata IDE Controller Mode + * @brief INCHIP Sata IDE Controller Mode */ #define IDE_LEGACY_MODE 0 #define IDE_NATIVE_MODE 1 /** * @def SATA_IDE_MODE - * @breif INCHIP Sata IDE Controller Mode + * @brief INCHIP Sata IDE Controller Mode * NOTE: DO NOT ALLOW SATA & IDE use same mode */ #ifndef SATA_IDE_MODE @@ -163,7 +163,7 @@ #define AZALIA_ENABLE 2 /** - * @breif INCHIP HDA controller + * @brief INCHIP HDA controller */ #ifndef AZALIA_CONTROLLER #define AZALIA_CONTROLLER AZALIA_AUTO diff --git a/src/mainboard/supermicro/h8scm/sb700_cfg.h b/src/mainboard/supermicro/h8scm/sb700_cfg.h index aac61ec..ea8766b 100644 --- a/src/mainboard/supermicro/h8scm/sb700_cfg.h +++ b/src/mainboard/supermicro/h8scm/sb700_cfg.h @@ -61,7 +61,7 @@ /** * @def SB_HPET_TIMER - * @breif + * @brief * 0 - Disable hpet * 1 - Enable hpet */ @@ -84,7 +84,7 @@ /** * @def PCI_CLOCK_CTRL - * @breif bit[0-4] used for PCI Slots Clock Control, + * @brief bit[0-4] used for PCI Slots Clock Control, * 0 - disable * 1 - enable * PCI SLOT 0 define at BIT0 @@ -97,7 +97,7 @@ /** * @def SATA_CONTROLLER - * @breif INCHIP Sata Controller + * @brief INCHIP Sata Controller */ #ifndef SATA_CONTROLLER #define SATA_CONTROLLER 1 @@ -105,7 +105,7 @@ /** * @def SATA_MODE - * @breif INCHIP Sata Controller Mode + * @brief INCHIP Sata Controller Mode * NOTE: DO NOT ALLOW SATA & IDE use same mode */ #ifndef SATA_MODE @@ -113,14 +113,14 @@ #endif /** - * @breif INCHIP Sata IDE Controller Mode + * @brief INCHIP Sata IDE Controller Mode */ #define IDE_LEGACY_MODE 0 #define IDE_NATIVE_MODE 1 /** * @def SATA_IDE_MODE - * @breif INCHIP Sata IDE Controller Mode + * @brief INCHIP Sata IDE Controller Mode * NOTE: DO NOT ALLOW SATA & IDE use same mode */ #ifndef SATA_IDE_MODE @@ -163,7 +163,7 @@ #define AZALIA_ENABLE 2 /** - * @breif INCHIP HDA controller + * @brief INCHIP HDA controller */ #ifndef AZALIA_CONTROLLER #define AZALIA_CONTROLLER AZALIA_AUTO diff --git a/src/mainboard/tyan/s8226/sb700_cfg.h b/src/mainboard/tyan/s8226/sb700_cfg.h index ddfa7df..a021a71 100644 --- a/src/mainboard/tyan/s8226/sb700_cfg.h +++ b/src/mainboard/tyan/s8226/sb700_cfg.h @@ -61,7 +61,7 @@ /** * @def SB_HPET_TIMER - * @breif + * @brief * 0 - Disable hpet * 1 - Enable hpet */ @@ -84,7 +84,7 @@ /** * @def PCI_CLOCK_CTRL - * @breif bit[0-4] used for PCI Slots Clock Control, + * @brief bit[0-4] used for PCI Slots Clock Control, * 0 - disable * 1 - enable * PCI SLOT 0 define at BIT0 @@ -97,7 +97,7 @@ /** * @def SATA_CONTROLLER - * @breif INCHIP Sata Controller + * @brief INCHIP Sata Controller */ #ifndef SATA_CONTROLLER #define SATA_CONTROLLER 1 @@ -105,7 +105,7 @@ /** * @def SATA_MODE - * @breif INCHIP Sata Controller Mode + * @brief INCHIP Sata Controller Mode * NOTE: DO NOT ALLOW SATA & IDE use same mode */ #ifndef SATA_MODE @@ -113,14 +113,14 @@ #endif /** - * @breif INCHIP Sata IDE Controller Mode + * @brief INCHIP Sata IDE Controller Mode */ #define IDE_LEGACY_MODE 0 #define IDE_NATIVE_MODE 1 /** * @def SATA_IDE_MODE - * @breif INCHIP Sata IDE Controller Mode + * @brief INCHIP Sata IDE Controller Mode * NOTE: DO NOT ALLOW SATA & IDE use same mode */ #ifndef SATA_IDE_MODE @@ -163,7 +163,7 @@ #define AZALIA_ENABLE 2 /** - * @breif INCHIP HDA controller + * @brief INCHIP HDA controller */ #ifndef AZALIA_CONTROLLER #define AZALIA_CONTROLLER AZALIA_AUTO

1 0

New patch to review for coreboot: 08da629 AMD boards: ACPI DSDT: Use COREBOOT for the OEM Table ID field
by Paul Menzel 21 Feb '13

21 Feb '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2472 -gerrit commit 08da6291b41333bb3313ed7fbbee8b214f56f7cf Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu Feb 21 15:54:50 2013 +0100 AMD boards: ACPI DSDT: Use COREBOOT for the OEM Table ID field The DSDT header contains the fields OEMID and OEM Table ID. See for example ACPI specification 4.0a [1] 5.2.11.1 Differentiated System Description Table (DSDT) on page 135. There Table 5-16 contains the descriptions. Field Byte Length Byte Offset Description =================================================== OEMID 6 10 OEM ID OEM Table ID 8 16 The manufacture model ID. Currently in coreboot there is no common method what to put in these fields. Mostly Intel based boards populate it with "CORE " ore "COREv4" and AMD based boards populate it with the board vendor and model number, abbreviated appropriately to fit into these fields. On most boards the proprietary vendor BIOS seems to leave these fields – displayed with `sudo dmidecode` under System Information – blank To Be Filled By O.E.M. and fill out the Base Board Information with the board vendor and model name. In [2] Jens Rottmann argues that the this is really just the table ID used for naming it and that »99% of the DSDT code is not board specific«. Both approaches seem to have their advantages, but using the second one, developers often seem to forget to update them (for example AMD Thather). The current situation is at least not optimal. and therefore at least unify the string in the OEM Table ID. If unifying the OEM ID is also a good idea this should be done too. If later on it should be decided that the board vendor and model should be used again, this should be somehow derived from Kconfig. The following command was used for the change [3]. $ git grep -l '\/\* TABLE ID \*\/' | xargs sed -i '/TABLE ID/s/"$[^"]*$"/"COREBOOT"/' This patch is split out from [2]. [1] http://www.acpi.info/spec40a.htm [2] http://review.coreboot.org/#/c/2464/ [3] http://stackoverflow.com/questions/5207838/sed-regex-matching-text-between-… Change-Id: Iec98c615ce37f928abc1b500eff5aa865d772cb2 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/advansus/a785e-i/dsdt.asl | 2 +- src/mainboard/amd/bimini_fam10/dsdt.asl | 2 +- src/mainboard/amd/dbm690t/dsdt.asl | 2 +- src/mainboard/amd/dinar/dsdt.asl | 2 +- src/mainboard/amd/inagua/dsdt.asl | 2 +- src/mainboard/amd/mahogany/dsdt.asl | 2 +- src/mainboard/amd/mahogany_fam10/dsdt.asl | 2 +- src/mainboard/amd/parmer/dsdt.asl | 2 +- src/mainboard/amd/persimmon/dsdt.asl | 2 +- src/mainboard/amd/pistachio/dsdt.asl | 2 +- src/mainboard/amd/south_station/dsdt.asl | 2 +- src/mainboard/amd/thatcher/dsdt.asl | 2 +- src/mainboard/amd/tilapia_fam10/dsdt.asl | 2 +- src/mainboard/amd/torpedo/dsdt.asl | 2 +- src/mainboard/amd/union_station/dsdt.asl | 2 +- src/mainboard/asrock/939a785gmh/dsdt.asl | 2 +- src/mainboard/asrock/e350m1/dsdt.asl | 2 +- src/mainboard/asus/m4a78-em/dsdt.asl | 2 +- src/mainboard/asus/m4a785-m/dsdt.asl | 2 +- src/mainboard/asus/m4a785t-m/dsdt.asl | 2 +- src/mainboard/asus/m5a88-v/dsdt.asl | 2 +- src/mainboard/avalue/eax-785e/dsdt.asl | 2 +- src/mainboard/gigabyte/ma785gm/dsdt.asl | 2 +- src/mainboard/gigabyte/ma785gmt/dsdt.asl | 2 +- src/mainboard/gigabyte/ma78gm/dsdt.asl | 2 +- src/mainboard/iei/kino-780am2-fam10/dsdt.asl | 2 +- src/mainboard/jetway/pa78vm5/dsdt.asl | 2 +- src/mainboard/supermicro/h8qgi/dsdt.asl | 2 +- src/mainboard/supermicro/h8scm/dsdt.asl | 2 +- src/mainboard/supermicro/h8scm_fam10/dsdt.asl | 2 +- src/mainboard/technexion/tim5690/dsdt.asl | 2 +- src/mainboard/technexion/tim8690/dsdt.asl | 2 +- src/mainboard/tyan/s8226/dsdt.asl | 2 +- 33 files changed, 33 insertions(+), 33 deletions(-) diff --git a/src/mainboard/advansus/a785e-i/dsdt.asl b/src/mainboard/advansus/a785e-i/dsdt.asl index 52ca3b9..7caedd0 100644 --- a/src/mainboard/advansus/a785e-i/dsdt.asl +++ b/src/mainboard/advansus/a785e-i/dsdt.asl @@ -23,7 +23,7 @@ DefinitionBlock ( "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ "ADVANSUS", /* OEMID */ - "A785E-I ", /* TABLE ID */ + "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ diff --git a/src/mainboard/amd/bimini_fam10/dsdt.asl b/src/mainboard/amd/bimini_fam10/dsdt.asl index e54723c..d0bba43 100644 --- a/src/mainboard/amd/bimini_fam10/dsdt.asl +++ b/src/mainboard/amd/bimini_fam10/dsdt.asl @@ -23,7 +23,7 @@ DefinitionBlock ( "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ "AMD ", /* OEMID */ - "BIMINI ", /* TABLE ID */ + "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ diff --git a/src/mainboard/amd/dbm690t/dsdt.asl b/src/mainboard/amd/dbm690t/dsdt.asl index 2b1aab8..da1a516 100644 --- a/src/mainboard/amd/dbm690t/dsdt.asl +++ b/src/mainboard/amd/dbm690t/dsdt.asl @@ -23,7 +23,7 @@ DefinitionBlock ( "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ "AMD ", /* OEMID */ - "DBM690T ", /* TABLE ID */ + "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ diff --git a/src/mainboard/amd/dinar/dsdt.asl b/src/mainboard/amd/dinar/dsdt.asl index 7df090f..575ce6c 100644 --- a/src/mainboard/amd/dinar/dsdt.asl +++ b/src/mainboard/amd/dinar/dsdt.asl @@ -23,7 +23,7 @@ DefinitionBlock ( "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ "AMD ", /* OEMID */ - "DINAR ", /* TABLE ID */ + "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ diff --git a/src/mainboard/amd/inagua/dsdt.asl b/src/mainboard/amd/inagua/dsdt.asl index 46b92f1..c7b44d0 100644 --- a/src/mainboard/amd/inagua/dsdt.asl +++ b/src/mainboard/amd/inagua/dsdt.asl @@ -23,7 +23,7 @@ DefinitionBlock ( "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ "AMD ", /* OEMID */ - "INAGUA ", /* TABLE ID */ + "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ diff --git a/src/mainboard/amd/mahogany/dsdt.asl b/src/mainboard/amd/mahogany/dsdt.asl index 4920e2f..50b2ba9 100644 --- a/src/mainboard/amd/mahogany/dsdt.asl +++ b/src/mainboard/amd/mahogany/dsdt.asl @@ -23,7 +23,7 @@ DefinitionBlock ( "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ "AMD ", /* OEMID */ - "MAHOGANY", /* TABLE ID */ + "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ diff --git a/src/mainboard/amd/mahogany_fam10/dsdt.asl b/src/mainboard/amd/mahogany_fam10/dsdt.asl index d50027b..6993593 100644 --- a/src/mainboard/amd/mahogany_fam10/dsdt.asl +++ b/src/mainboard/amd/mahogany_fam10/dsdt.asl @@ -23,7 +23,7 @@ DefinitionBlock ( "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ "AMD ", /* OEMID */ - "MAHOGANY", /* TABLE ID */ + "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ diff --git a/src/mainboard/amd/parmer/dsdt.asl b/src/mainboard/amd/parmer/dsdt.asl index 4b600e8..446c12f 100644 --- a/src/mainboard/amd/parmer/dsdt.asl +++ b/src/mainboard/amd/parmer/dsdt.asl @@ -23,7 +23,7 @@ DefinitionBlock ( "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ "AMD ", /* OEMID */ - "PARMER ", /* TABLE ID */ + "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ diff --git a/src/mainboard/amd/persimmon/dsdt.asl b/src/mainboard/amd/persimmon/dsdt.asl index dd7b4b1..c7b44d0 100644 --- a/src/mainboard/amd/persimmon/dsdt.asl +++ b/src/mainboard/amd/persimmon/dsdt.asl @@ -23,7 +23,7 @@ DefinitionBlock ( "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ "AMD ", /* OEMID */ - "PERSIMMO", /* TABLE ID */ + "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ diff --git a/src/mainboard/amd/pistachio/dsdt.asl b/src/mainboard/amd/pistachio/dsdt.asl index 045db08..a7a9bff 100644 --- a/src/mainboard/amd/pistachio/dsdt.asl +++ b/src/mainboard/amd/pistachio/dsdt.asl @@ -23,7 +23,7 @@ DefinitionBlock ( "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ "AMD ", /* OEMID */ - "PISTACHI", /* TABLE ID */ + "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ diff --git a/src/mainboard/amd/south_station/dsdt.asl b/src/mainboard/amd/south_station/dsdt.asl index 958295b..c7b44d0 100644 --- a/src/mainboard/amd/south_station/dsdt.asl +++ b/src/mainboard/amd/south_station/dsdt.asl @@ -23,7 +23,7 @@ DefinitionBlock ( "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ "AMD ", /* OEMID */ - "SOUTHSTN", /* TABLE ID */ + "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ diff --git a/src/mainboard/amd/thatcher/dsdt.asl b/src/mainboard/amd/thatcher/dsdt.asl index 4b600e8..446c12f 100644 --- a/src/mainboard/amd/thatcher/dsdt.asl +++ b/src/mainboard/amd/thatcher/dsdt.asl @@ -23,7 +23,7 @@ DefinitionBlock ( "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ "AMD ", /* OEMID */ - "PARMER ", /* TABLE ID */ + "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ diff --git a/src/mainboard/amd/tilapia_fam10/dsdt.asl b/src/mainboard/amd/tilapia_fam10/dsdt.asl index 666cebe..61e4574 100644 --- a/src/mainboard/amd/tilapia_fam10/dsdt.asl +++ b/src/mainboard/amd/tilapia_fam10/dsdt.asl @@ -23,7 +23,7 @@ DefinitionBlock ( "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ "AMD ", /* OEMID */ - "TILAPIA ", /* TABLE ID */ + "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ diff --git a/src/mainboard/amd/torpedo/dsdt.asl b/src/mainboard/amd/torpedo/dsdt.asl index 61ceca0..d1522f7 100755 --- a/src/mainboard/amd/torpedo/dsdt.asl +++ b/src/mainboard/amd/torpedo/dsdt.asl @@ -23,7 +23,7 @@ DefinitionBlock ( "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ "AMD ", /* OEMID */ - "TORPEDO ", /* TABLE ID */ + "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ diff --git a/src/mainboard/amd/union_station/dsdt.asl b/src/mainboard/amd/union_station/dsdt.asl index 0752640..f56020a 100644 --- a/src/mainboard/amd/union_station/dsdt.asl +++ b/src/mainboard/amd/union_station/dsdt.asl @@ -23,7 +23,7 @@ DefinitionBlock ( "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ "AMD ", /* OEMID */ - "UNIONSTN", /* TABLE ID */ + "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ diff --git a/src/mainboard/asrock/939a785gmh/dsdt.asl b/src/mainboard/asrock/939a785gmh/dsdt.asl index a7c863f..58381e8 100644 --- a/src/mainboard/asrock/939a785gmh/dsdt.asl +++ b/src/mainboard/asrock/939a785gmh/dsdt.asl @@ -23,7 +23,7 @@ DefinitionBlock ( "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ "ASROCK", /* OEMID */ - "939A785GM", /* TABLE ID */ + "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ diff --git a/src/mainboard/asrock/e350m1/dsdt.asl b/src/mainboard/asrock/e350m1/dsdt.asl index 1cd88b8..e7e2b60 100644 --- a/src/mainboard/asrock/e350m1/dsdt.asl +++ b/src/mainboard/asrock/e350m1/dsdt.asl @@ -23,7 +23,7 @@ DefinitionBlock ( "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ "ASROCK", /* OEMID */ - "E350M1 ", /* TABLE ID */ + "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ diff --git a/src/mainboard/asus/m4a78-em/dsdt.asl b/src/mainboard/asus/m4a78-em/dsdt.asl index 0d08d29..3f03e0a 100644 --- a/src/mainboard/asus/m4a78-em/dsdt.asl +++ b/src/mainboard/asus/m4a78-em/dsdt.asl @@ -23,7 +23,7 @@ DefinitionBlock ( "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ "ASUS ", /* OEMID */ - "M4A78-EM ", /* TABLE ID */ + "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ diff --git a/src/mainboard/asus/m4a785-m/dsdt.asl b/src/mainboard/asus/m4a785-m/dsdt.asl index 7ea5672..3f03e0a 100644 --- a/src/mainboard/asus/m4a785-m/dsdt.asl +++ b/src/mainboard/asus/m4a785-m/dsdt.asl @@ -23,7 +23,7 @@ DefinitionBlock ( "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ "ASUS ", /* OEMID */ - "M4A785-M ", /* TABLE ID */ + "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ diff --git a/src/mainboard/asus/m4a785t-m/dsdt.asl b/src/mainboard/asus/m4a785t-m/dsdt.asl index 9e6ce88..6f22bda 100644 --- a/src/mainboard/asus/m4a785t-m/dsdt.asl +++ b/src/mainboard/asus/m4a785t-m/dsdt.asl @@ -23,7 +23,7 @@ DefinitionBlock ( "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ "ASUS", /* OEMID */ - "M4A785T ", /* TABLE ID */ + "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ diff --git a/src/mainboard/asus/m5a88-v/dsdt.asl b/src/mainboard/asus/m5a88-v/dsdt.asl index a248766..0beb7df 100644 --- a/src/mainboard/asus/m5a88-v/dsdt.asl +++ b/src/mainboard/asus/m5a88-v/dsdt.asl @@ -23,7 +23,7 @@ DefinitionBlock ( "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ "ASUS ", /* OEMID */ - "M5A88 ", /* TABLE ID */ + "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ diff --git a/src/mainboard/avalue/eax-785e/dsdt.asl b/src/mainboard/avalue/eax-785e/dsdt.asl index b835128..3811ab7 100644 --- a/src/mainboard/avalue/eax-785e/dsdt.asl +++ b/src/mainboard/avalue/eax-785e/dsdt.asl @@ -23,7 +23,7 @@ DefinitionBlock ( "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ "AVALUE ", /* OEMID */ - "EAX-785E", /* TABLE ID */ + "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ diff --git a/src/mainboard/gigabyte/ma785gm/dsdt.asl b/src/mainboard/gigabyte/ma785gm/dsdt.asl index 727b32e..0ed4040 100644 --- a/src/mainboard/gigabyte/ma785gm/dsdt.asl +++ b/src/mainboard/gigabyte/ma785gm/dsdt.asl @@ -23,7 +23,7 @@ DefinitionBlock ( "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ "GIGA ", /* OEMID */ - "MA785GM ", /* TABLE ID */ + "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ diff --git a/src/mainboard/gigabyte/ma785gmt/dsdt.asl b/src/mainboard/gigabyte/ma785gmt/dsdt.asl index a29bb2a..0ed4040 100644 --- a/src/mainboard/gigabyte/ma785gmt/dsdt.asl +++ b/src/mainboard/gigabyte/ma785gmt/dsdt.asl @@ -23,7 +23,7 @@ DefinitionBlock ( "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ "GIGA ", /* OEMID */ - "MA785GMT-UD2H", /* TABLE ID */ + "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ diff --git a/src/mainboard/gigabyte/ma78gm/dsdt.asl b/src/mainboard/gigabyte/ma78gm/dsdt.asl index c850b9e..0ed4040 100644 --- a/src/mainboard/gigabyte/ma78gm/dsdt.asl +++ b/src/mainboard/gigabyte/ma78gm/dsdt.asl @@ -23,7 +23,7 @@ DefinitionBlock ( "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ "GIGA ", /* OEMID */ - "MA78GM-US2H", /* TABLE ID */ + "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ diff --git a/src/mainboard/iei/kino-780am2-fam10/dsdt.asl b/src/mainboard/iei/kino-780am2-fam10/dsdt.asl index 1501731..2581fd1 100644 --- a/src/mainboard/iei/kino-780am2-fam10/dsdt.asl +++ b/src/mainboard/iei/kino-780am2-fam10/dsdt.asl @@ -23,7 +23,7 @@ DefinitionBlock ( "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ "IEI ", /* OEMID */ - "KINO ", /* TABLE ID */ + "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ diff --git a/src/mainboard/jetway/pa78vm5/dsdt.asl b/src/mainboard/jetway/pa78vm5/dsdt.asl index 8f75019..987b1d2 100644 --- a/src/mainboard/jetway/pa78vm5/dsdt.asl +++ b/src/mainboard/jetway/pa78vm5/dsdt.asl @@ -23,7 +23,7 @@ DefinitionBlock ( "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ "JETWAY", /* OEMID */ - "PA78VM5 ", /* TABLE ID */ + "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ diff --git a/src/mainboard/supermicro/h8qgi/dsdt.asl b/src/mainboard/supermicro/h8qgi/dsdt.asl index 2955eea..6dee4ea 100644 --- a/src/mainboard/supermicro/h8qgi/dsdt.asl +++ b/src/mainboard/supermicro/h8qgi/dsdt.asl @@ -23,7 +23,7 @@ DefinitionBlock ( "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ "AMD ", /* OEMID */ - "H8QGI ", /* TABLE ID */ + "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ diff --git a/src/mainboard/supermicro/h8scm/dsdt.asl b/src/mainboard/supermicro/h8scm/dsdt.asl index 0177aab..f0ebb70 100644 --- a/src/mainboard/supermicro/h8scm/dsdt.asl +++ b/src/mainboard/supermicro/h8scm/dsdt.asl @@ -23,7 +23,7 @@ DefinitionBlock ( "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ "AMD ", /* OEMID */ - "H8SCM ", /* TABLE ID */ + "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ diff --git a/src/mainboard/supermicro/h8scm_fam10/dsdt.asl b/src/mainboard/supermicro/h8scm_fam10/dsdt.asl index dd3c897..289a672 100644 --- a/src/mainboard/supermicro/h8scm_fam10/dsdt.asl +++ b/src/mainboard/supermicro/h8scm_fam10/dsdt.asl @@ -23,7 +23,7 @@ DefinitionBlock ( "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ "AMD ", /* OEMID */ - "H8SCM ", /* TABLE ID */ + "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ diff --git a/src/mainboard/technexion/tim5690/dsdt.asl b/src/mainboard/technexion/tim5690/dsdt.asl index 9279b5f..60eb8b4 100644 --- a/src/mainboard/technexion/tim5690/dsdt.asl +++ b/src/mainboard/technexion/tim5690/dsdt.asl @@ -23,7 +23,7 @@ DefinitionBlock ( "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ "TECHNEXION", /* OEMID */ - "TIM-5690", /* TABLE ID */ + "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ diff --git a/src/mainboard/technexion/tim8690/dsdt.asl b/src/mainboard/technexion/tim8690/dsdt.asl index b13d2ec..4e1441a 100644 --- a/src/mainboard/technexion/tim8690/dsdt.asl +++ b/src/mainboard/technexion/tim8690/dsdt.asl @@ -23,7 +23,7 @@ DefinitionBlock ( "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ "TECHNEXION", /* OEMID */ - "TIM-8690", /* TABLE ID */ + "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ diff --git a/src/mainboard/tyan/s8226/dsdt.asl b/src/mainboard/tyan/s8226/dsdt.asl index f26359f..cd10173 100644 --- a/src/mainboard/tyan/s8226/dsdt.asl +++ b/src/mainboard/tyan/s8226/dsdt.asl @@ -23,7 +23,7 @@ DefinitionBlock ( "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ "AMD ", /* OEMID */ - "S8226 ", /* TABLE ID */ + "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */

1 0

[RESEND] Some questions about SeaBIOS's native VGA drivers.
by Denis 'GNUtoo' Carikli 21 Feb '13

21 Feb '13

Hi, I'd like to replace the lenovo x60(supported by coreboot) non-free VGA option rom: I don't use it right now but that has serious drawbacks: * No graphics at all until the i915 kernel module is loaded (really user unfriendly), my main motivation to replace it... * No backlight control * nvramtool doesn't work anymore without using the -y option (not really important). I've created stub in SeaBIOS(there is an attached patch for that) for the i915 driver(it will be filled in later), however I don't know how to run the code: * I guess it creates an option rom that is in out/vgabios.bin and that I've to include it trough one of the various ways(let seabios pick it, run it in coreboot, run it in coreboot trough YABEL for debugging etc...)? right? romheaders seem to think that the option rom is valid(more on it later). I guess YABEL also thinks it's valid. I guess SeaBIOS out/bios.bin.elf doesn't link that option rom inside SeaBIOS... * it doesn't print a thing, I've CONFIG_DEBUG_LEVEL=2 and there is the following in the driver stub: dprintf(1, "i915vga_setup: VGA init...\n"); So I've tried the YABEL way with debugging enabled and here's the result: [...] Normal boot. PCI: 00:02.0 init CBFS: Looking for 'pci8086,27a2.rom' starting from 0x0. CBFS: (unmatched file @0x0: cmos_layout.bin) CBFS: (unmatched file @0x640: fallback/romstage) CBFS: (unmatched file @0xb500: fallback/coreboot_ram) CBFS: (unmatched file @0x2d200: fallback/payload) CBFS: (unmatched file @0x39a80: config) CBFS: (unmatched file @0x3a9c0: ) CBFS: (unmatched file @0x3ff80: normal/romstage) CBFS: (unmatched file @0x4ae80: normal/coreboot_ram) CBFS: (unmatched file @0x6cb80: normal/payload) CBFS: Found file (offset=0x79af8, len=33280). In CBFS, ROM address for PCI: 00:02.0 = ffe79af8 PCI expansion ROM, signature 0xaa55, INIT size 0x8200, data ptr 0x4930 PCI ROM image, vendor ID 8086, device ID 27a2, PCI ROM image, Class Code 030000, Code Type 00 Copying VGA ROM Image from ffe79af8 to 0xc0000, 0x8200 bytes [long wait] PCI: 00:02.1 init CBFS: Looking for 'cmos_layout.bin' starting from 0x0. CBFS: Found file (offset=0x28, len=1560). PCI: 00:1b.0 init [...] It doesn't seem to print a thing...and YABEL is pretty silent and should really not be that silent according to the YABEL debug options: CONFIG_X86EMU_DEBUG=y CONFIG_X86EMU_DEBUG_JMP=y # CONFIG_X86EMU_DEBUG_TRACE is not set CONFIG_X86EMU_DEBUG_PNP=y CONFIG_X86EMU_DEBUG_DISK=y CONFIG_X86EMU_DEBUG_PMM=y CONFIG_X86EMU_DEBUG_VBE=y CONFIG_X86EMU_DEBUG_INT10=y CONFIG_X86EMU_DEBUG_INTERRUPTS=y CONFIG_X86EMU_DEBUG_CHECK_VMEM_ACCESS=y CONFIG_X86EMU_DEBUG_MEM=y CONFIG_X86EMU_DEBUG_IO=y Denis.

2 2

Patch merged into coreboot/master: 3138bb8 Persimmon: dimmSpd.c: Use spaces for alignment of if-predicate
by gerrit＠coreboot.org 21 Feb '13

21 Feb '13

the following patch was just integrated into master: commit 3138bb875c57c3962cd0ee00e0e297af1a315108 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu Feb 21 14:01:39 2013 +0100 Persimmon: dimmSpd.c: Use spaces for alignment of if-predicate The relational operators in the if-predicate are aligned in all `dimmSpd.c` files so revert part of the change in commit 36abff1dc8e74beafa47ad83de17416681970916 Author: Marc Jones <marcj303(a)gmail.com> Date: Mon Nov 7 23:26:14 2011 -0700 Cleanup Persimmon mainboard whitespace. Reviewed-on: http://review.coreboot.org/427 to remove the incorrectly introduced tabs and to unify that. It might contradict the current coding style but it is even used in the latest code as seen in the following file. src/northbridge/amd/agesa/family15tn/dimmSpd.c Change-Id: Ib611267f99090d0830bdc2319527389f193ea1eb Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2471 Reviewed-by: Alvaro G. <andor(a)pierdelacabeza.com> Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Thu Feb 21 14:44:14 2013, giving +1 Reviewed-By: Paul Menzel <paulepanter(a)users.sourceforge.net> at Thu Feb 21 14:51:05 2013, giving +2 See http://review.coreboot.org/2471 for details. -gerrit

1 0

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coreboot February 2013