coreboot February 2013

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New patch to review for coreboot: 68327b9 Tyan S8226: Fix integer truncated warning
by Martin Roth 19 Feb '13

19 Feb '13

Martin Roth (martin.roth(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2452 -gerrit commit 68327b9ffb3e9d3663afb07ab6058e280a8b3023 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Mon Feb 18 21:42:18 2013 -0700 Tyan S8226: Fix integer truncated warning Fix Warning: sb700_cfg.c:129, GNU Compiler 4 (gcc), Priority: Normal large integer implicitly truncated to unsigned type [-Woverflow] The issue here was that an 8 bit value was being placed into a 2-bit bitfield. The 8 bit value 0x2A was being used incorrectly - I believe the original intent of this value was to enable the SDIN pins 0, 1, & 2. Because it was getting truncated as it was put into AzaliaSdin0, this wasn't happening and only SDIN0 was being enabled. UINT32 AzaliaSdin0 :2; //6 UINT32 AzaliaSdin1 :2; //8 UINT32 AzaliaSdin2 :2; //10 UINT32 AzaliaSdin3 :2; //12 * SDIN0 is define at BIT0 & BIT1 * 00 - GPIO PIN * 01 - Reserved * 10 - As a Azalia SDIN pin I am leaving only SDIN0 enabled at this point to as not change the actual behavior on the platform. Change-Id: Icaeb956926309dbfb5af25a36ccb842877e17a34 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/mainboard/tyan/s8226/sb700_cfg.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/mainboard/tyan/s8226/sb700_cfg.h b/src/mainboard/tyan/s8226/sb700_cfg.h index 45d7a92..ddfa7df 100644 --- a/src/mainboard/tyan/s8226/sb700_cfg.h +++ b/src/mainboard/tyan/s8226/sb700_cfg.h @@ -191,8 +191,7 @@ * SDIN3 is define at BIT6 & BIT7 */ #ifndef AZALIA_SDIN_PIN -//#define AZALIA_SDIN_PIN 0xAA -#define AZALIA_SDIN_PIN 0x2A +#define AZALIA_SDIN_PIN 0x02 #endif /**

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New patch to review for coreboot: fccd63e Tyan S8226: Fix printk warnings
by Martin Roth 19 Feb '13

19 Feb '13

Martin Roth (martin.roth(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2451 -gerrit commit fccd63eb23701b56de2b96142392cd7021eebf13 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Mon Feb 18 21:33:04 2013 -0700 Tyan S8226: Fix printk warnings Fix 84 warnings all like this one: agesawrapper.c:289, GNU Compiler 4 (gcc), Priority: Normal format '%lu' expects argument of type 'long unsigned int', but argument 3 has type 'UINT32' [-Wformat] Fixed by getting rid of the l length specifier and casting to unsigned int. Change-Id: Ic143c1034f760fa5efb2220aa33861e399ddd708 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/mainboard/tyan/s8226/agesawrapper.c | 220 ++++++++++++++++---------------- 1 file changed, 113 insertions(+), 107 deletions(-) diff --git a/src/mainboard/tyan/s8226/agesawrapper.c b/src/mainboard/tyan/s8226/agesawrapper.c index c8620a7..305ac28 100644 --- a/src/mainboard/tyan/s8226/agesawrapper.c +++ b/src/mainboard/tyan/s8226/agesawrapper.c @@ -286,7 +286,7 @@ UINT32 agesawrapper_amdinitearly(VOID) GetCpuServicesOfCurrentCore((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &AmdParamStruct.StdHeader); FamilySpecificServices->GetTscRate(FamilySpecificServices, &TscRateInMhz, &AmdParamStruct.StdHeader); - printk(BIOS_DEBUG, "BSP Frequency: %luMHz\n", TscRateInMhz); + printk(BIOS_DEBUG, "BSP Frequency: %uMHz\n", (unsigned int)TscRateInMhz); AmdReleaseStruct(&AmdParamStruct); return (UINT32)status; @@ -339,7 +339,7 @@ UINT32 agesawrapper_amdinitpost(VOID) GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &AmdParamStruct.StdHeader); FamilySpecificServices->GetTscRate (FamilySpecificServices, &TscRateInMhz, &AmdParamStruct.StdHeader); - printk(BIOS_DEBUG, "BSP Frequency: %luMHz\n", TscRateInMhz); + printk(BIOS_DEBUG, "BSP Frequency: %uMHz\n", (unsigned int)TscRateInMhz); return (UINT32)status; } @@ -547,47 +547,47 @@ static void agesa_alert(EVENT_PARAMS *event) { switch (event->EventInfo) { case MEM_ALERT_USER_TMG_MODE_OVERRULED: - printk(BIOS_DEBUG, "Socket %lx Dct %lx Channel %lx " + printk(BIOS_DEBUG, "Socket %x Dct %x Channel %x " "TIMING_MODE_SPECIFIC is requested but can not be applied to current configurations.\n", - event->DataParam1, - event->DataParam2, - event->DataParam3); + (unsigned int)event->DataParam1, + (unsigned int)event->DataParam2, + (unsigned int)event->DataParam3); break; case MEM_ALERT_ORG_MISMATCH_DIMM: - printk(BIOS_DEBUG, "Socket %lx Dct %lx Channel %lx " + printk(BIOS_DEBUG, "Socket %x Dct %x Channel %x " "DIMM organization miss-match\n", - event->DataParam1, - event->DataParam2, - event->DataParam3); + (unsigned int)event->DataParam1, + (unsigned int)event->DataParam2, + (unsigned int)event->DataParam3); break; case MEM_ALERT_BK_INT_DIS: - printk(BIOS_DEBUG, "Socket %lx Dct %lx Channel %lx " + printk(BIOS_DEBUG, "Socket %x Dct %x Channel %x " "Bank interleaving disable for internal issue\n", - event->DataParam1, - event->DataParam2, - event->DataParam3); + (unsigned int)event->DataParam1, + (unsigned int)event->DataParam2, + (unsigned int)event->DataParam3); break; case CPU_EVENT_BIST_ERROR: - printk(BIOS_DEBUG, "BIST error: %lx reported on Socket %lx Core %lx\n", - event->DataParam1, - event->DataParam2, - event->DataParam3); + printk(BIOS_DEBUG, "BIST error: %x reported on Socket %x Core %x\n", + (unsigned int)event->DataParam1, + (unsigned int)event->DataParam2, + (unsigned int)event->DataParam3); break; case HT_EVENT_HW_SYNCFLOOD: - printk(BIOS_DEBUG, "HT_EVENT_DATA_HW_SYNCFLOOD error on Socket %lx Link %lx\n", - event->DataParam1, - event->DataParam2); + printk(BIOS_DEBUG, "HT_EVENT_DATA_HW_SYNCFLOOD error on Socket %x Link %x\n", + (unsigned int)event->DataParam1, + (unsigned int)event->DataParam2); break; case HT_EVENT_HW_HTCRC: - printk(BIOS_DEBUG, "HT_EVENT_HW_HTCRC error on Socket %lx Link %lx Lanemask:%lx\n", - event->DataParam1, - event->DataParam2, - event->DataParam3); + printk(BIOS_DEBUG, "HT_EVENT_HW_HTCRC error on Socket %x Link %x Lanemask:%x\n", + (unsigned int)event->DataParam1, + (unsigned int)event->DataParam2, + (unsigned int)event->DataParam3); break; default: @@ -612,10 +612,10 @@ static void agesa_warning(EVENT_PARAMS *event) switch (event->EventInfo >> 24) { case 0x04: - printk(BIOS_DEBUG, "Memory: Socket %lx Dct %lx Channel%lx ", - event->DataParam1, - event->DataParam2, - event->DataParam3); + printk(BIOS_DEBUG, "Memory: Socket %x Dct %x Channel%x ", + (unsigned int)event->DataParam1, + (unsigned int)event->DataParam2, + (unsigned int)event->DataParam3); break; case 0x08: @@ -712,24 +712,24 @@ static void agesa_warning(EVENT_PARAMS *event) } else if ((event->EventInfo & 0x000000FF) == 0x03) { printk(BIOS_DEBUG, "AGESA_CACHE_REGIONS_ACROSS_4GB\n"); } - printk(BIOS_DEBUG, "cache region index:%lx, start:%lx size:%lx\n", - event->DataParam1, - event->DataParam2, - event->DataParam3); + printk(BIOS_DEBUG, "cache region index:%x, start:%x size:%x\n", + (unsigned int)event->DataParam1, + (unsigned int)event->DataParam2, + (unsigned int)event->DataParam3); break; case CPU_WARNING_ADJUSTED_LEVELING_MODE: printk(BIOS_DEBUG, "CPU_WARNING_ADJUSTED_LEVELING_MODE " - "requested: %lx, actual level:%lx\n", - event->DataParam1, - event->DataParam2); + "requested: %x, actual level:%x\n", + (unsigned int)event->DataParam1, + (unsigned int)event->DataParam2); break; case CPU_EVENT_PM_PSTATE_OVERCURRENT: printk(BIOS_DEBUG, "CPU_EVENT_PM_PSTATE_OVERCURRENT " - "Socket: %lx, Pstate:%lx\n", - event->DataParam1, - event->DataParam2); + "Socket: %x, Pstate:%x\n", + (unsigned int)event->DataParam1, + (unsigned int)event->DataParam2); break; case CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG: @@ -745,34 +745,34 @@ static void agesa_warning(EVENT_PARAMS *event) */ case HT_EVENT_OPT_REQUIRED_CAP_RETRY: - printk(BIOS_DEBUG, "HT_EVENT_OPT_REQUIRED_CAP_RETRY, Socket %lx Link %lx Depth %lx\n", + printk(BIOS_DEBUG, "HT_EVENT_OPT_REQUIRED_CAP_RETRY, Socket %x Link %x Depth %x\n", event->DataParam1, event->DataParam2, event->DataParam3); break; case HT_EVENT_OPT_REQUIRED_CAP_GEN3: - printk(BIOS_DEBUG, "HT_EVENT_OPT_REQUIRED_CAP_GEN3, Socket %lx Link %lx Depth %lx\n", - event->DataParam1, - event->DataParam2, - event->DataParam3); + printk(BIOS_DEBUG, "HT_EVENT_OPT_REQUIRED_CAP_GEN3, Socket %x Link %x Depth %x\n", + (unsigned int)event->DataParam1, + (unsigned int)event->DataParam2, + (unsigned int)event->DataParam3); break; case HT_EVENT_OPT_UNUSED_LINKS: - printk(BIOS_DEBUG, "HT_EVENT_OPT_UNUSED_LINKS, SocketA%lx LinkA%lx SocketB%lx LinkB%lx\n", - event->DataParam1, - event->DataParam2, - event->DataParam3, - event->DataParam4); + printk(BIOS_DEBUG, "HT_EVENT_OPT_UNUSED_LINKS, SocketA%x LinkA%x SocketB%x LinkB%x\n", + (unsigned int)event->DataParam1, + (unsigned int)event->DataParam2, + (unsigned int)event->DataParam3, + (unsigned int)event->DataParam4); break; case HT_EVENT_OPT_LINK_PAIR_EXCEED: - printk(BIOS_DEBUG, "HT_EVENT_OPT_LINK_PAIR_EXCEED, SocketA%lx MasterLink%lx SocketB%lx AltLink%lx\n", + printk(BIOS_DEBUG, "HT_EVENT_OPT_LINK_PAIR_EXCEED, SocketA%x MasterLink%x SocketB%x AltLink%x\n", - event->DataParam1, - event->DataParam2, - event->DataParam3, - event->DataParam4); + (unsigned int)event->DataParam1, + (unsigned int)event->DataParam2, + (unsigned int)event->DataParam3, + (unsigned int)event->DataParam4); default: break; } @@ -786,10 +786,10 @@ static void agesa_error(EVENT_PARAMS *event) switch (event->EventInfo >> 24) { case 0x04: - printk(BIOS_DEBUG, "Memory: Socket %lx Dct %lx Channel%lx ", - event->DataParam1, - event->DataParam2, - event->DataParam3); + printk(BIOS_DEBUG, "Memory: Socket %x Dct %x Channel%x ", + (unsigned int)event->DataParam1, + (unsigned int)event->DataParam2, + (unsigned int)event->DataParam3); break; case 0x08: @@ -953,47 +953,47 @@ static void agesa_error(EVENT_PARAMS *event) } else if ((event->EventInfo & 0x000000FF) == 0x07) { printk(BIOS_DEBUG, "AGESA_DEALLOCATE_CACHE_REGIONS\n"); } - printk(BIOS_DEBUG, "cache region index:%lx, start:%lx size:%lx\n", - event->DataParam1, - event->DataParam2, - event->DataParam3); + printk(BIOS_DEBUG, "cache region index:%x, start:%x size:%x\n", + (unsigned int)event->DataParam1, + (unsigned int)event->DataParam2, + (unsigned int)event->DataParam3); break; case HT_EVENT_COH_NO_TOPOLOGY: - printk(BIOS_DEBUG, "no Matching Topology was found during coherent initializatio TotalHtNodes: %lx\n", - event->DataParam1); + printk(BIOS_DEBUG, "no Matching Topology was found during coherent initializatio TotalHtNodes: %x\n", + (unsigned int)event->DataParam1); break; case HT_EVENT_NCOH_BUID_EXCEED: - printk(BIOS_DEBUG, "there is a limit of 32 unit IDs per chain Socket%lx Link%lx Depth%lx" - "Current BUID: %lx, Unit Count: %lx\n", - event->DataParam1, - event->DataParam2, - event->DataParam3, - event->DataParam4 >> 16, - event->DataParam4 & 0x0000FFFF); + printk(BIOS_DEBUG, "there is a limit of 32 unit IDs per chain Socket%x Link%x Depth%x" + "Current BUID: %x, Unit Count: %x\n", + (unsigned int)event->DataParam1, + (unsigned int)event->DataParam2, + (unsigned int)event->DataParam3, + (unsigned int)event->DataParam4 >> 16, + (unsigned int)event->DataParam4 & 0x0000FFFF); break; case HT_EVENT_NCOH_BUS_MAX_EXCEED: - printk(BIOS_DEBUG, "maximum auto bus limit exceeded, Socket %lx Link %lx Bus %lx\n", - event->DataParam1, - event->DataParam2, - event->DataParam3); + printk(BIOS_DEBUG, "maximum auto bus limit exceeded, Socket %x Link %x Bus %x\n", + (unsigned int)event->DataParam1, + (unsigned int)event->DataParam2, + (unsigned int)event->DataParam3); break; case HT_EVENT_NCOH_CFG_MAP_EXCEED: - printk(BIOS_DEBUG, "there is a limit of four non-coherent chains, Socket %lx Link %lx\n", - event->DataParam1, - event->DataParam2); + printk(BIOS_DEBUG, "there is a limit of four non-coherent chains, Socket %x Link %x\n", + (unsigned int)event->DataParam1, + (unsigned int)event->DataParam2); break; case HT_EVENT_NCOH_DEVICE_FAILED: printk(BIOS_DEBUG, "after assigning an IO Device an ID, it does not respond at the new ID" - "Socket %lx Link %lx Depth %lx DeviceID %lx\n", - event->DataParam1, - event->DataParam2, - event->DataParam3, - event->DataParam4); + "Socket %x Link %x Depth %x DeviceID %x\n", + (unsigned int)event->DataParam1, + (unsigned int)event->DataParam2, + (unsigned int)event->DataParam3, + (unsigned int)event->DataParam4); default: break; } @@ -1005,33 +1005,33 @@ static void agesa_critical(EVENT_PARAMS *event) { switch (event->EventInfo) { case MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR3: - printk(BIOS_DEBUG, "Socket: %lx, Heap allocation error for DMI table for DDR3\n", - event->DataParam1); + printk(BIOS_DEBUG, "Socket: %x, Heap allocation error for DMI table for DDR3\n", + (unsigned int)event->DataParam1); break; case MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR2: - printk(BIOS_DEBUG, "Socket: %lx, Heap allocation error for DMI table for DDR2\n", - event->DataParam1); + printk(BIOS_DEBUG, "Socket: %x, Heap allocation error for DMI table for DDR2\n", + (unsigned int)event->DataParam1); break; case MEM_ERROR_UNSUPPORTED_DIMM_CONFIG: - printk(BIOS_DEBUG, "Socket: %lx, Dimm population is not supported\n", - event->DataParam1); + printk(BIOS_DEBUG, "Socket: %x, Dimm population is not supported\n", + (unsigned int)event->DataParam1); break; case HT_EVENT_COH_PROCESSOR_TYPE_MIX: - printk(BIOS_DEBUG, "Socket %lx Link %lx TotalSockets %lx, HT_EVENT_COH_PROCESSOR_TYPE_MIX \n", - event->DataParam1, - event->DataParam2, - event->DataParam3); + printk(BIOS_DEBUG, "Socket %x Link %x TotalSockets %x, HT_EVENT_COH_PROCESSOR_TYPE_MIX \n", + (unsigned int)event->DataParam1, + (unsigned int)event->DataParam2, + (unsigned int)event->DataParam3); break; case HT_EVENT_COH_MPCAP_MISMATCH: - printk(BIOS_DEBUG, "Socket %lx Link %lx MpCap %lx TotalSockets %lx, HT_EVENT_COH_MPCAP_MISMATCH\n", - event->DataParam1, - event->DataParam2, - event->DataParam3, - event->DataParam4); + printk(BIOS_DEBUG, "Socket %x Link %x MpCap %x TotalSockets %x, HT_EVENT_COH_MPCAP_MISMATCH\n", + (unsigned int)event->DataParam1, + (unsigned int)event->DataParam2, + (unsigned int)event->DataParam3, + (unsigned int)event->DataParam4); default: break; } @@ -1045,10 +1045,10 @@ static void agesa_fatal(EVENT_PARAMS *event) switch (event->EventInfo >> 24) { case 0x04: - printk(BIOS_DEBUG, "Memory: Socket %lx Dct %lx Channel%lx ", - event->DataParam1, - event->DataParam2, - event->DataParam3); + printk(BIOS_DEBUG, "Memory: Socket %x Dct %x Channel%x ", + (unsigned int)event->DataParam1, + (unsigned int)event->DataParam2, + (unsigned int)event->DataParam3); break; case 0x08: @@ -1124,8 +1124,8 @@ static void agesa_fatal(EVENT_PARAMS *event) break; case CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT: - printk(BIOS_DEBUG, "Socket: %lx, All PStates exceeded the motherboard current limit on specified socket\n", - event->DataParam1); + printk(BIOS_DEBUG, "Socket: %x, All PStates exceeded the motherboard current limit on specified socket\n", + (unsigned int)event->DataParam1); break; default: @@ -1191,9 +1191,15 @@ UINT32 agesawrapper_amdreadeventlog(UINT8 HeapStatus) AmdEventParams.StdHeader.HeapStatus = HeapStatus; Status = AmdReadEventLog(&AmdEventParams); while (AmdEventParams.EventClass != 0) { - printk(BIOS_DEBUG,"\nEventLog: EventClass = %lx, EventInfo = %lx.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo); - printk(BIOS_DEBUG," Param1 = %lx, Param2 = %lx.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2); - printk(BIOS_DEBUG," Param3 = %lx, Param4 = %lx.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4); + printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n", + (unsigned int)AmdEventParams.EventClass, + (unsigned int)AmdEventParams.EventInfo); + printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n", + (unsigned int)AmdEventParams.DataParam1, + (unsigned int)AmdEventParams.DataParam2); + printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n", + (unsigned int)AmdEventParams.DataParam3, + (unsigned int)AmdEventParams.DataParam4); interpret_agesa_eventlog(&AmdEventParams); Status = AmdReadEventLog(&AmdEventParams); }

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New patch to review for coreboot: 2b2582e Tyan S8226: Fix incompatible pointer warning
by Martin Roth 19 Feb '13

19 Feb '13

Martin Roth (martin.roth(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2450 -gerrit commit 2b2582e7997b1708cc7c12f97bbf28b73b4adcc8 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Mon Feb 18 21:23:16 2013 -0700 Tyan S8226: Fix incompatible pointer warning Fix warning: mptable.c:52, GNU Compiler 4 (gcc), Priority: Normal passing argument 3 of 'mptable_write_buses' from incompatible pointer type [enabled by default] mptable_write_buses is expecting a pointer to an int, so I changed the U8 isa_bus to an int to match. A U8 doesn't make sense if the value could be greater than 255 - certainly unlikely, but possible since the value of isa_bus gets set to the maximum PCI bus number + 1. Change-Id: I7ea416f48285922d6cf341382109993fd3f6405c Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/mainboard/tyan/s8226/get_bus_conf.c | 6 +++--- src/mainboard/tyan/s8226/mptable.c | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/tyan/s8226/get_bus_conf.c b/src/mainboard/tyan/s8226/get_bus_conf.c index 5171c45..ef34a99 100644 --- a/src/mainboard/tyan/s8226/get_bus_conf.c +++ b/src/mainboard/tyan/s8226/get_bus_conf.c @@ -32,7 +32,7 @@ /* Global variables for MB layouts and these will be shared by irqtable mptable * and acpi_tables busnum is default. */ -u8 bus_isa; +int bus_isa; u8 bus_sp5100[2]; u8 bus_sr5650[14]; @@ -101,7 +101,7 @@ void get_bus_conf(void) if (dev) { bus_sp5100[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); - bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa = (int)pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_isa++; for (j = bus_sp5100[1]; j < bus_isa; j++) bus_type[j] = 1; @@ -113,7 +113,7 @@ void get_bus_conf(void) if (dev) { bus_sr5650[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); if(255 != bus_sr5650[i]) { - bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa = (int)pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_isa++; bus_type[bus_sr5650[i]] = 1; /* PCI bus. */ } diff --git a/src/mainboard/tyan/s8226/mptable.c b/src/mainboard/tyan/s8226/mptable.c index 61a7bd4..c5c1ab6 100644 --- a/src/mainboard/tyan/s8226/mptable.c +++ b/src/mainboard/tyan/s8226/mptable.c @@ -33,7 +33,7 @@ extern u8 bus_sp5100[2]; extern u32 bus_type[256]; extern u32 sbdn_sr5650; extern u32 sbdn_sp5100; -extern u8 bus_isa; +extern int bus_isa; static void *smp_write_config_table(void *v)

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Patch merged into coreboot/master: f57d0dc AMD S3: Change S3_VOLATILE_POS to S3_DATA_POS
by gerrit＠coreboot.org 19 Feb '13

19 Feb '13

the following patch was just integrated into master: commit f57d0dce95e258e6c065ceac32b9ce0935a141cb Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Sun Feb 17 17:01:34 2013 +0800 AMD S3: Change S3_VOLATILE_POS to S3_DATA_POS S3_DATA_POS defines address where the whole S3 data is stored. Change-Id: I4155a0821e74a3653caaead890e5fec5677637aa Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: http://review.coreboot.org/2438 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin(a)se-eng.com> Reviewed-by: Marc Jones <marcj303(a)gmail.com> Build-Tested: build bot (Jenkins) at Sun Feb 17 13:08:32 2013, giving +1 Reviewed-By: Marc Jones <marcj303(a)gmail.com> at Tue Feb 19 01:24:09 2013, giving +2 See http://review.coreboot.org/2438 for details. -gerrit

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SCaLE 11x coreboot BoF meetup
by Marc Jones 19 Feb '13

19 Feb '13

Hi All, I'll be at SCaLE 11x this weekend (Feb21-23) and will host a coreboot BoF Friday and/or Saturday based on interest. Please come by and say hi if you are in the area. http://www.socallinuxexpo.org/scale11x Marc -- http://se-eng.com

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Patch merged into coreboot/master: 832452a RTC: Use the correct index when setting the default month
by gerrit＠coreboot.org 19 Feb '13

19 Feb '13

the following patch was just integrated into master: commit 832452a7ea71af1cba160fdb34c1856c7c9216fd Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Mon Feb 18 08:34:49 2013 -0700 RTC: Use the correct index when setting the default month Change-Id: I947a8b7ccd6141f164d1e63f7b8f524efa6c00f2 Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> Reviewed-on: http://review.coreboot.org/2442 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Mon Feb 18 17:30:18 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Tue Feb 19 00:59:49 2013, giving +2 See http://review.coreboot.org/2442 for details. -gerrit

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Patch merged into coreboot/master: b313e90 armv7: init stack to 0xdeadbeef to detect stack overflows
by gerrit＠coreboot.org 19 Feb '13

19 Feb '13

the following patch was just integrated into master: commit b313e90162fcc305178d26408533b183ce045965 Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Feb 15 17:50:20 2013 -0800 armv7: init stack to 0xdeadbeef to detect stack overflows This adds a simple loop which initializes the stack to 0xdeadbeef which is used by checkstack(). Change-Id: I8aecf7bfb1067de68c4080c1fcb7eefa28fd04a7 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/2421 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Build-Tested: build bot (Jenkins) at Mon Feb 18 23:56:19 2013, giving +1 See http://review.coreboot.org/2421 for details. -gerrit

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Patch set updated for coreboot: 93b5c94 snow: add cpu_cluster and domain resources via devicetree.cb
by David Hendricks 19 Feb '13

19 Feb '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2420 -gerrit commit 93b5c94d881c14ca507277e0bd6658e020170174 Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Feb 15 16:23:23 2013 -0800 snow: add cpu_cluster and domain resources via devicetree.cb This patch will cause the resource allocator to actually set aside the memory resources using methods in the previous patch. The coreboot table output will include "RAM" entries (there were none before): coreboot memory table: 0. 0000000040400000-00000000bff001ff: RAM 1. 00000000bff00200-00000000bff00fff: CONFIGURATION TABLES 2. 00000000bff01000-00000000bfffffff: RAM Change-Id: I5cd76e93fc232fdae1754253efb4e9269b3a20c0 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/mainboard/google/snow/devicetree.cb | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/mainboard/google/snow/devicetree.cb b/src/mainboard/google/snow/devicetree.cb index f88835e..4c88ea8 100644 --- a/src/mainboard/google/snow/devicetree.cb +++ b/src/mainboard/google/snow/devicetree.cb @@ -19,8 +19,14 @@ # FIXME: this is just a stub for now chip cpu/samsung/exynos5250 + +device cpu_cluster 0 on +end + +device domain 0 on chip drivers/generic/generic # I2C0 controller device i2c 6 on end # ? device i2c 9 on end # ? end end +end

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New patch to review for coreboot: 55e091d SPI: Increase the default SPI page erase timeout
by Dave Frodin 19 Feb '13

19 Feb '13

Dave Frodin (dave.frodin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2449 -gerrit commit 55e091d745f1f6e4178e356e287ebd080178d54c Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Mon Feb 18 16:30:34 2013 -0700 SPI: Increase the default SPI page erase timeout The M25P32 device can take up to 600mS to erase. Change-Id: I01e5bbb1f5bcf6ca68f6afe97d9b9052349d3242 Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> --- src/drivers/spi/spi_flash_internal.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/drivers/spi/spi_flash_internal.h b/src/drivers/spi/spi_flash_internal.h index 37ffee6..a738eaa 100644 --- a/src/drivers/spi/spi_flash_internal.h +++ b/src/drivers/spi/spi_flash_internal.h @@ -10,7 +10,7 @@ */ #define CONFIG_SYS_HZ 100 #define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ) -#define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ) +#define SPI_FLASH_PAGE_ERASE_TIMEOUT (20 * CONFIG_SYS_HZ) #define SPI_FLASH_SECTOR_ERASE_TIMEOUT (10 * CONFIG_SYS_HZ) /* Common commands */

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Re: [coreboot] AMD S3: Experiences with ACPI 2.0 method _BFS (Back From Sleep)
by Paul Menzel 19 Feb '13

19 Feb '13

Am Montag, den 18.02.2013, 12:21 -0700 schrieb Marc Jones: > On Mon, Feb 18, 2013 at 9:24 AM, Paul Menzel wrote: > > Am Montag, den 18.02.2013, 17:09 +0100 schrieb Paul Menzel: > > > >> searching for ACPI in the output of `dmesg` I noticed the following > >> message. > >> > >> $ uname -v > >> #1 SMP Debian 3.2.35-2 > >> $ dmesg | grep -i acpi > >> [ 0.154063] ACPI: BIOS offers _BFS > >> [ 0.154067] ACPI: If "acpi.bfs=1" improves resume, please notify linux-acpi(a)vger.kernel.org > >> > >> Doing > >> > >> $ git grep _GTA for correctness, that was supposed to be `git grep _BFS`. > >> reveals that it is only implemented in the DSDT of AMD based boards. > > The kernel sees the ACPI method, but doesn't do anything with it. If > you would like the kernel to use the method, pass acpi.bfs=1. > > > Looking at the actual “implementation” it looks like it is not > > implemented at all (see for AMD Thatcher’s DSDT) [1]. ;-) > ... > >> Was this ever tested by adding `acpi.bfs=1` to the Linux kernel command > >> line and what was the outcome? A test on AMD Persimmon would be very > >> interesting. > > Why would this be interesting? As noted, the method is present, but > doesn't do anything. So why is it there in the first place? > Some debug information could be enabled if the OS called the function. I see. I read the Linux ACPI message »If "acpi.bfs=1" improves resume, …« that way, that resume will be improved (by being quicker). I guess it was supposed to mean, »If your system has less problems with "acpi.bfs=1" than without, please …«. Sorry for the confusion. > >> It looks like support for this has been removed in the meantime though > >> > >> commit 3f6f49c7854c9294119437a82c5b35be78f9cea6 > >> Author: Len Brown <len.brown(a)intel.com> > >> Date: Thu Jul 26 20:08:54 2012 -0400 > >> > >> ACPI: delete _GTS/_BFS support > >> > >> since Linux Git tag v3.6-rc2. > > The function is part of the spec up to 4.0 and Len recommends that it > be remove it in the future revisions. > > It seems safe to remove it, but it isn't causing harm and is part of > the spec as implemented by coreboot. True. Thanks, Paul

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coreboot February 2013