coreboot February 2013

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Patch set updated for coreboot: 5da7cf6 Persimmon FWTS update: Fix FWTS S3 test.
by Mike Loptien 18 Feb '13

18 Feb '13

Mike Loptien (mike.loptien(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2444 -gerrit commit 5da7cf6104743e1560982004181019fcd91a6bfc Author: Mike Loptien <mike.loptien(a)se-eng.com> Date: Mon Feb 18 09:11:57 2013 -0700 Persimmon FWTS update: Fix FWTS S3 test. Fixing the _WAK method to allow it to return status and wake the system from S3 sleep with the RTC. This allows the FWTS S3 test to pass. The change being made is to uncomment a block of code in the WAK method which was commented out over 2 years ago: if(DeRefOf(Index(WKST,0))) { Store(0, Index(WKST,1)) } else { Store(Arg0, Index(WKST,1)) } Change-Id: Ica01572c23efa6d1c0fc422b5b2abf1b0f6eba71 Signed-off-by: Mike Loptien <mike.loptien(a)se-eng.com> --- src/mainboard/amd/persimmon/dsdt.asl | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/mainboard/amd/persimmon/dsdt.asl b/src/mainboard/amd/persimmon/dsdt.asl index dd7b4b1..876905d 100644 --- a/src/mainboard/amd/persimmon/dsdt.asl +++ b/src/mainboard/amd/persimmon/dsdt.asl @@ -931,12 +931,12 @@ DefinitionBlock ( /* Arbitrarily clear PciExpWakeStatus */ Store(PWST, PWST) - /* if(DeRefOf(Index(WKST,0))) { - * Store(0, Index(WKST,1)) - * } else { - * Store(Arg0, Index(WKST,1)) - * } - */ + if(DeRefOf(Index(WKST,0))) { + Store(0, Index(WKST,1)) + } else { + Store(Arg0, Index(WKST,1)) + } + Return(WKST) } /* End Method(\_WAK) */

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New patch to review for coreboot: b6ae9a2 Inagua: fix simple copy & paste error in code to reset PCIe slots
by Jens Rottmann 18 Feb '13

18 Feb '13

Jens Rottmann (JRottmann(a)LiPPERTembedded.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2445 -gerrit commit b6ae9a213bf1aeb1e18dc07b8f3fca4bebdfff35 Author: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Date: Mon Feb 18 18:56:48 2013 +0100 Inagua: fix simple copy & paste error in code to reset PCIe slots Looking at AssertSlotReset, the comments and all other 'case's it's obvious this is a simple copy&paste error where someone just forgot to change one occurrance of the GPIO nr. Also the Inagua schematics show that GPIO02 is what they really meant. Change-Id: I6b9a3d473245fa27604b2f148a730290277a88ed Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> --- src/mainboard/amd/inagua/BiosCallOuts.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/amd/inagua/BiosCallOuts.c b/src/mainboard/amd/inagua/BiosCallOuts.c index 3c38239..88bb1be 100644 --- a/src/mainboard/amd/inagua/BiosCallOuts.c +++ b/src/mainboard/amd/inagua/BiosCallOuts.c @@ -594,7 +594,7 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) Status = AGESA_SUCCESS; break; case DeassertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); Data8 |= BIT6 ; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 Status = AGESA_SUCCESS;

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Patch set updated for coreboot: 376fb02 Persimmon FWTS update: Fix FWTS S3 test.
by Mike Loptien 18 Feb '13

18 Feb '13

Mike Loptien (mike.loptien(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2444 -gerrit commit 376fb028342172ed072c5e253629dd55f26924c9 Author: Mike Loptien <mike.loptien(a)se-eng.com> Date: Mon Feb 18 09:11:57 2013 -0700 Persimmon FWTS update: Fix FWTS S3 test. Fixing the _WAK method to allow it to return status and wake the system from S3 sleep with the RTC. This allows the FWTS S3 test to pass. Change-Id: Ica01572c23efa6d1c0fc422b5b2abf1b0f6eba71 Signed-off-by: Mike Loptien <mike.loptien(a)se-eng.com> --- src/mainboard/amd/persimmon/dsdt.asl | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/mainboard/amd/persimmon/dsdt.asl b/src/mainboard/amd/persimmon/dsdt.asl index dd7b4b1..876905d 100644 --- a/src/mainboard/amd/persimmon/dsdt.asl +++ b/src/mainboard/amd/persimmon/dsdt.asl @@ -931,12 +931,12 @@ DefinitionBlock ( /* Arbitrarily clear PciExpWakeStatus */ Store(PWST, PWST) - /* if(DeRefOf(Index(WKST,0))) { - * Store(0, Index(WKST,1)) - * } else { - * Store(Arg0, Index(WKST,1)) - * } - */ + if(DeRefOf(Index(WKST,0))) { + Store(0, Index(WKST,1)) + } else { + Store(Arg0, Index(WKST,1)) + } + Return(WKST) } /* End Method(\_WAK) */

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New patch to review for coreboot: 454599b Persimmon FWTS update: Fix FWTS S3 test.
by Mike Loptien 18 Feb '13

18 Feb '13

Mike Loptien (mike.loptien(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2444 -gerrit commit 454599b51dd1ca5fb48babb4cae36002542a58aa Author: Mike Loptien <mike.loptien(a)se-eng.com> Date: Mon Feb 18 09:11:57 2013 -0700 Persimmon FWTS update: Fix FWTS S3 test. Fixing the _WAK method to allow it to return status and wake the system from S3 sleep with the RTC. This allows the FWTS S3 test to pass. Change-Id: Ica01572c23efa6d1c0fc422b5b2abf1b0f6eba71 Signed-off-by: Mike Loptien <mike.loptien(a)se-eng.com> --- src/mainboard/amd/persimmon/dsdt.asl | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/mainboard/amd/persimmon/dsdt.asl b/src/mainboard/amd/persimmon/dsdt.asl index dd7b4b1..0550905 100644 --- a/src/mainboard/amd/persimmon/dsdt.asl +++ b/src/mainboard/amd/persimmon/dsdt.asl @@ -931,12 +931,12 @@ DefinitionBlock ( /* Arbitrarily clear PciExpWakeStatus */ Store(PWST, PWST) - /* if(DeRefOf(Index(WKST,0))) { - * Store(0, Index(WKST,1)) - * } else { - * Store(Arg0, Index(WKST,1)) - * } - */ + if(DeRefOf(Index(WKST,0))) { + Store(0, Index(WKST,1)) + } else { + Store(Arg0, Index(WKST,1)) + } + Return(WKST) } /* End Method(\_WAK) */

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Patch merged into coreboot/master: 686dc0d Kconfig: string option doesn't work properly inside choice section
by gerrit＠coreboot.org 18 Feb '13

18 Feb '13

the following patch was just integrated into master: commit 686dc0d66b2c83898d8a9ad845cf908c4b8294d2 Author: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Date: Mon Feb 18 17:26:01 2013 +0100 Kconfig: string option doesn't work properly inside choice section At least not in menuconfig. Move it after the endchoice. Change-Id: I87d2f70e7c1fbe539cd78cb602a39335b2886d8d Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Reviewed-on: http://review.coreboot.org/2443 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter(a)stuge.se> Build-Tested: build bot (Jenkins) at Mon Feb 18 17:37:53 2013, giving +1 Reviewed-By: Peter Stuge <peter(a)stuge.se> at Mon Feb 18 17:39:37 2013, giving +2 See http://review.coreboot.org/2443 for details. -gerrit

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New patch to review for coreboot: 5f607b1 Kconfig: string option doesn't work properly inside choice section
by Jens Rottmann 18 Feb '13

18 Feb '13

Jens Rottmann (JRottmann(a)LiPPERTembedded.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2443 -gerrit commit 5f607b11ba3846a747a39284d82a99d2a3089d39 Author: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Date: Mon Feb 18 17:26:01 2013 +0100 Kconfig: string option doesn't work properly inside choice section At least not in menuconfig. Move it after the endchoice. Change-Id: I87d2f70e7c1fbe539cd78cb602a39335b2886d8d Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> --- src/cpu/Kconfig | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index caf4ebc..bb27da0 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -106,13 +106,6 @@ config CPU_MICROCODE_CBFS_EXTERNAL If unsure, select "Generate from tree" -config CPU_MICROCODE_FILE - string "Path and filename of CPU microcode" - depends on CPU_MICROCODE_CBFS_EXTERNAL - default "cpu_microcode.bin" - help - The path and filename of the file containing the CPU microcode. - config CPU_MICROCODE_CBFS_NONE bool "Do not include microcode updates" help @@ -156,3 +149,10 @@ config CPU_MICROCODE_CBFS_NONE selecting this option. endchoice + +config CPU_MICROCODE_FILE + string "Path and filename of CPU microcode" + depends on CPU_MICROCODE_CBFS_EXTERNAL + default "cpu_microcode.bin" + help + The path and filename of the file containing the CPU microcode.

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New patch to review for coreboot: 01d565f RTC: Use the correct index when setting the default month
by Dave Frodin 18 Feb '13

18 Feb '13

Dave Frodin (dave.frodin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2442 -gerrit commit 01d565f4de4022509a623413bf19155204f2e478 Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Mon Feb 18 08:34:49 2013 -0700 RTC: Use the correct index when setting the default month Change-Id: I947a8b7ccd6141f164d1e63f7b8f524efa6c00f2 Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> --- src/drivers/pc80/mc146818rtc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/drivers/pc80/mc146818rtc.c b/src/drivers/pc80/mc146818rtc.c index 5ffa9d7..d91f207 100644 --- a/src/drivers/pc80/mc146818rtc.c +++ b/src/drivers/pc80/mc146818rtc.c @@ -21,7 +21,7 @@ static void rtc_update_cmos_date(u8 has_century) cmos_write(1, RTC_CLK_HOUR); cmos_write(COREBOOT_BUILD_WEEKDAY_BCD + 1, RTC_CLK_DAYOFWEEK); cmos_write(COREBOOT_BUILD_DAY_BCD, RTC_CLK_DAYOFMONTH); - cmos_write(COREBOOT_BUILD_MONTH_BCD, RTC_CLK_MINUTE); + cmos_write(COREBOOT_BUILD_MONTH_BCD, RTC_CLK_MONTH); cmos_write(COREBOOT_BUILD_YEAR_BCD, RTC_CLK_YEAR); if (has_century) cmos_write(0x20, RTC_CLK_ALTCENTURY); }

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Trac reminder: list of new ticket(s)
by coreboot tracker 18 Feb '13

18 Feb '13

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Patch set updated for coreboot: a9442ef AMD S3: Introduce Kconfig variable 'S3_DATA_SIZE'
by Zheng Bao 18 Feb '13

18 Feb '13

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2383 -gerrit commit a9442ef4cbd79665941b66fbd741b5fe788d1acf Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Mon Feb 18 16:56:09 2013 +0800 AMD S3: Introduce Kconfig variable 'S3_DATA_SIZE' Currently the size of the volatile storage for S3 reserved in the image is hardcoded to 32768 bytes. Make that configurable by introducing the Kconfig 'S3_DATA_SIZE'. As the storage space is needed for storing non-volatile, volatile and MTRR data, add a check if the size is big enough. Change-Id: I9152797cf0045c8da48109a9d760e417717686db Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- src/cpu/amd/agesa/s3_resume.h | 4 ++++ src/southbridge/amd/Makefile.inc | 2 +- src/southbridge/amd/agesa/hudson/Kconfig | 8 ++++++++ src/southbridge/amd/cimx/sb700/Kconfig | 8 ++++++++ src/southbridge/amd/cimx/sb800/Kconfig | 8 ++++++++ src/southbridge/amd/cimx/sb900/Kconfig | 8 ++++++++ 6 files changed, 37 insertions(+), 1 deletion(-) diff --git a/src/cpu/amd/agesa/s3_resume.h b/src/cpu/amd/agesa/s3_resume.h index 367cc3f..af5b509 100644 --- a/src/cpu/amd/agesa/s3_resume.h +++ b/src/cpu/amd/agesa/s3_resume.h @@ -28,6 +28,10 @@ #define S3_DATA_MTRR_POS (CONFIG_S3_DATA_POS + S3_DATA_VOLATILE_SIZE) #define S3_DATA_NONVOLATILE_POS (CONFIG_S3_DATA_POS + S3_DATA_VOLATILE_SIZE + S3_DATA_MTRR_SIZE) +#if (S3_DATA_VOLATILE_SIZE + S3_DATA_MTRR_SIZE + S3_DATA_NONVOLATILE_SIZE) > CONFIG_S3_DATA_SIZE +#error "Please increase the value of S3_DATA_SIZE" +#endif + typedef enum { S3DataTypeNonVolatile=0, ///< NonVolatile Data Type S3DataTypeVolatile ///< Volatile Data Type diff --git a/src/southbridge/amd/Makefile.inc b/src/southbridge/amd/Makefile.inc index 5f54314..cce4702 100644 --- a/src/southbridge/amd/Makefile.inc +++ b/src/southbridge/amd/Makefile.inc @@ -22,7 +22,7 @@ ifeq ($(CONFIG_CPU_AMD_AGESA), y) $(obj)/coreboot_s3nv.rom: $(obj)/config.h echo " S3 NVRAM $(CONFIG_S3_DATA_POS) (S3 storage area)" # force C locale, so cygwin awk doesn't try to interpret the 0xff below as UTF-8 (or worse) - LC_ALL=C awk 'BEGIN {for (i=0; i<32768; i++) {printf "%c", 255}}' > $@.tmp + printf %d $(CONFIG_S3_DATA_SIZE) | LC_ALL=C awk '{for (i=0; i<$$1; i++) {printf "%c", 255}}' > $@.tmp mv $@.tmp $@ cbfs-files-y += s3nv diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index a469970..22caa31 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -212,6 +212,14 @@ config S3_DATA_POS For a system with S3 feature, the BIOS needs to save some data to non-volatile storage at cold boot stage. +config S3_DATA_SIZE + int "S3 volatile storage size" + default 32768 + depends on HAVE_ACPI_RESUME + help + For a system with S3 feature, the BIOS needs to save some data to + non-volatile storage at cold boot stage. + config HUDSON_LEGACY_FREE bool "System is legacy free" help diff --git a/src/southbridge/amd/cimx/sb700/Kconfig b/src/southbridge/amd/cimx/sb700/Kconfig index 706309d..37e9614 100644 --- a/src/southbridge/amd/cimx/sb700/Kconfig +++ b/src/southbridge/amd/cimx/sb700/Kconfig @@ -68,5 +68,13 @@ config S3_DATA_POS For a system with S3 feature, the BIOS needs to save some data to non-volatile storage at cold boot stage. +config S3_DATA_SIZE + int "S3 volatile storage size" + default 32768 + depends on HAVE_ACPI_RESUME + help + For a system with S3 feature, the BIOS needs to save some data to + non-volatile storage at cold boot stage. + endif #SOUTHBRIDGE_AMD_CIMX_SB700 diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index f56e017..2af0b32 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -130,6 +130,14 @@ config S3_DATA_POS For a system with S3 feature, the BIOS needs to save some data to non-volatile storage at cold boot stage. +config S3_DATA_SIZE + int "S3 volatile storage size" + default 32768 + depends on HAVE_ACPI_RESUME + help + For a system with S3 feature, the BIOS needs to save some data to + non-volatile storage at cold boot stage. + config SB800_IMC_FWM bool "Add IMC firmware" default n diff --git a/src/southbridge/amd/cimx/sb900/Kconfig b/src/southbridge/amd/cimx/sb900/Kconfig index 3cadba1..c886504 100755 --- a/src/southbridge/amd/cimx/sb900/Kconfig +++ b/src/southbridge/amd/cimx/sb900/Kconfig @@ -61,5 +61,13 @@ config S3_DATA_POS For a system with S3 feature, the BIOS needs to save some data to non-volatile storage at cold boot stage. +config S3_DATA_SIZE + int "S3 volatile storage size" + default 32768 + depends on HAVE_ACPI_RESUME + help + For a system with S3 feature, the BIOS needs to save some data to + non-volatile storage at cold boot stage. + endif #SOUTHBRIDGE_AMD_CIMX_SB900

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Patch merged into coreboot/master: 7b654a9 cbfstool: Fix compile warnings caused by incorrect data types.
by gerrit＠coreboot.org 18 Feb '13

18 Feb '13

the following patch was just integrated into master: commit 7b654a9702640c2d9fb8c37e4ae7f6b27ca949a0 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Mon Feb 18 18:35:00 2013 +0800 cbfstool: Fix compile warnings caused by incorrect data types. The "offset" in cbfs-mkpayload should be printed as type %lu instead of %d as `gcc` rightfully warns about. gcc -g -Wall -D_7ZIP_ST -c -o /srv/filme/src/coreboot/util/cbfstool/cbfs-mkpayload.o cbfs-mkpayload.c cbfs-mkpayload.c: In function ‘parse_fv_to_payload’: cbfs-mkpayload.c:284:3: warning: format ‘%d’ expects argument of type ‘int’, but argument 3 has type ‘long unsigned int’ [-Wformat] cbfs-mkpayload.c:296:3: warning: format ‘%d’ expects argument of type ‘int’, but argument 3 has type ‘long unsigned int’ [-Wformat] This warning was introduced in the following commit. commit 4610247ef1744ccabbcc6bfc441a3583aa49f7b5 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Feb 9 13:26:19 2013 +0100 cbfstool: Handle alignment in UEFI payloads Reviewed-on: http://review.coreboot.org/2334 Change-Id: I50c26a314723d45fcc6ff9ae2f08266cb7969a12 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Reviewed-on: http://review.coreboot.org/2440 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Mon Feb 18 12:02:35 2013, giving +1 Reviewed-By: Paul Menzel <paulepanter(a)users.sourceforge.net> at Mon Feb 18 11:55:25 2013, giving +2 See http://review.coreboot.org/2440 for details. -gerrit

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coreboot February 2013