coreboot February 2013

coreboot@coreboot.org

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New patch to review for coreboot: 422b0a1 exynos5250: add uartmem_getbaseaddr() in uart driver
by David Hendricks 16 Feb '13

16 Feb '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2423 -gerrit commit 422b0a19a148fff1ccb7ca704f146ae18036f4a0 Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Feb 15 19:32:01 2013 -0800 exynos5250: add uartmem_getbaseaddr() in uart driver Change-Id: I76545ad3fca3cc0997050253be77ea83b5d74cb2 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5250/uart.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/cpu/samsung/exynos5250/uart.c b/src/cpu/samsung/exynos5250/uart.c index 3e80017..c17a417 100644 --- a/src/cpu/samsung/exynos5250/uart.c +++ b/src/cpu/samsung/exynos5250/uart.c @@ -201,6 +201,11 @@ static const struct console_driver exynos5_uart_console __console = { .rx_byte = exynos5_uart_rx_byte, // .tst_byte = exynos5_uart_tst_byte, }; + +uint32_t uartmem_getbaseaddr(void) +{ + return base_port; +} #else void uart_init(void) {

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New patch to review for coreboot: 5365c9e move uartmem_getbaseaddr() to generic uart header
by David Hendricks 16 Feb '13

16 Feb '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2422 -gerrit commit 5365c9ee001dfbb80d912bbfbef884e9dfa5879b Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Feb 15 19:29:12 2013 -0800 move uartmem_getbaseaddr() to generic uart header This moves uartmem_getbaseaddr() from an 8250-specific header to the generic uart header. This is to accomodate non-8250 memory-mapped UARTs. Change-Id: Id25e7dab12b33bdd928f2aa4611d720aa79f3dee Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/include/uart.h | 4 ++++ src/include/uart8250.h | 1 - 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/src/include/uart.h b/src/include/uart.h index ca5191e..6b8d8e8 100644 --- a/src/include/uart.h +++ b/src/include/uart.h @@ -37,4 +37,8 @@ void uart_tx_flush(void); void uart_init(void); #endif +#if CONFIG_HAVE_UART_MEMORY_MAPPED +uint32_t uartmem_getbaseaddr(void); +#endif + #endif /* UART_H */ diff --git a/src/include/uart8250.h b/src/include/uart8250.h index 9af43f2..d1164c5 100644 --- a/src/include/uart8250.h +++ b/src/include/uart8250.h @@ -136,7 +136,6 @@ void uart8250_mem_tx_byte(unsigned base_port, unsigned char data); void uart8250_mem_tx_flush(unsigned base_port); void uart8250_mem_init(unsigned base_port, unsigned divisor); u32 uart_mem_init(void); -u32 uartmem_getbaseaddr(void); #if defined(__PRE_RAM__) && CONFIG_DRIVERS_OXFORD_OXPCIE /* and special init for OXPCIe based cards */

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Patch set updated for coreboot: 18d945f armv7: add lb_serial entry to coreboot tables
by David Hendricks 16 Feb '13

16 Feb '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2365 -gerrit commit 18d945f698689a9a4e60ca3c52a531459f9fb790 Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Feb 11 19:23:18 2013 -0800 armv7: add lb_serial entry to coreboot tables This adds a console entry to the coreboot tables. To accomodate Exynos' "special" uart type, a new LB_TAG_CONSOLE_UART_SPECIAL type was added. Change-Id: I65009d862e9731b609d09ea215cd0dd774109c11 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/boot/coreboot_table.c | 10 ++++++---- src/include/boot/coreboot_tables.h | 1 + 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/src/arch/armv7/boot/coreboot_table.c b/src/arch/armv7/boot/coreboot_table.c index 64f6a66..bc712b9 100644 --- a/src/arch/armv7/boot/coreboot_table.c +++ b/src/arch/armv7/boot/coreboot_table.c @@ -110,7 +110,7 @@ static struct lb_memory *lb_memory(struct lb_header *header) static struct lb_serial *lb_serial(struct lb_header *header) { -#if CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_HAVE_UART_IO_MAPPED struct lb_record *rec; struct lb_serial *serial; rec = lb_new_record(header); @@ -121,7 +121,7 @@ static struct lb_serial *lb_serial(struct lb_header *header) serial->baseaddr = CONFIG_TTYS0_BASE; serial->baud = CONFIG_TTYS0_BAUD; return serial; -#elif CONFIG_CONSOLE_SERIAL8250MEM +#elif CONFIG_HAVE_UART_MEMORY_MAPPED if (uartmem_getbaseaddr()) { struct lb_record *rec; struct lb_serial *serial; @@ -141,8 +141,7 @@ static struct lb_serial *lb_serial(struct lb_header *header) #endif } -#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM || \ - CONFIG_CONSOLE_LOGBUF || CONFIG_USBDEBUG +#if CONFIG_CONSOLE_SERIAL || CONFIG_CONSOLE_LOGBUF || CONFIG_USBDEBUG static void add_console(struct lb_header *header, u16 consoletype) { struct lb_console *console; @@ -162,6 +161,9 @@ static void lb_console(struct lb_header *header) #if CONFIG_CONSOLE_SERIAL8250MEM add_console(header, LB_TAG_CONSOLE_SERIAL8250MEM); #endif +#if CONFIG_HAVE_UART_SPECIAL + add_console(header, LB_TAG_CONSOLE_UART_SPECIAL); +#endif #if CONFIG_CONSOLE_LOGBUF add_console(header, LB_TAG_CONSOLE_LOGBUF); #endif diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index 9cf90d3..04427d2 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -167,6 +167,7 @@ struct lb_console { #define LB_TAG_CONSOLE_SROM 4 // OBSOLETE #define LB_TAG_CONSOLE_EHCI 5 #define LB_TAG_CONSOLE_SERIAL8250MEM 6 +#define LB_TAG_CONSOLE_UART_SPECIAL 7 #define LB_TAG_FORWARD 0x0011 struct lb_forward {

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Patch merged into coreboot/master: 7b69454 libpayload: only compile drivers/serial.c on machines that use it.
by gerrit＠coreboot.org 16 Feb '13

16 Feb '13

the following patch was just integrated into master: commit 7b6945405a7c703bb371cab973238e0c15b07cdf Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Fri Feb 15 08:13:29 2013 -0800 libpayload: only compile drivers/serial.c on machines that use it. Create a new serial console variable, X86_SERIAL_CONSOLE which is only enabled when SERIAL_CONSOLE and ARCH_X86 are defined. Builds for x86 and ARM. Change-Id: I607253c418de015975a839e3c33577842885ec0c Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-on: http://review.coreboot.org/2412 Tested-by: build bot (Jenkins) Reviewed-by: Gabe Black <gabeblack(a)chromium.org> Build-Tested: build bot (Jenkins) at Fri Feb 15 17:22:38 2013, giving +1 Reviewed-By: Gabe Black <gabeblack(a)chromium.org> at Sat Feb 16 04:48:50 2013, giving +2 See http://review.coreboot.org/2412 for details. -gerrit

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Patch set updated for coreboot: 4337ed3 armv7: init stack to 0xdeadbeef
by David Hendricks 16 Feb '13

16 Feb '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2421 -gerrit commit 4337ed3bbe4d14311ba897c61830ce5f385a5f87 Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Feb 15 17:50:20 2013 -0800 armv7: init stack to 0xdeadbeef This adds a simple loop which initializes the stack to 0xdeadbeef which is used by checkstack(). Change-Id: I8aecf7bfb1067de68c4080c1fcb7eefa28fd04a7 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/bootblock.inc | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/src/arch/armv7/bootblock.inc b/src/arch/armv7/bootblock.inc index c8cfe5e..2b7b41b 100644 --- a/src/arch/armv7/bootblock.inc +++ b/src/arch/armv7/bootblock.inc @@ -71,6 +71,18 @@ reset: cmp r1, #0 bne wait_for_interrupt @ If this is not core0, wait + /* init the stack */ + ldr r0, .Stack + ldr r1, .Stack_size + sub r0, r0, r1 + ldr r1, .Stack + ldr r2, =0xdeadbeef +init_stack_loop: + str r2, [r0] + add r0, #4 + cmp r0, r1 + bne init_stack_loop + /* Set stackpointer in internal RAM to call board_init_f */ call_bootblock: ldr sp, .Stack /* Set up stack pointer */ @@ -95,3 +107,6 @@ wait_for_interrupt: .align 2 .Stack: .word CONFIG_STACK_TOP +.align 2 +.Stack_size: + .word CONFIG_STACK_SIZE

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New patch to review for coreboot: 4868c88 armv7: init stack to 0xdeadbeef
by David Hendricks 16 Feb '13

16 Feb '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2421 -gerrit commit 4868c8839cc1be368bc774f91ae5803d5a219304 Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Feb 15 17:50:20 2013 -0800 armv7: init stack to 0xdeadbeef This adds a simple loop which initializes the stack to 0xdeadbeef which is used by checkstack(). Change-Id: I8aecf7bfb1067de68c4080c1fcb7eefa28fd04a7 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/bootblock.inc | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/src/arch/armv7/bootblock.inc b/src/arch/armv7/bootblock.inc index c8cfe5e..e9de16a 100644 --- a/src/arch/armv7/bootblock.inc +++ b/src/arch/armv7/bootblock.inc @@ -71,6 +71,18 @@ reset: cmp r1, #0 bne wait_for_interrupt @ If this is not core0, wait + /* init the stack */ + ldr r0, .Stack + ldr r1, .Stack_size + sub r0, r0, r1 + ldr r1, .Stack + ldr r2, =0xdeadbeef +init_stack_loop: + cmp r0, r1 + str r2, [r0] + add r0, #4 + bne init_stack_loop + /* Set stackpointer in internal RAM to call board_init_f */ call_bootblock: ldr sp, .Stack /* Set up stack pointer */ @@ -95,3 +107,6 @@ wait_for_interrupt: .align 2 .Stack: .word CONFIG_STACK_TOP +.align 2 +.Stack_size: + .word CONFIG_STACK_SIZE

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New patch to review for coreboot: 01b2e35 snow: add cpu_cluster and domain resources via devicetree.cb
by David Hendricks 16 Feb '13

16 Feb '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2420 -gerrit commit 01b2e3586aa00f328d29e208132eb5bb09bfbb61 Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Feb 15 16:23:23 2013 -0800 snow: add cpu_cluster and domain resources via devicetree.cb Change-Id: I5cd76e93fc232fdae1754253efb4e9269b3a20c0 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/mainboard/google/snow/devicetree.cb | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/mainboard/google/snow/devicetree.cb b/src/mainboard/google/snow/devicetree.cb index f88835e..4c88ea8 100644 --- a/src/mainboard/google/snow/devicetree.cb +++ b/src/mainboard/google/snow/devicetree.cb @@ -19,8 +19,14 @@ # FIXME: this is just a stub for now chip cpu/samsung/exynos5250 + +device cpu_cluster 0 on +end + +device domain 0 on chip drivers/generic/generic # I2C0 controller device i2c 6 on end # ? device i2c 9 on end # ? end end +end

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New patch to review for coreboot: af05080 armv7/snow: add CPU and RAM resources via allocator
by David Hendricks 16 Feb '13

16 Feb '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2419 -gerrit commit af050805a5d20534cface2b7509dbbd570a358f7 Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Feb 15 16:18:28 2013 -0800 armv7/snow: add CPU and RAM resources via allocator This adds necessary device operations to add CPU and RAM resources. Change-Id: Ief8f66627ef37f4fa786bfc3f7899529d3e5b037 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/boot/coreboot_table.c | 4 --- src/cpu/samsung/exynos5250/Makefile.inc | 1 + src/cpu/samsung/exynos5250/cpu.c | 61 +++++++++++++++++++++++++++++++++ 3 files changed, 62 insertions(+), 4 deletions(-) diff --git a/src/arch/armv7/boot/coreboot_table.c b/src/arch/armv7/boot/coreboot_table.c index 64f6a66..044f3d5 100644 --- a/src/arch/armv7/boot/coreboot_table.c +++ b/src/arch/armv7/boot/coreboot_table.c @@ -545,13 +545,11 @@ struct lb_memory *get_lb_mem(void) return mem_ranges; } -#if 0 static void build_lb_mem_range(void *gp, struct device *dev, struct resource *res) { struct lb_memory *mem = gp; new_lb_memory_range(mem, LB_MEM_RAM, res->base, res->size); } -#endif static struct lb_memory *build_lb_mem(struct lb_header *head) { @@ -562,12 +560,10 @@ static struct lb_memory *build_lb_mem(struct lb_header *head) mem_ranges = mem; /* FIXME: implement this */ -#if 0 /* Build the raw table of memory */ search_global_resources( IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE, build_lb_mem_range, mem); -#endif /* FIXME: things die in cleanup_memory_ranges(), skip for now */ // lb_cleanup_memory_ranges(mem); return mem; diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index 10c071a..c9a9341 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -27,6 +27,7 @@ ramstage-y += pinmux.c ramstage-y += power.c ramstage-y += soc.c ramstage-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c +ramstage-y += cpu.c #ramstage-$(CONFIG_SATA_AHCI) += sata.c diff --git a/src/cpu/samsung/exynos5250/cpu.c b/src/cpu/samsung/exynos5250/cpu.c new file mode 100644 index 0000000..0a49e1e --- /dev/null +++ b/src/cpu/samsung/exynos5250/cpu.c @@ -0,0 +1,61 @@ +#include <console/console.h> +#include <device/device.h> + +#define RAM_BASE ((CONFIG_SYS_SDRAM_BASE >> 10) + (CONFIG_COREBOOT_ROMSIZE_KB)) +#define RAM_SIZE (((CONFIG_DRAM_SIZE_MB << 10UL) * CONFIG_NR_DRAM_BANKS) \ + - CONFIG_COREBOOT_ROMSIZE_KB) + +static void domain_read_resources(device_t dev) +{ + ram_resource(dev, 0, RAM_BASE, RAM_SIZE); +} + +static void domain_set_resources(device_t dev) +{ + assign_resources(dev->link_list); +} + +static unsigned int domain_scan_bus(device_t dev, unsigned int max) +{ + return max; +} + + +static struct device_operations domain_ops = { + .read_resources = domain_read_resources, + .set_resources = domain_set_resources, + .enable_resources = NULL, + .init = NULL, + .scan_bus = domain_scan_bus, +}; + +static void cpu_init(device_t dev) +{ +} + +static void cpu_noop(device_t dev) +{ +} + +static struct device_operations cpu_ops = { + .read_resources = cpu_noop, + .set_resources = cpu_noop, + .enable_resources = cpu_noop, + .init = cpu_init, + .scan_bus = 0, +}; + +static void enable_dev(device_t dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_DOMAIN) { + dev->ops = &domain_ops; + } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { + dev->ops = &cpu_ops; + } +} + +struct chip_operations cpu_samsung_exynos5250_ops = { + CHIP_NAME("CPU Samsung Exynos 5250") + .enable_dev = enable_dev, +};

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New patch to review for coreboot: b241395 build system: Retire REQUIRES_BLOB
by Patrick Georgi 16 Feb '13

16 Feb '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2418 -gerrit commit b2413951604484fcfaa7cb147113690411fa401f Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Feb 16 01:06:57 2013 +0100 build system: Retire REQUIRES_BLOB REQUIRES_BLOB assumes that all blob files come from the 3rdparty directory, builds failed when all files were configured to point to other sources. This change modifies the blob mechanism so that cbfs-files can be tagged as "required" with some specification what is missing. If the configured files can't be found (wrong path, missing file), the build system returns a list of descriptions, then aborts. Change-Id: Icc128e3afcee8acf49bff9409b93af7769db3517 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- Makefile | 3 +++ Makefile.inc | 12 +++++++----- src/Kconfig | 10 ---------- src/cpu/amd/geode_gx2/Makefile.inc | 2 ++ src/cpu/amd/geode_lx/Kconfig | 1 - src/cpu/amd/geode_lx/Makefile.inc | 2 ++ src/southbridge/amd/agesa/hudson/Kconfig | 3 --- src/southbridge/amd/agesa/hudson/Makefile.inc | 4 ++++ 8 files changed, 18 insertions(+), 19 deletions(-) diff --git a/Makefile b/Makefile index 92b4d0b..9aafe7c 100644 --- a/Makefile +++ b/Makefile @@ -232,6 +232,9 @@ evaluate_subdirs= \ # collect all object files eligible for building subdirs:=$(TOPLEVEL) $(eval $(call evaluate_subdirs)) +ifeq ($(FAILBUILD),1) +$(error cannot continue build) +endif # Eliminate duplicate mentions of source files in a class $(foreach class,$(classes),$(eval $(class)-srcs:=$(sort $($(class)-srcs)))) diff --git a/Makefile.inc b/Makefile.inc index 069bdfe..36e7e53 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -105,10 +105,6 @@ endif ifeq ($(CONFIG_USE_BLOBS),y) forgetthis:=$(shell git submodule update --init --checkout 3rdparty) -else -ifeq ($(CONFIG_REQUIRES_BLOB),y) -$(error Your current configuration requires binary-only components, but you did not choose to use them) -endif endif bootblock-c-ccopts:=-D__BOOT_BLOCK__ -D__PRE_RAM__ @@ -164,6 +160,11 @@ cbfs-files-handler= \ $(if $(wildcard $(1)$($(2)-file)), \ $(eval tmp-cbfs-file:= $(wildcard $(1)$($(2)-file))), \ $(eval tmp-cbfs-file:= $($(2)-file))) \ + $(if $(strip $($(2)-required)), \ + $(ifeq $(wildcard $(tmp-cbfs-file)),, \ + $(info This build configuration requires $($(2)-required)) \ + $(eval FAILBUILD:=1) \ + )) \ $(if $(tmp-cbfs-method), \ $(eval tmp-old-cbfs-file:=$(tmp-cbfs-file)) \ $(eval tmp-cbfs-file:=$(shell mkdir -p $(obj)/mainboard/$(MAINBOARDDIR); mktemp $(obj)/mainboard/$(MAINBOARDDIR)/cbfs-file.XXXXXX).out) \ @@ -172,7 +173,8 @@ cbfs-files-handler= \ $(eval $(2)-name:=) \ $(eval $(2)-type:=) \ $(eval $(2)-compression:=) \ - $(eval $(2)-position:=) + $(eval $(2)-position:=) \ + $(eval $(2)-required:=) ####################################################################### # a variety of flags for our build diff --git a/src/Kconfig b/src/Kconfig index 4e7957e..2dc251d 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -184,16 +184,6 @@ config USE_BLOBS might be required for some chipsets or boards. This flag ensures that a "Free" option remains available for users. -config REQUIRES_BLOB - bool - default n - help - This option can be configured by boards that require the blobs - repository for the default configuration. It will make the build - fail if USE_BLOBS is disabled. Users that still desire to do a - coreboot build for such a board can override this manually, but - this option serves as warning that it might fail. - config COVERAGE bool "Code coverage support" depends on COMPILER_GCC diff --git a/src/cpu/amd/geode_gx2/Makefile.inc b/src/cpu/amd/geode_gx2/Makefile.inc index b3f3de9..f42f1bd 100644 --- a/src/cpu/amd/geode_gx2/Makefile.inc +++ b/src/cpu/amd/geode_gx2/Makefile.inc @@ -11,3 +11,5 @@ cpu_incs += $(src)/cpu/amd/geode_gx2/cache_as_ram.inc cbfs-files-$(CONFIG_GEODE_VSA_FILE) += vsa vsa-file = $(call strip_quotes,$(CONFIG_VSA_FILENAME)):vsa vsa-type = stage +vsa-required = VSA binary + diff --git a/src/cpu/amd/geode_lx/Kconfig b/src/cpu/amd/geode_lx/Kconfig index 777dc94..7deb100 100644 --- a/src/cpu/amd/geode_lx/Kconfig +++ b/src/cpu/amd/geode_lx/Kconfig @@ -19,7 +19,6 @@ config GEODE_VSA bool default y select PCI_OPTION_ROM_RUN_REALMODE - select REQUIRES_BLOB config GEODE_VSA_FILE bool "Add a VSA image" diff --git a/src/cpu/amd/geode_lx/Makefile.inc b/src/cpu/amd/geode_lx/Makefile.inc index c9df888..29fe0aa 100644 --- a/src/cpu/amd/geode_lx/Makefile.inc +++ b/src/cpu/amd/geode_lx/Makefile.inc @@ -11,3 +11,5 @@ cpu_incs += $(src)/cpu/amd/geode_lx/cache_as_ram.inc cbfs-files-$(CONFIG_GEODE_VSA_FILE) += vsa vsa-file = $(call strip_quotes,$(CONFIG_VSA_FILENAME)):vsa vsa-type = stage +vsa-required = VSA binary + diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index 92e5960..6cbed53 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -46,21 +46,18 @@ if SOUTHBRIDGE_AMD_AGESA_HUDSON config HUDSON_XHCI_FWM bool "Add xhci firmware" default y - select REQUIRES_BLOB help Add Hudson 2/3/4 XHCI Firmware to support the onboard usb3.0 config HUDSON_IMC_FWM bool "Add imc firmware" default y - select REQUIRES_BLOB help Add Hudson 2/3/4 IMC Firmware to support the onboard fan control config HUDSON_GEC_FWM bool "Add gec firmware" default n - select REQUIRES_BLOB help Add Hudson 2/3/4 GEC Firmware diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index c9a1731..a5b1231 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -74,6 +74,7 @@ cbfs-files-y += hudson/xhci hudson/xhci-file := $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) hudson/xhci-position := $(HUDSON_XHCI_POSITION) hudson/xhci-type := raw +hudson/xhci-required := Hudson XHCI firmware endif ifeq ($(CONFIG_HUDSON_IMC_FWM), y) @@ -81,6 +82,7 @@ cbfs-files-y += hudson/imc hudson/imc-file := $(call strip_quotes, $(CONFIG_HUDSON_IMC_FWM_FILE)) hudson/imc-position := $(HUDSON_IMC_POSITION) hudson/imc-type := raw +hudson/imc-required := Hudson IMC Firmware endif ifeq ($(CONFIG_HUDSON_GEC_FWM), y) @@ -88,6 +90,7 @@ cbfs-files-y += hudson/gec hudson/gec-file := $(call strip_quotes, $(CONFIG_HUDSON_GEC_FWM_FILE)) hudson/gec-position := $(HUDSON_GEC_POSITION) hudson/gec-type := raw +hudson/gec-required := Hudson Gigabit Ethernet Controller Firmware (Contact your AMD representative) endif #ifeq ($(CONFIG_HUDSON_SATA_AHCI), y) @@ -96,5 +99,6 @@ stripped_ahci_rom_id = $(call strip_quotes,$(CONFIG_AHCI_ROM_ID)) cbfs-files-y += pci$(stripped_ahci_rom_id).rom pci$(stripped_ahci_rom_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_ROM_FILE)) pci$(stripped_ahci_rom_id).rom-type := optionrom +pci$(stripped_ahci_rom_id).rom-required := Hudson AHCI Option ROM (Contact your AMD representative) #endif endif

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Patch merged into coreboot/master: 8029215 exynos5250: clean out some stale IRAM-related config variables
by gerrit＠coreboot.org 16 Feb '13

16 Feb '13

the following patch was just integrated into master: commit 802921562f2f9b94686b1464e994c761416ad88e Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Feb 15 15:20:32 2013 -0800 exynos5250: clean out some stale IRAM-related config variables This cleans out some obsolete Kconfig variables pertaining to IRAM usage. Change-Id: Ie53f5f7204eadc3a3dddc739d2b4b6237242b198 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/2417 Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Sat Feb 16 00:42:53 2013, giving +1 See http://review.coreboot.org/2417 for details. -gerrit

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coreboot February 2013