coreboot February 2013

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Patch merged into coreboot/master: 882fdcf armv7/exynos5250: fix usage of _stack and _estack
by gerrit＠coreboot.org 16 Feb '13

16 Feb '13

the following patch was just integrated into master: commit 882fdcf2271d385f1110c0f3737ceeb5e30d2861 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Feb 14 16:41:54 2013 -0800 armv7/exynos5250: fix usage of _stack and _estack This patch fixes up the usage of stack pointer and regions. The current approach only works by coincidence, so this fixes a few things at once to get it into a working state and allow us to use checkstack() again: - Add a STACK_SIZE Kconfig variable. Earlier on it was evaluated to 0. - Assign _stack and _estack using CPU-specific Kconfig variables since it may reside elsewhere in memory (not necessarily DRAM). - Make the existing IRAM stack variables more useful in this context. Change-Id: I4ca5b5680c9ea7e26b1b2b6b3890e028188b51c2 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/2416 Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Sat Feb 16 00:33:24 2013, giving +1 See http://review.coreboot.org/2416 for details. -gerrit

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New patch to review for coreboot: 018167a exynos5250: clean out some stale IRAM-related config variables
by David Hendricks 16 Feb '13

16 Feb '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2417 -gerrit commit 018167a4d0ac084962294e18d4a5c431610d188c Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Feb 15 15:20:32 2013 -0800 exynos5250: clean out some stale IRAM-related config variables This cleans out some obsolete Kconfig variables pertaining to IRAM usage. Change-Id: Ie53f5f7204eadc3a3dddc739d2b4b6237242b198 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5-common/exynos5-common.h | 28 ------------------------- src/cpu/samsung/exynos5250/Kconfig | 9 -------- 2 files changed, 37 deletions(-) diff --git a/src/cpu/samsung/exynos5-common/exynos5-common.h b/src/cpu/samsung/exynos5-common/exynos5-common.h index 5bbc52b..b510d68 100644 --- a/src/cpu/samsung/exynos5-common/exynos5-common.h +++ b/src/cpu/samsung/exynos5-common/exynos5-common.h @@ -179,34 +179,6 @@ #define CONFIG_EFI_PARTITION #endif -#if 0 -/* - * FIXME(dhendrix): 0x02050000 was in the u-boot sources, but the docs say the - * iRAM range is 0x0202_0000 - 0x0207_7fff (352KB). - */ -#define CONFIG_IRAM_TOP 0x02050000 - -/* - * Put the initial stack pointer 1KB below this to allow room for the - * SPL marker. This value is arbitrary, but gd_t is placed starting here. - */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_IRAM_TOP - 0x800) -#endif - -/* The place where we put our SPL marker */ -#define CONFIG_SPL_MARKER (CONFIG_IRAM_TOP - 4) - -/* Place to stash bootstage data from first-stage U-Boot */ -#define CONFIG_BOOTSTAGE_STASH (CONFIG_IRAM_TOP - 0x400) -#define CONFIG_BOOTSTAGE_STASH_SIZE 0x3fc - -/* The top of the SPL stack, also used for early U-Boot init */ -//#define CONFIG_IRAM_STACK CONFIG_SYS_INIT_SP_ADDR - -//#define CONFIG_SPL_LDSCRIPT -//#define CONFIG_SPL_TEXT_BASE 0x02023400 -//#define CONFIG_SPL_MAX_SIZE (14 * 1024) - /* Enable devicetree support */ #define CONFIG_OF_LIBFDT diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig index 01268e4..1b8b23f 100644 --- a/src/cpu/samsung/exynos5250/Kconfig +++ b/src/cpu/samsung/exynos5250/Kconfig @@ -25,15 +25,6 @@ config BL1_SIZE_KB # 0x0203_0000: romstage, assume up to 128KB in size. # 0x0207_8000: stack pointer -# this may be used to calculate offsets -config IRAM_BOTTOM - hex - default 0x02020000 - -config IRAM_TOP - hex - default 0x02077fff - config BOOTBLOCK_BASE hex default 0x02023400

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New patch to review for coreboot: 0aeccb6 armv7/exynos5250: fix usage of _stack and _estack
by David Hendricks 16 Feb '13

16 Feb '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2416 -gerrit commit 0aeccb60fff83d4c99c7744419155d9e670cc4ce Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Feb 14 16:41:54 2013 -0800 armv7/exynos5250: fix usage of _stack and _estack This patch fixes up the usage of stack pointer and regions. The current approach only works by coincidence, so this fixes a few things at once to get it into a working state and allow us to use checkstack() again: - Add a STACK_SIZE Kconfig variable. Earlier on it was evaluated to 0. - Assign _stack and _estack using CPU-specific Kconfig variables since it may reside elsewhere in memory (not necessarily DRAM). - Make the existing IRAM stack variables more useful in this context. Change-Id: I4ca5b5680c9ea7e26b1b2b6b3890e028188b51c2 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/bootblock.inc | 2 +- src/arch/armv7/coreboot_ram.ld | 12 +++--------- src/cpu/samsung/exynos5250/Kconfig | 23 ++++++++++++++++++----- 3 files changed, 22 insertions(+), 15 deletions(-) diff --git a/src/arch/armv7/bootblock.inc b/src/arch/armv7/bootblock.inc index efe3d67..c8cfe5e 100644 --- a/src/arch/armv7/bootblock.inc +++ b/src/arch/armv7/bootblock.inc @@ -94,4 +94,4 @@ wait_for_interrupt: */ .align 2 .Stack: - .word CONFIG_IRAM_STACK + .word CONFIG_STACK_TOP diff --git a/src/arch/armv7/coreboot_ram.ld b/src/arch/armv7/coreboot_ram.ld index 0644e36..2edf8e3 100644 --- a/src/arch/armv7/coreboot_ram.ld +++ b/src/arch/armv7/coreboot_ram.ld @@ -99,15 +99,6 @@ SECTIONS * this line. */ - . = ALIGN(CONFIG_STACK_SIZE); - - _stack = .; - .stack . : { - /* Reserve a stack for each possible cpu */ - . += CONFIG_MAX_CPUS*CONFIG_STACK_SIZE; - } - _estack = .; - _heap = .; .heap . : { /* Reserve CONFIG_HEAP_SIZE bytes for the heap */ @@ -116,6 +107,9 @@ SECTIONS } _eheap = .; + _stack = CONFIG_STACK_BOTTOM; + _estack = CONFIG_STACK_TOP; + /* The ram segment. This includes all memory used by the memory * resident copy of coreboot, except the tables that are produced on * the fly, but including stack and heap. diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig index 2869d76..01268e4 100644 --- a/src/cpu/samsung/exynos5250/Kconfig +++ b/src/cpu/samsung/exynos5250/Kconfig @@ -23,7 +23,7 @@ config BL1_SIZE_KB # 0x0202_0000: vendor-provided BL1 # 0x0202_3400: bootblock, assume up to 32KB in size # 0x0203_0000: romstage, assume up to 128KB in size. -# 0x0207_7f00: stack pointer +# 0x0207_8000: stack pointer # this may be used to calculate offsets config IRAM_BOTTOM @@ -46,6 +46,23 @@ config ROMSTAGE_SIZE hex default 0x10000 +# Stack may reside in either IRAM or DRAM. We will define it to live +# at the top of IRAM for now. +# +# Stack grows downward, push operation stores register contents in +# consecutive memory locations ending just below SP +config STACK_TOP + hex + default 0x02078000 + +config STACK_BOTTOM + hex + default 0x02077000 + +config STACK_SIZE + hex + default 0x1000 + config CBFS_ROM_OFFSET # Calculated by BL1 + max bootblock size. hex "offset of CBFS data in ROM" @@ -73,10 +90,6 @@ config SPI_IMAGE_HACK hex default 0x02060000 -config IRAM_STACK - hex - default 0x02077f00 - # FIXME: other magic numbers that should probably go away config XIP_ROM_SIZE hex

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New patch to review for coreboot: e8b0756 AMD Hudson: Disable the binary blobs requirement
by Martin Roth 15 Feb '13

15 Feb '13

Martin Roth (martin.roth(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2415 -gerrit commit e8b07560c4b6506f3dd86f405d8f2007e06aae79 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Fri Feb 15 13:45:43 2013 -0700 AMD Hudson: Disable the binary blobs requirement Enabling the binary blobs repository is an artificial requirement and is keeping me from building my system when I have my config pointed to roms that are not in the binary blobs repo anyway. This change removes the binary blobs requirement for hudson and gives better feedback about the files when they are missing from the build. Change-Id: Id080905928848a239a992ce6604ea75d00081a8f Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/southbridge/amd/agesa/hudson/Kconfig | 3 -- src/southbridge/amd/agesa/hudson/Makefile.inc | 48 +++++++++++++++++++++++++-- 2 files changed, 46 insertions(+), 5 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index 92e5960..6cbed53 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -46,21 +46,18 @@ if SOUTHBRIDGE_AMD_AGESA_HUDSON config HUDSON_XHCI_FWM bool "Add xhci firmware" default y - select REQUIRES_BLOB help Add Hudson 2/3/4 XHCI Firmware to support the onboard usb3.0 config HUDSON_IMC_FWM bool "Add imc firmware" default y - select REQUIRES_BLOB help Add Hudson 2/3/4 IMC Firmware to support the onboard fan control config HUDSON_GEC_FWM bool "Add gec firmware" default n - select REQUIRES_BLOB help Add Hudson 2/3/4 GEC Firmware diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index c9a1731..085c64b 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -74,6 +74,17 @@ cbfs-files-y += hudson/xhci hudson/xhci-file := $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) hudson/xhci-position := $(HUDSON_XHCI_POSITION) hudson/xhci-type := raw + +# check to see if the XHCI firmware exists +$(call strip_quotes,$(CONFIG_HUDSON_XHCI_FWM_FILE)): + $(info ) + $(info ###########################################################################) + $(info # ERROR: The XHCI firmware file specified does not exist:) + $(info # $(CONFIG_HUDSON_XHCI_FWM_FILE) ) + $(info # Please enable binary blobs or configure a valid XHCI firmware path.) + $(info ###########################################################################) + $(info ) + __XHCI_FIRMWARE_ERROR___END_BUILD__ endif ifeq ($(CONFIG_HUDSON_IMC_FWM), y) @@ -81,6 +92,17 @@ cbfs-files-y += hudson/imc hudson/imc-file := $(call strip_quotes, $(CONFIG_HUDSON_IMC_FWM_FILE)) hudson/imc-position := $(HUDSON_IMC_POSITION) hudson/imc-type := raw + +# check to see if the IMC firmware exists +$(call strip_quotes,$(CONFIG_HUDSON_IMC_FWM_FILE)): + $(info ) + $(info ###########################################################################) + $(info # ERROR: The IMC firmware file specified does not exist:) + $(info # $(CONFIG_HUDSON_IMC_FWM_FILE) ) + $(info # Please enable binary blobs or config a valid IMC firmware path.) + $(info ###########################################################################) + $(info ) + __IMC_FIRMWARE_ERROR___END_BUILD__ endif ifeq ($(CONFIG_HUDSON_GEC_FWM), y) @@ -88,13 +110,35 @@ cbfs-files-y += hudson/gec hudson/gec-file := $(call strip_quotes, $(CONFIG_HUDSON_GEC_FWM_FILE)) hudson/gec-position := $(HUDSON_GEC_POSITION) hudson/gec-type := raw + +# check to see if the GEC firmware exists +$(call strip_quotes,$(CONFIG_HUDSON_GEC_FWM_FILE)): + $(info ) + $(info ###########################################################################) + $(info # ERROR: The GEC firmware file specified does not exist:) + $(info # $(CONFIG_HUDSON_GEC_FWM_FILE) ) + $(info # Please configure a valid GEC firmware path. If you don't have) + $(info # this file, it may be obtained from your AMD representative.) + $(info ###########################################################################) + $(info ) + __GEC_FIRMWARE_ERROR___END_BUILD__ endif -#ifeq ($(CONFIG_HUDSON_SATA_AHCI), y) ifdef CONFIG_HUDSON_AHCI_ROM stripped_ahci_rom_id = $(call strip_quotes,$(CONFIG_AHCI_ROM_ID)) cbfs-files-y += pci$(stripped_ahci_rom_id).rom pci$(stripped_ahci_rom_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_ROM_FILE)) pci$(stripped_ahci_rom_id).rom-type := optionrom -#endif + +# check to see if the AHCI rom exists +$(call strip_quotes,$(CONFIG_AHCI_ROM_FILE)): + $(info ) + $(info ###########################################################################) + $(info # ERROR: The AHCI rom specified does not exist:) + $(info # $(CONFIG_AHCI_ROM_FILE) ) + $(info # Please configure a valid AHCI rom path. If you don't have) + $(info # this file, it may be obtained from your AMD representative.) + $(info ###########################################################################) + $(info ) + __AHCI_ROM_ERROR___END_BUILD__ endif

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Patch set updated for coreboot: 97a6e96 libpayload: add support for the exynos5 UART
by Ronald G. Minnich 15 Feb '13

15 Feb '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2414 -gerrit commit 97a6e9653dcf23438fb3faca37158e662ee6e809 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Fri Feb 15 09:44:28 2013 -0800 libpayload: add support for the exynos5 UART This CL adds *limited* support for the exynos5 uart. It's a new BSD-licensed implementation. We support read, write, and test for input as in the existing serial.c. Because of the plethora of other hardware that it would bring in, we've decided for now to leave out configuration operations such as setting baud rate. Set it right in coreboot and leave it alone. Add two new variables, EXYNOS5_SERIAL_CONSOLE -- enable it EXYNOS5_SERIAL_BASE -- set the base in Config.in, add options for selecting the UART and setting its base address; a reasonable default is configured. Set that default into sysinfo if EXYNOS5_SERIAL_CONSOLE is set. Compile the UART in if EXYNOS5_SERIAL_CONSOLE is set. Add the slightly truncated code from coreboot; don't bother with an include file, only this one file needs to see the structs. This is one case where an include file would do more harm than good. Change-Id: Iff1f601a8ba5e69d63eb10763e748c92a03a3df8 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- payloads/libpayload/Config.in | 12 ++- payloads/libpayload/arch/armv7/sysinfo.c | 3 + payloads/libpayload/drivers/Makefile.inc | 1 + payloads/libpayload/drivers/exynos5250_uart.c | 117 ++++++++++++++++++++++++++ 4 files changed, 132 insertions(+), 1 deletion(-) diff --git a/payloads/libpayload/Config.in b/payloads/libpayload/Config.in index a14291d..ccc9449 100644 --- a/payloads/libpayload/Config.in +++ b/payloads/libpayload/Config.in @@ -70,7 +70,7 @@ choice config ARCH_ARMV7 bool "ARMv7" help - Support the x86 architecture + Support the ARMV7 architecture config ARCH_POWERPC bool "PowerPC" @@ -168,6 +168,16 @@ config SERIAL_CONSOLE bool "See output on the serial port console" default y +config EXYNOS5_SERIAL_CONSOLE + bool "Exynos 5xxx serial console" + depends on ARCH_ARMV7 + default n + +config EXYNOS5_SERIAL_BASE + hex "Base for the Exynos5 serial port" + depends on EXYNOS5_SERIAL_CONSOLE + default 0x12c30000 + config SERIAL_IOBASE hex "I/O base for the serial port (default 0x3f8)" depends on SERIAL_CONSOLE diff --git a/payloads/libpayload/arch/armv7/sysinfo.c b/payloads/libpayload/arch/armv7/sysinfo.c index 5aa5175..fc527d2 100644 --- a/payloads/libpayload/arch/armv7/sysinfo.c +++ b/payloads/libpayload/arch/armv7/sysinfo.c @@ -37,6 +37,9 @@ */ struct sysinfo_t lib_sysinfo = { .cpu_khz = 200, +#ifdef CONFIG_SERIAL_CONSOLE + .ser_base = CONFIG_EXYNOS5_SERIAL_BASE, +#endif }; int lib_get_sysinfo(void) diff --git a/payloads/libpayload/drivers/Makefile.inc b/payloads/libpayload/drivers/Makefile.inc index e3bb995..71c2519 100644 --- a/payloads/libpayload/drivers/Makefile.inc +++ b/payloads/libpayload/drivers/Makefile.inc @@ -34,6 +34,7 @@ libc-$(CONFIG_PCI) += pci.c libc-$(CONFIG_SPEAKER) += speaker.c libc-$(CONFIG_SERIAL_CONSOLE) += serial.c +libc-$(CONFIG_EXYNOS5_SERIAL_CONSOLE) += exynos5250_uart.c libc-$(CONFIG_PC_KEYBOARD) += keyboard.c diff --git a/payloads/libpayload/drivers/exynos5250_uart.c b/payloads/libpayload/drivers/exynos5250_uart.c new file mode 100644 index 0000000..ad48769 --- /dev/null +++ b/payloads/libpayload/drivers/exynos5250_uart.c @@ -0,0 +1,117 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2013 Google, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <libpayload-config.h> +#include <libpayload.h> + +/* + * this is a seriously cut-down UART implementation, the assumption + * being that you should let coreboot set it up. It's quite + * messy to keep doing UART setup everywhere on these ARM SOCs. + */ + +/* word offset of registers from MEMBASE */ +enum { + /* RX and TX data. + * these are the lsb of the word + */ + RXDATA = 9, + TXDATA = 8, + + ERR = 5, + FIFOSTAT = 6, + RXCOUNT = 0xff, + RXFULL = 0x100, + RXREADY = 0x1ff, + TXFULL = 1<<24, +}; + +#define MEMBASE (u32 *)(phys_to_virt(lib_sysinfo.serial->baseaddr)) + +static inline u8 regreadb(u32 reg) +{ + return readb(MEMBASE + reg); +} + +static inline u32 regreadl(u32 reg) +{ + return readl(MEMBASE + reg); +} + +static inline void regwritel(u32 val, u32 reg) +{ + writel(val, MEMBASE + reg); +} + +static inline void regwriteb(u8 val, u32 reg) +{ + writeb(val, MEMBASE + reg); +} + +/* + * Initialise the serial port. + * This hardware is really complex, and we're not going to pretend + * it's a good idea to mess with it here. So, take what coreboot did + * and leave it at that. + */ +void serial_init(void) +{ +} + +int serial_havechar(void) +{ + return (regreadl(ERR)&RXREADY); +} + +int serial_getchar(void) +{ + /* wait for character to arrive */ + while (! serial_havechar()) + ; + return regreadl(RXDATA); +} + +static int serial_cansend(void) +{ + return (! (regreadl(FIFOSTAT)&TXFULL)); +} + +/* + * Output a single byte to the serial port. + * The function is defined as taking an int; unfortunate. + */ +void serial_putchar(unsigned int c) +{ + + /* wait for room in the tx FIFO */ + while (! serial_cansend()) + ; + + regwriteb(c, TXDATA); +}

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Patch set updated for coreboot: eb8fb19 libpayload: add support for the exynos5 UART
by Ronald G. Minnich 15 Feb '13

15 Feb '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2414 -gerrit commit eb8fb19a430333f1ce9fbe19ef17dee2d66f49d1 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Fri Feb 15 09:44:28 2013 -0800 libpayload: add support for the exynos5 UART This CL adds *limited* support for the exynos5 uart. It's a new BSD-licensed implementation. We support read, write, and test for input as in the existing serial.c. Because of the plethora of other hardware that it would bring in, we've decided for now to leave out configuration operations such as setting baud rate. Set it right in coreboot and leave it alone. Add two new variables, EXYNOS5_SERIAL_CONSOLE -- enable it EXYNOS5_SERIAL_BASE -- set the base in Config.in, add options for selecting the UART and setting its base address; a reasonable default is configured. Set that default into sysinfo if EXYNOS5_SERIAL_CONSOLE is set. Compile the UART in if EXYNOS5_SERIAL_CONSOLE is set. Add the slightly truncated code from coreboot; don't bother with an include file, only this one file needs to see the structs. This is one case where an include file would do more harm than good. Change-Id: Iff1f601a8ba5e69d63eb10763e748c92a03a3df8 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- payloads/libpayload/Config.in | 12 ++- payloads/libpayload/arch/armv7/sysinfo.c | 3 + payloads/libpayload/drivers/Makefile.inc | 1 + payloads/libpayload/drivers/exynos5250_uart.c | 117 ++++++++++++++++++++++++++ 4 files changed, 132 insertions(+), 1 deletion(-) diff --git a/payloads/libpayload/Config.in b/payloads/libpayload/Config.in index a14291d..ccc9449 100644 --- a/payloads/libpayload/Config.in +++ b/payloads/libpayload/Config.in @@ -70,7 +70,7 @@ choice config ARCH_ARMV7 bool "ARMv7" help - Support the x86 architecture + Support the ARMV7 architecture config ARCH_POWERPC bool "PowerPC" @@ -168,6 +168,16 @@ config SERIAL_CONSOLE bool "See output on the serial port console" default y +config EXYNOS5_SERIAL_CONSOLE + bool "Exynos 5xxx serial console" + depends on ARCH_ARMV7 + default n + +config EXYNOS5_SERIAL_BASE + hex "Base for the Exynos5 serial port" + depends on EXYNOS5_SERIAL_CONSOLE + default 0x12c30000 + config SERIAL_IOBASE hex "I/O base for the serial port (default 0x3f8)" depends on SERIAL_CONSOLE diff --git a/payloads/libpayload/arch/armv7/sysinfo.c b/payloads/libpayload/arch/armv7/sysinfo.c index 5aa5175..fc527d2 100644 --- a/payloads/libpayload/arch/armv7/sysinfo.c +++ b/payloads/libpayload/arch/armv7/sysinfo.c @@ -37,6 +37,9 @@ */ struct sysinfo_t lib_sysinfo = { .cpu_khz = 200, +#ifdef CONFIG_SERIAL_CONSOLE + .ser_base = CONFIG_EXYNOS5_SERIAL_BASE, +#endif }; int lib_get_sysinfo(void) diff --git a/payloads/libpayload/drivers/Makefile.inc b/payloads/libpayload/drivers/Makefile.inc index e3bb995..71c2519 100644 --- a/payloads/libpayload/drivers/Makefile.inc +++ b/payloads/libpayload/drivers/Makefile.inc @@ -34,6 +34,7 @@ libc-$(CONFIG_PCI) += pci.c libc-$(CONFIG_SPEAKER) += speaker.c libc-$(CONFIG_SERIAL_CONSOLE) += serial.c +libc-$(CONFIG_EXYNOS5_SERIAL_CONSOLE) += exynos5250_uart.c libc-$(CONFIG_PC_KEYBOARD) += keyboard.c diff --git a/payloads/libpayload/drivers/exynos5250_uart.c b/payloads/libpayload/drivers/exynos5250_uart.c new file mode 100644 index 0000000..d051f36 --- /dev/null +++ b/payloads/libpayload/drivers/exynos5250_uart.c @@ -0,0 +1,117 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2013 Google, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <libpayload-config.h> +#include <libpayload.h> + +/* + * this is a seriously cut-down UART implementation, the assumption + * being that you should let coreboot set it up. It's quite + * messy to keep doing UART setup everywhere on these ARM SOCs. + */ + +/* word offset of registers from MEMBASE */ +enum { + /* RX and TX data. + * these are the lsb of the word + */ + RXDATA = 9, + TXDATA = 8, + + ERR = 5, + FIFOSTAT = 6, + RXCOUNT = 0xff, + RXFULL = 0x100, + RXREADY = 0x1ff, + TXFULL = 1<<24, +}; + +#define MEMBASE (u32 *)(phys_to_virt(lib_sysinfo.serial->baseaddr)) + +static inline u8 regreadb(u32 reg) +{ + return readb(MEMBASE + reg); +} + +static inline u32 regreadl(u32 reg) +{ + return readl(MEMBASE + reg); +} + +static inline void regwritel(u32 val, u32 reg) +{ + writel(val, MEMBASE + reg); +} + +static inline void regwriteb(u8 val, u32 reg) +{ + writeb(val, MEMBASE + reg); +} + +/* + * Initialise the serial port. + * This hardware is really complex, and we're not going to pretend + * it's a good idea to mess with it here. So, take what coreboot did + * and leave it at that. + */ +void serial_init(void) +{ +} + +int serial_havechar(void) +{ + return (regreadl(ERR)&RXREADY); +} + +int serial_getchar(void) +{ + /* wait for character to arrive */ + while (! serial_havechar()) + ; + return regreadl(RXDATA); +} + +static int serial_cansend(void) +{ + return (! (regreadl(FIFOSTAT)&TXFULL)); +} + +/* + * Output a single byte to the serial port. + * The function is defined as taking an int; unfortunate. + */ +void serial_putchar(unsigned int c) +{ + + /* wait for room in the tx FIFO */ + while (! serial_cansend()) + ; + + regwriteb(c, TXDATA); +}

1 0

Patch set updated for coreboot: 70f53a3 libpayload: add support for the exynos5 UART
by Ronald G. Minnich 15 Feb '13

15 Feb '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2414 -gerrit commit 70f53a3c42d2259a33b350e62faa79b0a8f8279b Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Fri Feb 15 09:44:28 2013 -0800 libpayload: add support for the exynos5 UART This CL adds *limited* support for the exynos5 uart. It's a new BSD-licensed implementation. We support read, write, and test for input as in the existing serial.c. Because of the plethora of other hardware that it would bring in, we've decided for now to leave out configuration operations such as setting baud rate. Set it right in coreboot and leave it alone. Add two new variables, EXYNOS5_SERIAL_CONSOLE -- enable it EXYNOS5_SERIAL_BASE -- set the base in Config.in, add options for selecting the UART and setting its base address; a reasonable default is configured. Set that default into sysinfo if EXYNOS5_SERIAL_CONSOLE is set. Compile the UART in if EXYNOS5_SERIAL_CONSOLE is set. Add the slightly truncated code from coreboot; don't bother with an include file, only this one file needs to see the structs. This is one case where an include file would do more harm than good. Change-Id: Iff1f601a8ba5e69d63eb10763e748c92a03a3df8 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- payloads/libpayload/Config.in | 12 ++- payloads/libpayload/arch/armv7/sysinfo.c | 3 + payloads/libpayload/drivers/Makefile.inc | 1 + payloads/libpayload/drivers/exynos5250_uart.c | 128 ++++++++++++++++++++++++++ 4 files changed, 143 insertions(+), 1 deletion(-) diff --git a/payloads/libpayload/Config.in b/payloads/libpayload/Config.in index a14291d..ccc9449 100644 --- a/payloads/libpayload/Config.in +++ b/payloads/libpayload/Config.in @@ -70,7 +70,7 @@ choice config ARCH_ARMV7 bool "ARMv7" help - Support the x86 architecture + Support the ARMV7 architecture config ARCH_POWERPC bool "PowerPC" @@ -168,6 +168,16 @@ config SERIAL_CONSOLE bool "See output on the serial port console" default y +config EXYNOS5_SERIAL_CONSOLE + bool "Exynos 5xxx serial console" + depends on ARCH_ARMV7 + default n + +config EXYNOS5_SERIAL_BASE + hex "Base for the Exynos5 serial port" + depends on EXYNOS5_SERIAL_CONSOLE + default 0x12c30000 + config SERIAL_IOBASE hex "I/O base for the serial port (default 0x3f8)" depends on SERIAL_CONSOLE diff --git a/payloads/libpayload/arch/armv7/sysinfo.c b/payloads/libpayload/arch/armv7/sysinfo.c index 5aa5175..fc527d2 100644 --- a/payloads/libpayload/arch/armv7/sysinfo.c +++ b/payloads/libpayload/arch/armv7/sysinfo.c @@ -37,6 +37,9 @@ */ struct sysinfo_t lib_sysinfo = { .cpu_khz = 200, +#ifdef CONFIG_SERIAL_CONSOLE + .ser_base = CONFIG_EXYNOS5_SERIAL_BASE, +#endif }; int lib_get_sysinfo(void) diff --git a/payloads/libpayload/drivers/Makefile.inc b/payloads/libpayload/drivers/Makefile.inc index e3bb995..71c2519 100644 --- a/payloads/libpayload/drivers/Makefile.inc +++ b/payloads/libpayload/drivers/Makefile.inc @@ -34,6 +34,7 @@ libc-$(CONFIG_PCI) += pci.c libc-$(CONFIG_SPEAKER) += speaker.c libc-$(CONFIG_SERIAL_CONSOLE) += serial.c +libc-$(CONFIG_EXYNOS5_SERIAL_CONSOLE) += exynos5250_uart.c libc-$(CONFIG_PC_KEYBOARD) += keyboard.c diff --git a/payloads/libpayload/drivers/exynos5250_uart.c b/payloads/libpayload/drivers/exynos5250_uart.c new file mode 100644 index 0000000..731e41e --- /dev/null +++ b/payloads/libpayload/drivers/exynos5250_uart.c @@ -0,0 +1,128 @@ +/* + * (C) Copyright 2013 Google, Inc. + * (C) Copyright 2009 SAMSUNG Electronics + * Minkyu Kang <mk7.kang(a)samsung.com> + * Heungjun Kim <riverful.kim(a)samsung.com> + * + * based on drivers/serial/s3c64xx.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +/* + * this is a seriously cut-down UART implementation, the assumption + * being that you should let coreboot set it up. It's quite + * messy to keep doing UART setup everywhere on these ARM SOCs. + */ + +#include <libpayload-config.h> +#include <libpayload.h> + +/* baudrate rest value */ +union br_rest { + unsigned short slot; /* udivslot */ + unsigned char value; /* ufracval */ +}; + +struct s5p_uart { + unsigned int ulcon; + unsigned int ucon; + unsigned int ufcon; + unsigned int umcon; + unsigned int utrstat; + unsigned int uerstat; + unsigned int ufstat; + unsigned int umstat; + unsigned char utxh; + unsigned char res1[3]; + unsigned char urxh; + unsigned char res2[3]; + unsigned int ubrdiv; + union br_rest rest; + unsigned char res3[0xffd0]; +}; + +#define MEMBASE (struct s5p_uart *)(phys_to_virt(lib_sysinfo.serial->baseaddr)) +#define RX_FIFO_COUNT_MASK 0xff +#define RX_FIFO_FULL_MASK (1 << 8) +#define TX_FIFO_FULL_MASK (1 << 24) + +/* + * Initialise the serial port. + * This hardware is really complex, and we're not going to pretend + * it's a good idea to mess with it here. So, take what coreboot did + * and leave it at that. + */ +void serial_init(void) +{ +} + +static int exynos5_uart_err_check(int op) +{ + struct s5p_uart *uart = MEMBASE; + unsigned int mask; + + /* + * UERSTAT + * Break Detect [3] + * Frame Err [2] : receive operation + * Parity Err [1] : receive operation + * Overrun Err [0] : receive operation + */ + if (op) + mask = 0x8; + else + mask = 0xf; + + return readl(&uart->uerstat) & mask; +} + +int serial_havechar(void) +{ + struct s5p_uart *uart = MEMBASE; + return (readl(&uart->ufstat) & (RX_FIFO_COUNT_MASK | + RX_FIFO_FULL_MASK)); +} + +int serial_getchar(void) +{ + struct s5p_uart *uart = MEMBASE; + + /* wait for character to arrive */ + while (!(readl(&uart->ufstat) & (RX_FIFO_COUNT_MASK | + RX_FIFO_FULL_MASK))) { + if (exynos5_uart_err_check(0)) + return 0; + } + + return readb(&uart->urxh) & 0xff; +} + +/* + * Output a single byte to the serial port. + */ +void serial_putchar(unsigned int c) +{ + struct s5p_uart *uart = MEMBASE; + + /* wait for room in the tx FIFO */ + while ((readl(uart->ufstat) & TX_FIFO_FULL_MASK)) { + if (exynos5_uart_err_check(1)) + return; + } + + writeb(c, &uart->utxh); +}

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Patch merged into coreboot/master: 1cf46a7 ARMv7: Drop u-boot type remains
by gerrit＠coreboot.org 15 Feb '13

15 Feb '13

the following patch was just integrated into master: commit 1cf46a7bbf7881275ea74520e9e926abe18e5ffe Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Feb 14 17:06:43 2013 -0800 ARMv7: Drop u-boot type remains Just a mechanical cleanup. Change-Id: I0815625e629ab0b7ae6c948144085f1bd8cabfb5 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: http://review.coreboot.org/2408 Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Fri Feb 15 02:32:06 2013, giving +1 See http://review.coreboot.org/2408 for details. -gerrit

1 0

Patch merged into coreboot/master: 37955a2 Exynos5250: Drop unused file ehci-s5p.h
by gerrit＠coreboot.org 15 Feb '13

15 Feb '13

the following patch was just integrated into master: commit 37955a21d16e3626427f3685fdafe08297f9c67d Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Feb 14 16:58:00 2013 -0800 Exynos5250: Drop unused file ehci-s5p.h Change-Id: I39014377af718766ef86c149e2d2da3d97eaa728 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: http://review.coreboot.org/2407 Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Build-Tested: build bot (Jenkins) at Fri Feb 15 02:23:55 2013, giving +1 See http://review.coreboot.org/2407 for details. -gerrit

1 0

Patch set updated for coreboot: cfc311f libpayload: add support for the exynos5 UART
by Ronald G. Minnich 15 Feb '13

15 Feb '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2414 -gerrit commit cfc311f8d0b3cbdf99ff427d6e2fac4a3b72f57d Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Fri Feb 15 09:44:28 2013 -0800 libpayload: add support for the exynos5 UART This CL adds *limited* support for the exynos5 uart. IO operations are supported; because of the plethora of other hardware that it would bring in, we've decided for now to leave out configuration operations such as setting baud rate. Set it right in coreboot and leave it alone. We support read, write, and test for input as in the existing serial.c. Add two new variables, EXYNOS5_SERIAL_CONSOLE -- enable it EXYNOS5_SERIAL_BASE -- set the base in Config.in, add options for selecting the UART and setting its base address; a reasonable default is configured. Set that default into sysinfo if EXYNOS5_SERIAL_CONSOLE is set. Compile the UART in if EXYNOS5_SERIAL_CONSOLE is set. Add the slightly truncated code from coreboot; don't bother with an include file, only this one file needs to see the structs. This is one case where an include file would do more harm than good. Change-Id: Iff1f601a8ba5e69d63eb10763e748c92a03a3df8 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- payloads/libpayload/Config.in | 12 ++- payloads/libpayload/arch/armv7/sysinfo.c | 3 + payloads/libpayload/drivers/Makefile.inc | 1 + payloads/libpayload/drivers/exynos5250_uart.c | 128 ++++++++++++++++++++++++++ 4 files changed, 143 insertions(+), 1 deletion(-) diff --git a/payloads/libpayload/Config.in b/payloads/libpayload/Config.in index a14291d..ccc9449 100644 --- a/payloads/libpayload/Config.in +++ b/payloads/libpayload/Config.in @@ -70,7 +70,7 @@ choice config ARCH_ARMV7 bool "ARMv7" help - Support the x86 architecture + Support the ARMV7 architecture config ARCH_POWERPC bool "PowerPC" @@ -168,6 +168,16 @@ config SERIAL_CONSOLE bool "See output on the serial port console" default y +config EXYNOS5_SERIAL_CONSOLE + bool "Exynos 5xxx serial console" + depends on ARCH_ARMV7 + default n + +config EXYNOS5_SERIAL_BASE + hex "Base for the Exynos5 serial port" + depends on EXYNOS5_SERIAL_CONSOLE + default 0x12c30000 + config SERIAL_IOBASE hex "I/O base for the serial port (default 0x3f8)" depends on SERIAL_CONSOLE diff --git a/payloads/libpayload/arch/armv7/sysinfo.c b/payloads/libpayload/arch/armv7/sysinfo.c index 5aa5175..fc527d2 100644 --- a/payloads/libpayload/arch/armv7/sysinfo.c +++ b/payloads/libpayload/arch/armv7/sysinfo.c @@ -37,6 +37,9 @@ */ struct sysinfo_t lib_sysinfo = { .cpu_khz = 200, +#ifdef CONFIG_SERIAL_CONSOLE + .ser_base = CONFIG_EXYNOS5_SERIAL_BASE, +#endif }; int lib_get_sysinfo(void) diff --git a/payloads/libpayload/drivers/Makefile.inc b/payloads/libpayload/drivers/Makefile.inc index e3bb995..71c2519 100644 --- a/payloads/libpayload/drivers/Makefile.inc +++ b/payloads/libpayload/drivers/Makefile.inc @@ -34,6 +34,7 @@ libc-$(CONFIG_PCI) += pci.c libc-$(CONFIG_SPEAKER) += speaker.c libc-$(CONFIG_SERIAL_CONSOLE) += serial.c +libc-$(CONFIG_EXYNOS5_SERIAL_CONSOLE) += exynos5250_uart.c libc-$(CONFIG_PC_KEYBOARD) += keyboard.c diff --git a/payloads/libpayload/drivers/exynos5250_uart.c b/payloads/libpayload/drivers/exynos5250_uart.c new file mode 100644 index 0000000..731e41e --- /dev/null +++ b/payloads/libpayload/drivers/exynos5250_uart.c @@ -0,0 +1,128 @@ +/* + * (C) Copyright 2013 Google, Inc. + * (C) Copyright 2009 SAMSUNG Electronics + * Minkyu Kang <mk7.kang(a)samsung.com> + * Heungjun Kim <riverful.kim(a)samsung.com> + * + * based on drivers/serial/s3c64xx.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +/* + * this is a seriously cut-down UART implementation, the assumption + * being that you should let coreboot set it up. It's quite + * messy to keep doing UART setup everywhere on these ARM SOCs. + */ + +#include <libpayload-config.h> +#include <libpayload.h> + +/* baudrate rest value */ +union br_rest { + unsigned short slot; /* udivslot */ + unsigned char value; /* ufracval */ +}; + +struct s5p_uart { + unsigned int ulcon; + unsigned int ucon; + unsigned int ufcon; + unsigned int umcon; + unsigned int utrstat; + unsigned int uerstat; + unsigned int ufstat; + unsigned int umstat; + unsigned char utxh; + unsigned char res1[3]; + unsigned char urxh; + unsigned char res2[3]; + unsigned int ubrdiv; + union br_rest rest; + unsigned char res3[0xffd0]; +}; + +#define MEMBASE (struct s5p_uart *)(phys_to_virt(lib_sysinfo.serial->baseaddr)) +#define RX_FIFO_COUNT_MASK 0xff +#define RX_FIFO_FULL_MASK (1 << 8) +#define TX_FIFO_FULL_MASK (1 << 24) + +/* + * Initialise the serial port. + * This hardware is really complex, and we're not going to pretend + * it's a good idea to mess with it here. So, take what coreboot did + * and leave it at that. + */ +void serial_init(void) +{ +} + +static int exynos5_uart_err_check(int op) +{ + struct s5p_uart *uart = MEMBASE; + unsigned int mask; + + /* + * UERSTAT + * Break Detect [3] + * Frame Err [2] : receive operation + * Parity Err [1] : receive operation + * Overrun Err [0] : receive operation + */ + if (op) + mask = 0x8; + else + mask = 0xf; + + return readl(&uart->uerstat) & mask; +} + +int serial_havechar(void) +{ + struct s5p_uart *uart = MEMBASE; + return (readl(&uart->ufstat) & (RX_FIFO_COUNT_MASK | + RX_FIFO_FULL_MASK)); +} + +int serial_getchar(void) +{ + struct s5p_uart *uart = MEMBASE; + + /* wait for character to arrive */ + while (!(readl(&uart->ufstat) & (RX_FIFO_COUNT_MASK | + RX_FIFO_FULL_MASK))) { + if (exynos5_uart_err_check(0)) + return 0; + } + + return readb(&uart->urxh) & 0xff; +} + +/* + * Output a single byte to the serial port. + */ +void serial_putchar(unsigned int c) +{ + struct s5p_uart *uart = MEMBASE; + + /* wait for room in the tx FIFO */ + while ((readl(uart->ufstat) & TX_FIFO_FULL_MASK)) { + if (exynos5_uart_err_check(1)) + return; + } + + writeb(c, &uart->utxh); +}

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coreboot February 2013