coreboot February 2013

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New patch to review for coreboot: 826a0e7 AMD S3: Change S3_VOLATILE_POS to S3_DATA_POS
by Zheng Bao 19 Feb '13

19 Feb '13

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2438 -gerrit commit 826a0e79305cd7cd3a09cb5acfabf991b117fe17 Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Sun Feb 17 17:01:34 2013 +0800 AMD S3: Change S3_VOLATILE_POS to S3_DATA_POS S3_DATA_POS defines address where the whole S3 data is stored. Change-Id: I4155a0821e74a3653caaead890e5fec5677637aa Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- src/cpu/amd/agesa/s3_resume.h | 6 +++--- src/southbridge/amd/Makefile.inc | 4 ++-- src/southbridge/amd/agesa/hudson/Kconfig | 2 +- src/southbridge/amd/cimx/sb700/Kconfig | 2 +- src/southbridge/amd/cimx/sb800/Kconfig | 2 +- src/southbridge/amd/cimx/sb900/Kconfig | 2 +- 6 files changed, 9 insertions(+), 9 deletions(-) diff --git a/src/cpu/amd/agesa/s3_resume.h b/src/cpu/amd/agesa/s3_resume.h index 39ad30a..367cc3f 100644 --- a/src/cpu/amd/agesa/s3_resume.h +++ b/src/cpu/amd/agesa/s3_resume.h @@ -24,9 +24,9 @@ #define S3_DATA_VOLATILE_SIZE 0x6000 #define S3_DATA_MTRR_SIZE 0x1000 #define S3_DATA_NONVOLATILE_SIZE 0x1000 -#define S3_DATA_VOLATILE_POS CONFIG_S3_VOLATILE_POS -#define S3_DATA_MTRR_POS (CONFIG_S3_VOLATILE_POS + S3_DATA_VOLATILE_SIZE) -#define S3_DATA_NONVOLATILE_POS (CONFIG_S3_VOLATILE_POS + S3_DATA_VOLATILE_SIZE + S3_DATA_MTRR_SIZE) +#define S3_DATA_VOLATILE_POS CONFIG_S3_DATA_POS +#define S3_DATA_MTRR_POS (CONFIG_S3_DATA_POS + S3_DATA_VOLATILE_SIZE) +#define S3_DATA_NONVOLATILE_POS (CONFIG_S3_DATA_POS + S3_DATA_VOLATILE_SIZE + S3_DATA_MTRR_SIZE) typedef enum { S3DataTypeNonVolatile=0, ///< NonVolatile Data Type diff --git a/src/southbridge/amd/Makefile.inc b/src/southbridge/amd/Makefile.inc index 1b2cb1f..5f54314 100644 --- a/src/southbridge/amd/Makefile.inc +++ b/src/southbridge/amd/Makefile.inc @@ -20,14 +20,14 @@ ifeq ($(CONFIG_HAVE_ACPI_RESUME), y) ifeq ($(CONFIG_CPU_AMD_AGESA), y) $(obj)/coreboot_s3nv.rom: $(obj)/config.h - echo " S3 NVRAM $(CONFIG_S3_VOLATILE_POS) (S3 storage area)" + echo " S3 NVRAM $(CONFIG_S3_DATA_POS) (S3 storage area)" # force C locale, so cygwin awk doesn't try to interpret the 0xff below as UTF-8 (or worse) LC_ALL=C awk 'BEGIN {for (i=0; i<32768; i++) {printf "%c", 255}}' > $@.tmp mv $@.tmp $@ cbfs-files-y += s3nv s3nv-file := $(obj)/coreboot_s3nv.rom -s3nv-position := $(CONFIG_S3_VOLATILE_POS) +s3nv-position := $(CONFIG_S3_DATA_POS) s3nv-type := raw endif # CONFIG_CPU_AMD_AGESA == y diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index 35d8996..a469970 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -204,7 +204,7 @@ config RAID_MISC_ROM_POSITION The CONFIG_ROM_SIZE must larger than 0x100000. endif # HUDSON_SATA_RAID -config S3_VOLATILE_POS +config S3_DATA_POS hex "S3 volatile storage position" default 0xFFFF0000 depends on HAVE_ACPI_RESUME diff --git a/src/southbridge/amd/cimx/sb700/Kconfig b/src/southbridge/amd/cimx/sb700/Kconfig index ee740d5..706309d 100644 --- a/src/southbridge/amd/cimx/sb700/Kconfig +++ b/src/southbridge/amd/cimx/sb700/Kconfig @@ -60,7 +60,7 @@ config REDIRECT_SBCIMX_TRACE_TO_SERIAL Warning: Only enable this option when debuging or tracing AMD CIMX code. -config S3_VOLATILE_POS +config S3_DATA_POS hex "S3 volatile storage position" default 0xFFFF0000 depends on HAVE_ACPI_RESUME diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index 2620974..f56e017 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -122,7 +122,7 @@ config RAID_MISC_ROM_POSITION endif -config S3_VOLATILE_POS +config S3_DATA_POS hex "S3 volatile storage position" default 0xFFFF0000 depends on HAVE_ACPI_RESUME diff --git a/src/southbridge/amd/cimx/sb900/Kconfig b/src/southbridge/amd/cimx/sb900/Kconfig index 0efbf97..3cadba1 100755 --- a/src/southbridge/amd/cimx/sb900/Kconfig +++ b/src/southbridge/amd/cimx/sb900/Kconfig @@ -53,7 +53,7 @@ config BOOTBLOCK_SOUTHBRIDGE_INIT string default "southbridge/amd/cimx/sb900/bootblock.c" -config S3_VOLATILE_POS +config S3_DATA_POS hex "S3 volatile storage position" default 0xFFFF0000 depends on HAVE_ACPI_RESUME

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Patch set updated for coreboot: d6de565 SPI: Increase the default SPI page erase timeout
by Dave Frodin 19 Feb '13

19 Feb '13

Dave Frodin (dave.frodin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2449 -gerrit commit d6de5654d897392f7435405ba98fa7b4b1a7f625 Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Mon Feb 18 16:30:34 2013 -0700 SPI: Increase the default SPI page erase timeout The M25P32 device can take up to 600 ms to erase. Change-Id: I01e5bbb1f5bcf6ca68f6afe97d9b9052349d3242 Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> --- src/drivers/spi/spi_flash_internal.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/drivers/spi/spi_flash_internal.h b/src/drivers/spi/spi_flash_internal.h index 37ffee6..a738eaa 100644 --- a/src/drivers/spi/spi_flash_internal.h +++ b/src/drivers/spi/spi_flash_internal.h @@ -10,7 +10,7 @@ */ #define CONFIG_SYS_HZ 100 #define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ) -#define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ) +#define SPI_FLASH_PAGE_ERASE_TIMEOUT (20 * CONFIG_SYS_HZ) #define SPI_FLASH_SECTOR_ERASE_TIMEOUT (10 * CONFIG_SYS_HZ) /* Common commands */

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Patch merged into coreboot/master: 249cdc3 snow: add cpu_cluster and domain resources via devicetree.cb
by gerrit＠coreboot.org 19 Feb '13

19 Feb '13

the following patch was just integrated into master: commit 249cdc39431362241d154b6d091228e3c4c4e028 Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Feb 15 16:23:23 2013 -0800 snow: add cpu_cluster and domain resources via devicetree.cb This patch will cause the resource allocator to actually set aside the memory resources using methods in the previous patch. The coreboot table output will include "RAM" entries (there were none before): coreboot memory table: 0. 0000000040400000-00000000bff001ff: RAM 1. 00000000bff00200-00000000bff00fff: CONFIGURATION TABLES 2. 00000000bff01000-00000000bfffffff: RAM Change-Id: I5cd76e93fc232fdae1754253efb4e9269b3a20c0 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/2420 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Feb 19 01:04:23 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Tue Feb 19 17:21:30 2013, giving +2 See http://review.coreboot.org/2420 for details. -gerrit

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Patch set updated for coreboot: ba574e7 Inagua+children: fix simple copy & paste error in code to reset PCIe slots
by Paul Menzel 19 Feb '13

19 Feb '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2445 -gerrit commit ba574e787af05342ee1216c910fe75577a73ae26 Author: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Date: Mon Feb 18 18:56:48 2013 +0100 Inagua+children: fix simple copy & paste error in code to reset PCIe slots Looking at AssertSlotReset, the comments and all other case's it's obvious this is a simple copy & paste error where someone just forgot to change one occurrance of the GPIO nr. Also the AMD Inagua schematics show that GPIO02 is what they really meant. Also forward the fix to boards copied from Inagua (AMD South Station, Union Station, Asrock E350M1). Change-Id: I6b9a3d473245fa27604b2f148a730290277a88ed Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> --- src/mainboard/amd/inagua/BiosCallOuts.c | 2 +- src/mainboard/amd/south_station/BiosCallOuts.c | 2 +- src/mainboard/amd/union_station/BiosCallOuts.c | 2 +- src/mainboard/asrock/e350m1/BiosCallOuts.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/amd/inagua/BiosCallOuts.c b/src/mainboard/amd/inagua/BiosCallOuts.c index 3c38239..88bb1be 100644 --- a/src/mainboard/amd/inagua/BiosCallOuts.c +++ b/src/mainboard/amd/inagua/BiosCallOuts.c @@ -594,7 +594,7 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) Status = AGESA_SUCCESS; break; case DeassertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); Data8 |= BIT6 ; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 Status = AGESA_SUCCESS; diff --git a/src/mainboard/amd/south_station/BiosCallOuts.c b/src/mainboard/amd/south_station/BiosCallOuts.c index 3cfd741..0fc7bee 100644 --- a/src/mainboard/amd/south_station/BiosCallOuts.c +++ b/src/mainboard/amd/south_station/BiosCallOuts.c @@ -602,7 +602,7 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) Status = AGESA_SUCCESS; break; case DeassertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); Data8 |= BIT6 ; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 Status = AGESA_SUCCESS; diff --git a/src/mainboard/amd/union_station/BiosCallOuts.c b/src/mainboard/amd/union_station/BiosCallOuts.c index 3cfd741..0fc7bee 100644 --- a/src/mainboard/amd/union_station/BiosCallOuts.c +++ b/src/mainboard/amd/union_station/BiosCallOuts.c @@ -602,7 +602,7 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) Status = AGESA_SUCCESS; break; case DeassertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); Data8 |= BIT6 ; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 Status = AGESA_SUCCESS; diff --git a/src/mainboard/asrock/e350m1/BiosCallOuts.c b/src/mainboard/asrock/e350m1/BiosCallOuts.c index 2d6c9e0..8aa4398 100644 --- a/src/mainboard/asrock/e350m1/BiosCallOuts.c +++ b/src/mainboard/asrock/e350m1/BiosCallOuts.c @@ -592,7 +592,7 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) Status = AGESA_SUCCESS; break; case DeassertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); Data8 |= BIT6 ; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 Status = AGESA_SUCCESS;

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New patch to review for coreboot: 4b48791 AMD SB800: don't switch clock from 14 to 48 MHz for smscsuperio
by Jens Rottmann 19 Feb '13

19 Feb '13

Jens Rottmann (JRottmann(a)LiPPERTembedded.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2454 -gerrit commit 4b48791ecd0090cae99d0da6400f42f979da3c8c Author: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Date: Tue Feb 19 15:01:06 2013 +0100 AMD SB800: don't switch clock from 14 to 48 MHz for smscsuperio The power up default for 14M_25M_48M_OSC is 14 MHz. sb800/bootblock.c changes this to 48 MHz, which is the correct value for almost all SIOs. However, not for 'smscsuperio' (SMSC SCH311x), which needs the original 14 MHz. We could switch back to 14 in the mainboard's romstage.c, but then the clock frequency would change twice. This patch skips the SB800 clock switch if the SIO is smscsuperio. This does not affect any boards currently in the repository (yet). Change-Id: Icff41fd88dc41c08f3700ab4f786852f04eff2a4 Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> --- src/southbridge/amd/cimx/sb800/bootblock.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c index 0a339b0..8e88f4b 100644 --- a/src/southbridge/amd/cimx/sb800/bootblock.c +++ b/src/southbridge/amd/cimx/sb800/bootblock.c @@ -97,10 +97,13 @@ static void enable_clocks(void) reg8 &= ~(1 << 1); outb(reg8, 0xCD7); - // Program SB800 MiscCntrl Device_CLK1_sel for 48 MHz (default is 14 MHz) + // Program SB800 MiscClkCntrl to enable 14M_25M_48M_OSC clock output + // usually used for the Super-I/O reg32 = *acpi_mmio; - reg32 &= ~((1 << 0) | (1 << 2)); - reg32 |= 1 << 1; + reg32 &= ~((1 << 2) | (3 << 0)); // enable, 14 MHz +#ifndef CONFIG_SUPERIO_SMSC_SMSCSUPERIO + reg32 |= 2 << 0; // Device_CLK1_sel = 48 MHz +#endif *acpi_mmio = reg32; }

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New patch to review for coreboot: 4cf142e Persimmon: replace magic number with proper constant
by Jens Rottmann 19 Feb '13

19 Feb '13

Jens Rottmann (JRottmann(a)LiPPERTembedded.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2453 -gerrit commit 4cf142ebe72a8a1093abced10cd8162663d7467d Author: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Date: Tue Feb 19 14:46:31 2013 +0100 Persimmon: replace magic number with proper constant Use SMBUS0_BASE_ADDRESS, exactly like on Inagua. Change-Id: If095cd9d9b28b118b4072c7c9d345bf620b774c9 Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> --- src/mainboard/amd/persimmon/dimmSpd.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mainboard/amd/persimmon/dimmSpd.c b/src/mainboard/amd/persimmon/dimmSpd.c index 1343ae9..0d3eb2e 100644 --- a/src/mainboard/amd/persimmon/dimmSpd.c +++ b/src/mainboard/amd/persimmon/dimmSpd.c @@ -20,6 +20,7 @@ #include "Porting.h" #include "AGESA.h" #include "amdlib.h" +#include "OEM.h" /* SMBUS0_BASE_ADDRESS */ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info); #define DIMENSION(array)(sizeof (array)/ sizeof (array [0])) @@ -157,7 +158,7 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId]; if (spdAddress == 0) return AGESA_ERROR; - ioBase = 0xB00; + ioBase = SMBUS0_BASE_ADDRESS; setupFch (ioBase); return readspd (ioBase, spdAddress, (void *) info->Buffer, 128); }

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Patch set updated for coreboot: bc476f2 Inagua+children: fix simple copy & paste error in code to reset PCIe slots
by Jens Rottmann 19 Feb '13

19 Feb '13

Jens Rottmann (JRottmann(a)LiPPERTembedded.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2445 -gerrit commit bc476f23e28b69a177186995ab00cc0c48403835 Author: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Date: Mon Feb 18 18:56:48 2013 +0100 Inagua+children: fix simple copy & paste error in code to reset PCIe slots Looking at AssertSlotReset, the comments and all other 'case's it's obvious this is a simple copy&paste error where someone just forgot to change one occurrance of the GPIO nr. Also the AMD Inagua schematics show that GPIO02 is what they really meant. Also forwarded the fix to boards copied from Inagua (AMD South Station, Union Station, Asrock E250M1). Change-Id: I6b9a3d473245fa27604b2f148a730290277a88ed Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> --- src/mainboard/amd/inagua/BiosCallOuts.c | 2 +- src/mainboard/amd/south_station/BiosCallOuts.c | 2 +- src/mainboard/amd/union_station/BiosCallOuts.c | 2 +- src/mainboard/asrock/e350m1/BiosCallOuts.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/amd/inagua/BiosCallOuts.c b/src/mainboard/amd/inagua/BiosCallOuts.c index 3c38239..88bb1be 100644 --- a/src/mainboard/amd/inagua/BiosCallOuts.c +++ b/src/mainboard/amd/inagua/BiosCallOuts.c @@ -594,7 +594,7 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) Status = AGESA_SUCCESS; break; case DeassertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); Data8 |= BIT6 ; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 Status = AGESA_SUCCESS; diff --git a/src/mainboard/amd/south_station/BiosCallOuts.c b/src/mainboard/amd/south_station/BiosCallOuts.c index 3cfd741..0fc7bee 100644 --- a/src/mainboard/amd/south_station/BiosCallOuts.c +++ b/src/mainboard/amd/south_station/BiosCallOuts.c @@ -602,7 +602,7 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) Status = AGESA_SUCCESS; break; case DeassertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); Data8 |= BIT6 ; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 Status = AGESA_SUCCESS; diff --git a/src/mainboard/amd/union_station/BiosCallOuts.c b/src/mainboard/amd/union_station/BiosCallOuts.c index 3cfd741..0fc7bee 100644 --- a/src/mainboard/amd/union_station/BiosCallOuts.c +++ b/src/mainboard/amd/union_station/BiosCallOuts.c @@ -602,7 +602,7 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) Status = AGESA_SUCCESS; break; case DeassertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); Data8 |= BIT6 ; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 Status = AGESA_SUCCESS; diff --git a/src/mainboard/asrock/e350m1/BiosCallOuts.c b/src/mainboard/asrock/e350m1/BiosCallOuts.c index 2d6c9e0..8aa4398 100644 --- a/src/mainboard/asrock/e350m1/BiosCallOuts.c +++ b/src/mainboard/asrock/e350m1/BiosCallOuts.c @@ -592,7 +592,7 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) Status = AGESA_SUCCESS; break; case DeassertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); Data8 |= BIT6 ; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 Status = AGESA_SUCCESS;

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Patch set updated for coreboot: 45db4c1 Tyan S8226: Fix integer truncated warning
by Paul Menzel 19 Feb '13

19 Feb '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2452 -gerrit commit 45db4c157af9cb6f4da3fae8bce5b5b4cf99c10a Author: Martin Roth <martin.roth(a)se-eng.com> Date: Mon Feb 18 21:42:18 2013 -0700 Tyan S8226: Fix integer truncated warning Fix Warning: sb700_cfg.c:129, GNU Compiler 4 (gcc), Priority: Normal large integer implicitly truncated to unsigned type [-Woverflow] The issue here was that an 8 bit value was being placed into a 2-bit bitfield. $ more src/vendorcode/amd/cimx/sb700/SBTYPE.h […] UINT32 AzaliaSdin0 :2; //6 UINT32 AzaliaSdin1 :2; //8 UINT32 AzaliaSdin2 :2; //10 UINT32 AzaliaSdin3 :2; //12 $ more src/mainboard/tyan/s8226/sb700_cfg.h […] * SDIN0 is define at BIT0 & BIT1 * 00 - GPIO PIN * 01 - Reserved * 10 - As a Azalia SDIN pin * SDIN1 is define at BIT2 & BIT3 * SDIN2 is define at BIT4 & BIT5 * SDIN3 is define at BIT6 & BIT7 */ #ifndef AZALIA_SDIN_PIN #define AZALIA_SDIN_PIN 0x2A #endif […] $ more src/mainboard/tyan/s8226/sb700_cfg.c […] sb_config->AzaliaSdin0 = AZALIA_SDIN_PIN; […] The 8 bit value 0x2A (binary 00 10 10 10), was being used incorrectly – I believe the original intent of this value was to enable the SDIN pins 0, 1, & 2. Because it was getting truncated as it was put into AzaliaSdin0, this wasn't happening and only SDIN0 was being enabled. I am leaving only SDIN0 enabled at this point to as not change the actual behavior on the platform. Change-Id: Icaeb956926309dbfb5af25a36ccb842877e17a34 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/mainboard/tyan/s8226/sb700_cfg.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/mainboard/tyan/s8226/sb700_cfg.h b/src/mainboard/tyan/s8226/sb700_cfg.h index 45d7a92..ddfa7df 100644 --- a/src/mainboard/tyan/s8226/sb700_cfg.h +++ b/src/mainboard/tyan/s8226/sb700_cfg.h @@ -191,8 +191,7 @@ * SDIN3 is define at BIT6 & BIT7 */ #ifndef AZALIA_SDIN_PIN -//#define AZALIA_SDIN_PIN 0xAA -#define AZALIA_SDIN_PIN 0x2A +#define AZALIA_SDIN_PIN 0x02 #endif /**

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Patch merged into coreboot/master: 11a7db3 romcc: Don't fail on function prototypes
by gerrit＠coreboot.org 19 Feb '13

19 Feb '13

the following patch was just integrated into master: commit 11a7db3b570eb07759a7f4b5d8397be87518388d Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Feb 16 20:16:34 2013 +0100 romcc: Don't fail on function prototypes Instead, ignore them. One is as non-standard as the other and ignoring is more convenient since we don't need to guard prototypes with #ifndef __ROMCC_ all the time. Change-Id: I7be93a2ed0966ba1a86f0294132a204e6c8bf24f Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/2424 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth(a)se-eng.com> Reviewed-by: Marc Jones <marcj303(a)gmail.com> See http://review.coreboot.org/2424 for details. -gerrit

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Patch merged into coreboot/master: 70c85ea build system: Retire REQUIRES_BLOB
by gerrit＠coreboot.org 19 Feb '13

19 Feb '13

the following patch was just integrated into master: commit 70c85eab83564a9a5533afa16d4aa95416fb4424 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Feb 16 01:06:57 2013 +0100 build system: Retire REQUIRES_BLOB REQUIRES_BLOB assumes that all blob files come from the 3rdparty directory, builds failed when all files were configured to point to other sources. This change modifies the blob mechanism so that cbfs-files can be tagged as "required" with some specification what is missing. If the configured files can't be found (wrong path, missing file), the build system returns a list of descriptions, then aborts. Change-Id: Icc128e3afcee8acf49bff9409b93af7769db3517 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/2418 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth(a)se-eng.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Marc Jones <marcj303(a)gmail.com> See http://review.coreboot.org/2418 for details. -gerrit

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coreboot February 2013