coreboot March 2012

coreboot@coreboot.org

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718 discussions

New patch to review for coreboot: e97316e usbdebug_init() is a static function
by Stefan Reinauer 30 Mar '12

30 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/819 -gerrit commit e97316e1d704bd61aea45bc0e901ae9de6852210 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Mar 30 12:59:24 2012 -0700 usbdebug_init() is a static function Therefore, drop the prototype. Change-Id: I7b716215a3fd63167c0c566c2527b6a71bc76b19 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/include/usbdebug.h | 1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/src/include/usbdebug.h b/src/include/usbdebug.h index a7ab21f..2b55ec7 100644 --- a/src/include/usbdebug.h +++ b/src/include/usbdebug.h @@ -42,6 +42,5 @@ unsigned get_ehci_debug(void); void set_debug_port(unsigned port); int early_usbdebug_init(void); void usbdebug_tx_byte(unsigned char data); -int usbdebug_init(unsigned ehci_bar, unsigned offset, struct ehci_debug_info *info); #endif #endif

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New patch to review for coreboot: 0afabb9 Enable -Werror for romcc
by Stefan Reinauer 30 Mar '12

30 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/818 -gerrit commit 0afabb90a9f893e37097e0c393efe2d3f1f4cd94 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Mar 30 12:11:04 2012 -0700 Enable -Werror for romcc ... and remove some dead code. Change-Id: Id959bdf57af09db2a1f5742555c2dcabca38ac9a Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- util/romcc/Makefile | 2 +- util/romcc/romcc.c | 4 ---- 2 files changed, 1 insertions(+), 5 deletions(-) diff --git a/util/romcc/Makefile b/util/romcc/Makefile index 6543fbb..8242eb5 100644 --- a/util/romcc/Makefile +++ b/util/romcc/Makefile @@ -1,7 +1,7 @@ # Move the configuration defines to makefile.conf CC=gcc CPPFLAGS= -CFLAGS= -g -Wall $(CPPFLAGS) +CFLAGS= -g -Wall -Werror $(CPPFLAGS) CPROF_FLAGS=-pg -fprofile-arcs all: romcc test diff --git a/util/romcc/romcc.c b/util/romcc/romcc.c index c7ef223..1a939fb 100644 --- a/util/romcc/romcc.c +++ b/util/romcc/romcc.c @@ -9160,10 +9160,6 @@ static struct triple *decompose_index(struct compile_state *state, static void decompose_compound_types(struct compile_state *state) { struct triple *ins, *next, *first; -#if DEBUG_DECOMPOSE_HIRES - FILE *fp; - fp = state->dbgout; -#endif first = state->first; ins = first;

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New patch to review for coreboot: 9bf9535 Add Google ChromeOS vendor support
by Stefan Reinauer 30 Mar '12

30 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/817 -gerrit commit 9bf95351c917904deb99425c738cfb3386f57c35 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Mar 30 12:01:06 2012 -0700 Add Google ChromeOS vendor support Google's ChromeOS can be booted super fast and safely using coreboot. This adds the ChromeOS specific code that is required by all ChromeBooks to do this. Change-Id: Ic03ff090a569a27acbd798ce1e5f89a34897a2f2 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- Makefile.inc | 1 + src/vendorcode/Makefile.inc | 2 +- src/vendorcode/google/Makefile.inc | 20 +++++ src/vendorcode/google/chromeos/Kconfig | 29 +++++++- src/vendorcode/google/chromeos/Makefile.inc | 25 ++++++ src/vendorcode/google/chromeos/acpi/gnvs.asl | 37 +++++++++ src/vendorcode/google/chromeos/chromeos.c | 37 +++++++++ src/vendorcode/google/chromeos/chromeos.h | 40 ++++++++++ src/vendorcode/google/chromeos/gnvs.c | 88 +++++++++++++++++++++ src/vendorcode/google/chromeos/gnvs.h | 69 ++++++++++++++++ src/vendorcode/google/chromeos/vbnv.c | 109 ++++++++++++++++++++++++++ src/vendorcode/google/chromeos/vboot.c | 63 ++++++++++++---- 12 files changed, 504 insertions(+), 16 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index b4855d0..857ad16 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -43,6 +43,7 @@ subdirs-y += src/northbridge src/superio src/drivers src/cpu src/vendorcode subdirs-y += util/cbfstool util/sconfig subdirs-y += src/arch/$(ARCHDIR-y) subdirs-y += src/mainboard/$(MAINBOARDDIR) +subdirs-y += src/vendorcode subdirs-$(CONFIG_ARCH_X86) += src/pc80 diff --git a/src/vendorcode/Makefile.inc b/src/vendorcode/Makefile.inc index 16c0d68..e6d6bb1 100644 --- a/src/vendorcode/Makefile.inc +++ b/src/vendorcode/Makefile.inc @@ -1,2 +1,2 @@ subdirs-y += amd - +subdirs-y += google diff --git a/src/vendorcode/google/Makefile.inc b/src/vendorcode/google/Makefile.inc new file mode 100644 index 0000000..20d40a8 --- /dev/null +++ b/src/vendorcode/google/Makefile.inc @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +subdirs-$(CONFIG_CHROMEOS) += chromeos diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index f838b74..207431d 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -22,7 +22,34 @@ config CHROMEOS select TPM select CACHE_ROM help - Enable ChromeOS specific features + Enable ChromeOS specific features like the GPIO sub table in + the coreboot table. NOTE: Enabling this option on an unsupported + board will most likely break your build. +config VBNV_OFFSET + hex + default 0x26 + help + CMOS offset for VbNv data. This value must match cmos.layout + in the mainboard directory, minus 14 bytes for the RTC. + +config VBNV_SIZE + hex + default 0x10 + help + CMOS storage size for VbNv data. This value must match cmos.layout + in the mainboard directory. + +config CHROMEOS_RAMOOPS + bool "Reserve space for Chrome OS ramoops" + default y +config CHROMEOS_RAMOOPS_RAM_START + hex "Physical address of preserved RAM" + default 0x00f00000 + depends on CHROMEOS_RAMOOPS +config CHROMEOS_RAMOOPS_RAM_SIZE + hex "Size of preserved RAM" + default 0x00100000 + depends on CHROMEOS_RAMOOPS diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc new file mode 100644 index 0000000..c1b1cce --- /dev/null +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -0,0 +1,25 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +romstage-y += chromeos.c +ramstage-y += chromeos.c +romstage-y += vbnv.c +ramstage-y += vbnv.c +romstage-y += vboot.c +ramstage-y += gnvs.c diff --git a/src/vendorcode/google/chromeos/acpi/gnvs.asl b/src/vendorcode/google/chromeos/acpi/gnvs.asl new file mode 100644 index 0000000..dc4a0bf --- /dev/null +++ b/src/vendorcode/google/chromeos/acpi/gnvs.asl @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This is the ChromeOS specific ACPI information needed by + * the mainboard's chromeos.asl + */ + +VBT0, 32, // 0x000 - Boot Reason +VBT1, 32, // 0x004 - Active Main Firmware +VBT2, 32, // 0x008 - Active EC Firmware +VBT3, 16, // 0x00c - CHSW +VBT4, 2048, // 0x00e - HWID +VBT5, 512, // 0x10e - FWID +VBT6, 512, // 0x14e - FRID +VBT7, 32, // 0x18e - active main firmware type +VBT8, 32, // 0x192 - Recovery Reason +VBT9, 32, // 0x196 - FMAP base address +CHVD, 24576, // 0x19a - VDAT space filled by verified boot +VBTA, 32, // 0xd9a - pointer to smbios FWID +MEHH, 256, // 0xd9e - Management Engine Hash + // 0xdbe diff --git a/src/vendorcode/google/chromeos/chromeos.c b/src/vendorcode/google/chromeos/chromeos.c new file mode 100644 index 0000000..c1c3b38 --- /dev/null +++ b/src/vendorcode/google/chromeos/chromeos.c @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "chromeos.h" +#include <arch/coreboot_tables.h> +#include <console/console.h> + +int developer_mode_enabled(void) +{ + return get_developer_mode_switch(); +} + +int recovery_mode_enabled(void) +{ + /* TODO(reinauer): get information from VbInit. + * the recovery mode switch is not the only reason to go + * to recovery mode. + */ + return get_recovery_mode_switch() || get_recovery_mode_from_vbnv(); +} + diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h new file mode 100644 index 0000000..ec0f3b7 --- /dev/null +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __CHROMEOS_H__ +#define __CHROMEOS_H__ + +/* functions implemented per mainboard: */ +int get_developer_mode_switch(void); +int get_recovery_mode_switch(void); +#ifdef __PRE_RAM__ +void save_chromeos_gpios(void); +#endif + +/* functions implemented in vbnv.c: */ +int get_recovery_mode_from_vbnv(void); + +/* functions implemented in chromeos.c: */ +int developer_mode_enabled(void); +int recovery_mode_enabled(void); + +/* functions implemented in vboot.c */ +void init_chromeos(int bootmode); + +#endif diff --git a/src/vendorcode/google/chromeos/gnvs.c b/src/vendorcode/google/chromeos/gnvs.c new file mode 100644 index 0000000..8d0f9bb --- /dev/null +++ b/src/vendorcode/google/chromeos/gnvs.c @@ -0,0 +1,88 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <cbfs.h> +#include <console/console.h> +#include "gnvs.h" + +chromeos_acpi_t *vboot_data; +static u32 me_hash_saved[8]; + +void chromeos_init_vboot(chromeos_acpi_t *chromeos) +{ + vboot_data = chromeos; + + /* Copy saved ME hash into NVS */ + memcpy(vboot_data->mehh, me_hash_saved, sizeof(vboot_data->mehh)); +} + +void chromeos_set_vboot_data_ptr(void *blob) +{ + /* This code has to be rewritten to pass the vboot table + * pointer through the coreboot table instead of the + * FDT, since FDT support was rejected upstream. For now + * just make the code available for reference. + */ +#if 0 // CONFIG_ADD_FDT + int node_offset, addr_cell_len; + const u32 *cell; + uintptr_t table_addr = (uintptr_t)vboot_data; + u32 table_addr32; + u64 table_addr64; + void *table_ptr; + + cell = fdt_getprop(blob, 0, "#address-cells", NULL); + if (cell && *cell == 2) { + addr_cell_len = 8; + table_addr64 = cpu_to_fdt64(table_addr); + table_ptr = &table_addr64; + } else { + addr_cell_len = 4; + table_addr32 = cpu_to_fdt32(table_addr); + table_ptr = &table_addr32; + } + + node_offset = fdt_path_offset(blob, "/chromeos-config"); + if (node_offset < 0) { + printk(BIOS_ERR, + "Couldn't find /chromeos-config in the fdt.\n"); + return; + } + + if (fdt_setprop(blob, node_offset, "gnvs-vboot-table", + table_ptr, addr_cell_len) < 0) { + printk(BIOS_ERR, "Couldn't set gnvs-vboot-table.\n"); + } +#else + printk(BIOS_ERR, "Can't set gnvs-vboot-table.\n"); +#endif +} + +void chromeos_set_me_hash(u32 *hash, int len) +{ + if ((len*sizeof(u32)) > sizeof(vboot_data->mehh)) + return; + + /* Copy to NVS or save until it is ready */ + if (vboot_data) + memcpy(vboot_data->mehh, hash, len*sizeof(u32)); + else + memcpy(me_hash_saved, hash, len*sizeof(u32)); +} diff --git a/src/vendorcode/google/chromeos/gnvs.h b/src/vendorcode/google/chromeos/gnvs.h new file mode 100644 index 0000000..36922ba --- /dev/null +++ b/src/vendorcode/google/chromeos/gnvs.h @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __VENDORCODE_GOOGLE_CHROMEOS_GNVS_H +#define __VENDORCODE_GOOGLE_CHROMEOS_GNVS_H + +#define BOOT_REASON_OTHER 0 +#define BOOT_REASON_S3DIAG 9 + +#define CHSW_RECOVERY_X86 (1 << 1) +#define CHSW_RECOVERY_EC (1 << 2) +#define CHSW_DEVELOPER_SWITCH (1 << 5) +#define CHSW_FIRMWARE_WP_DIS (1 << 9) + +#define ACTIVE_MAINFW_RECOVERY 0 +#define ACTIVE_MAINFW_RW_A 1 +#define ACTIVE_MAINFW_RW_B 2 + +#define ACTIVE_MAINFW_TYPE_RECOVERY 0 +#define ACTIVE_MAINFW_TYPE_NORMAL 1 +#define ACTIVE_MAINFW_TYPE_DEVELOPER 2 + +#define RECOVERY_REASON_NONE 0 +#define RECOVERY_REASON_ME 1 +// TODO(reinauer) other recovery reasons? + +#define ACTIVE_ECFW_RO 0 +#define ACTIVE_ECFW_RW 1 + +typedef struct { + /* ChromeOS specific */ + u32 vbt0; // 00 boot reason + u32 vbt1; // 04 active main firmware + u32 vbt2; // 08 active ec firmware + u16 vbt3; // 0c CHSW + u8 vbt4[256]; // 0e HWID + u8 vbt5[64]; // 10e FWID + u8 vbt6[64]; // 14e FRID - 275 + u32 vbt7; // 18e active main firmware type + u32 vbt8; // 192 recovery reason + u32 vbt9; // 196 fmap base address + u8 vdat[3072]; // 19a + u32 vbt10; // d9a smbios bios version + u32 mehh[8]; // d9e management engine hash + // dbe +} __attribute__((packed)) chromeos_acpi_t; + +extern chromeos_acpi_t *vboot_data; +void chromeos_init_vboot(chromeos_acpi_t *chromeos); +void chromeos_set_vboot_data_ptr(void *); +void chromeos_set_me_hash(u32*, int); + +#endif diff --git a/src/vendorcode/google/chromeos/vbnv.c b/src/vendorcode/google/chromeos/vbnv.c new file mode 100644 index 0000000..2129461 --- /dev/null +++ b/src/vendorcode/google/chromeos/vbnv.c @@ -0,0 +1,109 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <console/console.h> +#include <pc80/mc146818rtc.h> +#include <cpu/x86/car.h> +#include "chromeos.h" + +#define VBNV_BLOCK_SIZE 16 /* Size of NV storage block in bytes */ + +/* Constants for NV storage. We use this rather than structs and + * bitfields so the data format is consistent across platforms and + * compilers. + */ +#define HEADER_OFFSET 0 +#define HEADER_MASK 0xC0 +#define HEADER_SIGNATURE 0x40 +#define HEADER_FIRMWARE_SETTINGS_RESET 0x20 +#define HEADER_KERNEL_SETTINGS_RESET 0x10 + +#define BOOT_OFFSET 1 +#define BOOT_DEBUG_RESET_MODE 0x80 +#define BOOT_TRY_B_COUNT_MASK 0x0F + +#define RECOVERY_OFFSET 2 +#define LOCALIZATION_OFFSET 3 + +#define DEV_FLAGS_OFFSET 4 +#define DEV_BOOT_USB_MASK 0x01 + +#define FIRMWARE_FLAGS_OFFSET 5 +#define FIRMWARE_TEST_ERR_FUNC_MASK 0x38 +#define FIRMWARE_TEST_ERR_FUNC_SHIFT 3 +#define FIRMWARE_TEST_ERR_NUM_MASK 0x07 + +#define KERNEL_FIELD_OFFSET 11 +#define CRC_OFFSET 15 + +static int vbnv_initialized CAR_GLOBAL; +uint8_t vbnv[CONFIG_VBNV_SIZE] CAR_GLOBAL; + +/* Return CRC-8 of the data, using x^8 + x^2 + x + 1 polynomial. A + * table-based algorithm would be faster, but for only 15 bytes isn't + * worth the code size. + */ + +static uint8_t crc8(const uint8_t * data, int len) +{ + unsigned crc = 0; + int i, j; + + for (j = len; j; j--, data++) { + crc ^= (*data << 8); + for (i = 8; i; i--) { + if (crc & 0x8000) + crc ^= (0x1070 << 3); + crc <<= 1; + } + } + + return (uint8_t) (crc >> 8); +} + +static void vbnv_setup(void) +{ + int i; + + for (i = 0; i < CONFIG_VBNV_SIZE; i++) + vbnv[i] = cmos_read(CONFIG_VBNV_OFFSET + 14 + i); + + /* Check data for consistency */ + if ((HEADER_SIGNATURE != (vbnv[HEADER_OFFSET] & HEADER_MASK)) + || (crc8(vbnv, CRC_OFFSET) != vbnv[CRC_OFFSET])) { + + /* Data is inconsistent (bad CRC or header), + * so reset to defaults + */ + memset(vbnv, 0, VBNV_BLOCK_SIZE); + vbnv[HEADER_OFFSET] = + (HEADER_SIGNATURE | HEADER_FIRMWARE_SETTINGS_RESET | + HEADER_KERNEL_SETTINGS_RESET); + } + vbnv_initialized = 1; +} + +int get_recovery_mode_from_vbnv(void) +{ + if (!vbnv_initialized) + vbnv_setup(); + return vbnv[RECOVERY_OFFSET]; +} diff --git a/src/vendorcode/google/chromeos/vboot.c b/src/vendorcode/google/chromeos/vboot.c index e0a8c9b..5bdb7a2 100644 --- a/src/vendorcode/google/chromeos/vboot.c +++ b/src/vendorcode/google/chromeos/vboot.c @@ -21,9 +21,11 @@ #include <console/console.h> #include <arch/acpi.h> #include <pc80/tpm.h> +#include <reset.h> #include "chromeos.h" //#define EXTRA_LOGGING +#define UBOOT_DOES_TPM_STARTUP #define TPM_LARGE_ENOUGH_COMMAND_SIZE 256 /* saves space in the firmware */ @@ -44,6 +46,12 @@ static const struct { }; static const struct { + u8 buffer[12]; +} tpm_startup_cmd = { + {0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x0, 0x0, 0x0, 0x99, 0x0, 0x1 } +}; + +static const struct { u8 buffer[10]; } tpm_continueselftest_cmd = { { 0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x53 } @@ -169,33 +177,60 @@ static u32 TlclSendReceive(const u8 * request, u8 * response, int max_length) return result; } -void init_vboot(void) +static void init_vboot(int bootmode) { u32 result; u8 response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; - printk(BIOS_DEBUG, "TPM: Init\n"); +#ifdef UBOOT_DOES_TPM_STARTUP + /* Doing TPM startup when we're not coming in on the S3 resume path + * saves us roughly 20ms in boot time only. This does not seem to + * be worth an API change to vboot_reference-firmware right now, so + * let's keep the code around, but just bail out early: + */ + if (bootmode != 2) + return; +#endif + + printk(BIOS_DEBUG, "Verified boot TPM initialization.\n"); + + printk(BIOS_SPEW, "TPM: Init\n"); if (tis_init()) return; - printk(BIOS_DEBUG, "TPM: Open\n"); + printk(BIOS_SPEW, "TPM: Open\n"); if (tis_open()) return; - printk(BIOS_DEBUG, "TPM: Resume\n"); - result = - TlclSendReceive(tpm_resume_cmd.buffer, response, sizeof(response)); - - if (result == TPM_E_INVALID_POSTINIT) { - /* We're on a platform where the TPM maintains power in S3, so - * it's already initialized. */ - printk(BIOS_DEBUG, "TPM: Already initialized.\n"); - return; + if (bootmode == 2) { + /* S3 Resume */ + printk(BIOS_SPEW, "TPM: Resume\n"); + result = TlclSendReceive(tpm_resume_cmd.buffer, + response, sizeof(response)); + if (result == TPM_E_INVALID_POSTINIT) { + /* We're on a platform where the TPM maintains power + * in S3, so it's already initialized. + */ + printk(BIOS_DEBUG, "TPM: Already initialized.\n"); + return; + } + } else { + printk(BIOS_SPEW, "TPM: Startup\n"); + result = TlclSendReceive(tpm_startup_cmd.buffer, + response, sizeof(response)); } + if (result == TPM_SUCCESS) { - printk(BIOS_DEBUG, "TPM: OK.\n"); + printk(BIOS_SPEW, "TPM: OK.\n"); return; } - // TODO(reinauer) hard reboot? + + printk(BIOS_ERR, "TPM: Error code 0x%x. Hard reset!\n", result); + hard_reset(); +} + +void init_chromeos(int bootmode) +{ + init_vboot(bootmode); }

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New patch to review for coreboot: 7b1da0f Make libpayload parse the coreboot tables before setting up the consoles
by Stefan Reinauer 30 Mar '12

30 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/816 -gerrit commit 7b1da0fb2b5dbc8cc7269811ac36bf52f3635b15 Author: Gabe Black <gabeblack(a)google.com> Date: Mon Mar 5 15:49:32 2012 -0800 Make libpayload parse the coreboot tables before setting up the consoles At least one of the console drivers, coreboot fb, uses information in the sysinfo structure to set itself up. If that structure hasn't been populated, the driver decides that there is no framebuffer and disables itself. Reversing the order these are set up fixes that problem. Change-Id: Idd8b5518980dfdd82fd4359dd0133ab7736fc428 Signed-off-by: Gabe Black <gabeblack(a)google.com> --- payloads/libpayload/arch/i386/main.c | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/payloads/libpayload/arch/i386/main.c b/payloads/libpayload/arch/i386/main.c index 378c6f3..36cfb69 100644 --- a/payloads/libpayload/arch/i386/main.c +++ b/payloads/libpayload/arch/i386/main.c @@ -46,12 +46,12 @@ void start_main(void) { extern int main(int argc, char **argv); - /* Set up the consoles. */ - console_init(); - /* Gather system information. */ lib_get_sysinfo(); + /* Set up the consoles. */ + console_init(); + /* * Any other system init that has to happen before the * user gets control goes here.

1 0

New patch to review for coreboot: 051b64d Force coreboot mconf to create temp files in the output directory
by Stefan Reinauer 30 Mar '12

30 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/815 -gerrit commit 051b64d6dda2a829454e5df752134dcbb0a35ba1 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Mon Oct 24 14:06:23 2011 -0700 Force coreboot mconf to create temp files in the output directory This change partially addresses the problem with attempting to generate coreboot image out of tree. The configuration step fails when in cheroot, if the destination directory is placed in /tmp. The problem is that the mconf package tries renaming the temporary file created in the local directory into the destination config file. If the destination root and the local directory are located on different file systems, the rename operation fails. The proper fix (still upcoming) would be to identify all places where mconf creates temp files, and make sure that all temp files get created in the destination tree. This change modifies just one location, which prevents building out of tree in the most common case. Test: run the following in the coreboot directory in chroot: (coreboot) cp config.lumpy .config (coreboot) /bin/rm -rf /tmp/cb (coreboot) CROSS_COMPILE=i686-pc-linux-gnu- make obj=/tmp/cb oldconfig (coreboot) CROSS_COMPILE=i686-pc-linux-gnu- make obj=/tmp/cb Observe the build succeed (it was failing during the config phase before this change) Change-Id: If4506e984b8afc192a1689c7b0aa956dd35f66c6 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- util/kconfig/confdata.c | 53 ++++++++++++++++++++++++++++++++++++++-------- 1 files changed, 43 insertions(+), 10 deletions(-) diff --git a/util/kconfig/confdata.c b/util/kconfig/confdata.c index 79e0b35..df39fcc 100644 --- a/util/kconfig/confdata.c +++ b/util/kconfig/confdata.c @@ -674,6 +674,33 @@ out: return res; } +/* + * Return malloced string the contents of which are a concatenation of the + * directory name of the first argument and the second argument. + */ +static char* get_tmp_file_name(const char* base, const char *tmp_name) +{ + char *file_name, *p; + /* for sure a few bytes longer than needed */ + int file_name_size = strlen(base) + sizeof(file_name) + 10; + + file_name = malloc(file_name_size); + if (!file_name) { + fprintf(stderr, "%s:%d: failed to allocate %d bytes\n", + __FILE__, __LINE__, file_name_size); + return 0; + } + + strcpy(file_name, base); + p = strrchr(file_name, '/'); + if (p) + strcpy(p + 1, tmp_name); + else + strcpy(file_name, tmp_name); + + return file_name; +} + int conf_write_autoconf(void) { struct symbol *sym; @@ -682,10 +709,19 @@ int conf_write_autoconf(void) FILE *out, *out_h; time_t now; int i, l; - char tmpname[128], tmpname_h[128]; + char *tmp_conf, *tmp_conf_h; sym_clear_all_valid(); + name = getenv("KCONFIG_AUTOHEADER"); + if (!name) + name = "include/linux/autoconf.h"; + + tmp_conf = get_tmp_file_name(name, ".tmpconfig"); + tmp_conf_h = get_tmp_file_name(name, ".tmpconfig.h"); + if (!tmp_conf || !tmp_conf_h) + return 1; + file_write_dep("build/auto.conf.cmd"); #if 0 @@ -693,13 +729,11 @@ int conf_write_autoconf(void) return 1; #endif - sprintf(tmpname, ".tmpconfig.%d", (int)getpid()); - out = fopen(tmpname, "w"); + out = fopen(tmp_conf, "w"); if (!out) return 1; - sprintf(tmpname_h, ".tmpconfig.h.%d", (int)getpid()); - out_h = fopen(tmpname_h, "w"); + out_h = fopen(tmp_conf_h, "w"); if (!out_h) { fclose(out); return 1; @@ -790,11 +824,8 @@ int conf_write_autoconf(void) fclose(out); fclose(out_h); - name = getenv("KCONFIG_AUTOHEADER"); - if (!name) - name = "include/linux/autoconf.h"; UNLINK_IF_NECESSARY(name); - if (rename(tmpname_h, name)) + if (rename(tmp_conf_h, name)) return 1; name = getenv("KCONFIG_AUTOCONFIG"); if (!name) @@ -804,9 +835,11 @@ int conf_write_autoconf(void) * and this marks the successful completion of the previous steps. */ UNLINK_IF_NECESSARY(name); - if (rename(tmpname, name)) + if (rename(tmp_conf, name)) return 1; + free(tmp_conf_h); + free(tmp_conf); return 0; }

1 0

New patch to review for coreboot: 41c6065 Add a "remove" command to cbfstool
by Stefan Reinauer 30 Mar '12

30 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/814 -gerrit commit 41c6065a48ad409b8d2dbf9d54e42df263c2939f Author: Gabe Black <gabeblack(a)google.com> Date: Fri Jan 27 00:33:47 2012 -0800 Add a "remove" command to cbfstool This command removes the first file it finds with the given name by changing its type to CBFS_COMPONENT_NULL and setting the first character of its name to a null terminator. If the "files" immediately before or after the target file are already marked as empty, they're all merged together into one large file. Change-Id: Idc6b2a4c355c3f039c2ccae81866e3ed6035539b Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-by: Ronald G. Minnich <rminnich(a)google.com> --- util/cbfstool/cbfstool.c | 30 ++++++++++++++++++++++++ util/cbfstool/common.c | 56 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 86 insertions(+), 0 deletions(-) diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index 939221e..9dbdc1c 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -29,6 +29,7 @@ typedef enum { CMD_ADD, CMD_ADD_PAYLOAD, CMD_ADD_STAGE, + CMD_REMOVE, CMD_CREATE, CMD_LOCATE, CMD_PRINT, @@ -195,6 +196,33 @@ static int cbfs_add_stage(int argc, char **argv) return 0; } +static int cbfs_remove(int argc, char **argv) +{ + char *romname = argv[1]; + char *cmd = argv[2]; + void *rom = loadrom(romname); + + if (rom == NULL) { + printf("Could not load ROM image '%s'.\n", romname); + return 1; + } + + if (argc < 4) { + printf("not enough arguments to '%s'.\n", cmd); + return 1; + } + + char *cbfsname = argv[3]; + + if (remove_file_from_cbfs(cbfsname)) { + printf("Removing file '%s' failed.\n", cbfsname); + return 1; + } + if (writerom(romname, rom, romsize)) + return 1; + return 0; +} + static int cbfs_create(int argc, char **argv) { char *romname = argv[1]; @@ -275,6 +303,7 @@ static const struct command commands[] = { {CMD_ADD, "add", cbfs_add}, {CMD_ADD_PAYLOAD, "add-payload", cbfs_add_payload}, {CMD_ADD_STAGE, "add-stage", cbfs_add_stage}, + {CMD_REMOVE, "remove", cbfs_remove}, {CMD_CREATE, "create", cbfs_create}, {CMD_LOCATE, "locate", cbfs_locate}, {CMD_PRINT, "print", cbfs_print}, @@ -292,6 +321,7 @@ static void usage(void) " add FILE NAME TYPE [base address] Add a component\n" " add-payload FILE NAME [COMP] [base] Add a payload to the ROM\n" " add-stage FILE NAME [COMP] [base] Add a stage to the ROM\n" + " remove FILE NAME Remove a component\n" " create SIZE BOOTBLOCK [ALIGN] Create a ROM file\n" " locate FILE NAME ALIGN Find a place for a file of that size\n" " print Show the contents of the ROM\n" diff --git a/util/cbfstool/common.c b/util/cbfstool/common.c index df74421..49da7ae 100644 --- a/util/cbfstool/common.c +++ b/util/cbfstool/common.c @@ -350,6 +350,62 @@ int add_file_to_cbfs(void *content, uint32_t contentsize, uint32_t location) return 1; } + +static struct cbfs_file *merge_adjacent_files(struct cbfs_file *first, + struct cbfs_file *second) +{ + uint32_t new_length = + ntohl(first->len) + ntohl(second->len) + ntohl(second->offset); + first->len = htonl(new_length); + first->checksum = 0; // FIXME? + return first; +} + +static struct cbfs_file *next_file(struct cbfs_file *prev) +{ + uint32_t pos = (prev == NULL) ? phys_start : + ALIGN(virt_to_phys(prev) + ntohl(prev->len) + ntohl(prev->offset), + align); + + for (; pos < phys_end; pos += align) { + if (cbfs_file_header(pos)) + return (struct cbfs_file *)phys_to_virt(pos); + } + return NULL; +} + + +int remove_file_from_cbfs(const char *filename) +{ + struct cbfs_file *prev = NULL; + struct cbfs_file *cur = next_file(prev); + struct cbfs_file *next = next_file(cur); + for (; cur; prev = cur, cur = next, next = next_file(next)) { + + /* Check if this is the file to remove. */ + char *name = (char *)cur + sizeof(*cur); + if (strcmp(name, filename)) + continue; + + /* Mark the file as free space and erase its name. */ + cur->type = CBFS_COMPONENT_NULL; + name[0] = '\0'; + + /* Merge it with the previous file if possible. */ + if (prev && prev->type == CBFS_COMPONENT_NULL) + cur = merge_adjacent_files(prev, cur); + + /* Merge it with the next file if possible. */ + if (next && next->type == CBFS_COMPONENT_NULL) + merge_adjacent_files(cur, next); + + return 0; + } + printf("CBFS file %s not found.\n", filename); + return 1; +} + + /* returns new data block with cbfs_file header, suitable to dump into the ROM. location returns the new location that points to the cbfs_file header */ void *create_cbfs_file(const char *filename, void *data, uint32_t * datasize,

1 0

Patch merged into coreboot/master: 1efff26 Fix warnings in coreboot utilities.
by gerrit＠coreboot.org 30 Mar '12

30 Mar '12

the following patch was just integrated into master: commit 1efff2687bff946fd09d6f7f7d54419e3f70fe83 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Nov 14 12:40:34 2011 -0800 Fix warnings in coreboot utilities. - Fix some poor programming practice (breaks of strict aliasing as well as not checking the return value of read) - Use PRIx64 instead of %llx to prevent compilation warnings with both 32bit and 64bit compilers - Use same compiler command options when linking inteltool and when detecting libpci for inteltool Change-Id: I08b2e8d1bbc908f6b1f26d25cb3a4b03d818e124 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Fri Mar 30 19:26:52 2012, giving +1 See http://review.coreboot.org/752 for details. -gerrit

1 0

separate mailling list for gerrit mails?
by Patrick Georgi 30 Mar '12

30 Mar '12

Hi, this came up on IRC again, but I think the issue requires wider discussion: Several people asked if gerrit mails can be moved to a separate mailing list to reduce the "mechanic" noise. We're highly flexible there, so we can keep it like it is, reduce the number of mail types, send different types to different lists, ... One proposal was to move all gerrit mail to coreboot-gerrit@ or so. A variant of that could be to move all gerrit mail to coreboot-gerrit@ except for the "change merged to master" mails, so people have an easier overview on what happens in our main branch. So asking generally: Do you like it the way it is, or do you think it should change, and how? Patrick

7 7

Patch set updated for coreboot: 1efff26 Fix warnings in coreboot utilities.
by Stefan Reinauer 30 Mar '12

30 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/752 -gerrit commit 1efff2687bff946fd09d6f7f7d54419e3f70fe83 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Nov 14 12:40:34 2011 -0800 Fix warnings in coreboot utilities. - Fix some poor programming practice (breaks of strict aliasing as well as not checking the return value of read) - Use PRIx64 instead of %llx to prevent compilation warnings with both 32bit and 64bit compilers - Use same compiler command options when linking inteltool and when detecting libpci for inteltool Change-Id: I08b2e8d1bbc908f6b1f26d25cb3a4b03d818e124 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- util/inteltool/Makefile | 4 ++-- util/inteltool/cpu.c | 7 +++---- util/inteltool/inteltool.c | 4 +++- util/inteltool/memory.c | 5 +++-- util/inteltool/pcie.c | 7 ++++--- util/nvramtool/cli/nvramtool.c | 6 +++++- 6 files changed, 20 insertions(+), 13 deletions(-) diff --git a/util/inteltool/Makefile b/util/inteltool/Makefile index 6a01173..d754005 100644 --- a/util/inteltool/Makefile +++ b/util/inteltool/Makefile @@ -42,7 +42,7 @@ endif all: pciutils dep $(PROGRAM) $(PROGRAM): $(OBJS) - $(CC) -o $(PROGRAM) $(OBJS) $(LDFLAGS) + $(CC) $(CFLAGS) -o $(PROGRAM) $(OBJS) $(LDFLAGS) clean: rm -f $(PROGRAM) *.o *~ @@ -59,7 +59,7 @@ pciutils: printf "struct pci_access *pacc;\n"; \ printf "int main(int argc, char **argv)\n"; \ printf "{ pacc = pci_alloc(); return 0; }\n"; ) > .test.c ) - @$(CC) $(CFLAGS) $(LDFLAGS) .test.c -o .test &>/dev/null && \ + @$(CC) $(CFLAGS) .test.c -o .test $(LDFLAGS) &>/dev/null && \ printf "found.\n" || ( printf "not found.\n\n"; \ printf "Please install pciutils-devel and zlib-devel.\n"; \ printf "See README for more information.\n\n"; \ diff --git a/util/inteltool/cpu.c b/util/inteltool/cpu.c index 20748bd..f018381 100644 --- a/util/inteltool/cpu.c +++ b/util/inteltool/cpu.c @@ -57,7 +57,7 @@ int msr_readerror = 0; msr_t rdmsr(int addr) { - uint8_t buf[8]; + uint32_t buf[2]; msr_t msr = { 0xffffffff, 0xffffffff }; if (lseek(fd_msr, (off_t) addr, SEEK_SET) == -1) { @@ -67,9 +67,8 @@ msr_t rdmsr(int addr) } if (read(fd_msr, buf, 8) == 8) { - msr.lo = *(uint32_t *)buf; - msr.hi = *(uint32_t *)(buf + 4); - + msr.lo = buf[0]; + msr.hi = buf[1]; return msr; } diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 6b99605..e5c2b86 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -21,6 +21,7 @@ #include <stdio.h> #include <stdlib.h> +#include <inttypes.h> #include <getopt.h> #include <fcntl.h> #include <sys/mman.h> @@ -99,7 +100,8 @@ void *map_physical(uint64_t phys_addr, size_t len) fd_mem, (off_t) phys_addr); if (virt_addr == MAP_FAILED) { - printf("Error mapping physical memory 0x%08lx[0x%zx]\n", phys_addr, len); + printf("Error mapping physical memory 0x%08" PRIx64 "[0x%zx]\n", + phys_addr, len); return NULL; } diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c index 9230419..18300ac 100644 --- a/util/inteltool/memory.c +++ b/util/inteltool/memory.c @@ -20,6 +20,7 @@ #include <stdio.h> #include <stdlib.h> +#include <inttypes.h> #include "inteltool.h" /* @@ -130,9 +131,9 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc) } if (nb->device_id == PCI_DEVICE_ID_INTEL_82865) - printf("BAR6 = 0x%08llx (MEM)\n\n", mchbar_phys); + printf("BAR6 = 0x%08" PRIx64 " (MEM)\n\n", mchbar_phys); else - printf("MCHBAR = 0x%08llx (MEM)\n\n", mchbar_phys); + printf("MCHBAR = 0x%08" PRIx64 " (MEM)\n\n", mchbar_phys); for (i = 0; i < size; i += 4) { if (*(uint32_t *)(mchbar + i)) diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c index 4913150..ea23835 100644 --- a/util/inteltool/pcie.c +++ b/util/inteltool/pcie.c @@ -19,6 +19,7 @@ #include <stdio.h> #include <stdlib.h> +#include <inttypes.h> #include "inteltool.h" /* @@ -72,7 +73,7 @@ int print_epbar(struct pci_dev *nb) exit(1); } - printf("EPBAR = 0x%08llx (MEM)\n\n", epbar_phys); + printf("EPBAR = 0x%08" PRIx64 " (MEM)\n\n", epbar_phys); for (i = 0; i < size; i += 4) { if (*(uint32_t *)(epbar + i)) printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(epbar+i)); @@ -135,7 +136,7 @@ int print_dmibar(struct pci_dev *nb) exit(1); } - printf("DMIBAR = 0x%08llx (MEM)\n\n", dmibar_phys); + printf("DMIBAR = 0x%08" PRIx64 " (MEM)\n\n", dmibar_phys); for (i = 0; i < size; i += 4) { if (*(uint32_t *)(dmibar + i)) printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(dmibar+i)); @@ -213,7 +214,7 @@ int print_pciexbar(struct pci_dev *nb) return 1; } - printf("PCIEXBAR: 0x%08llx\n", pciexbar_phys); + printf("PCIEXBAR: 0x%08" PRIx64 "\n", pciexbar_phys); pciexbar = map_physical(pciexbar_phys, (max_busses * 1024 * 1024)); diff --git a/util/nvramtool/cli/nvramtool.c b/util/nvramtool/cli/nvramtool.c index 11a1a70..bcb10bb 100644 --- a/util/nvramtool/cli/nvramtool.c +++ b/util/nvramtool/cli/nvramtool.c @@ -143,7 +143,11 @@ int main(int argc, char *argv[]) if (fd_stat.st_size < 128) { lseek(fd, 127, SEEK_SET); - write(fd, "\0", 1); + if (write(fd, "\0", 1) != 1) { + fprintf(stderr, "Unable to extended '%s' to its full size.\n", + nvramtool_op_modifiers[NVRAMTOOL_MOD_USE_CMOS_FILE].param); + exit(1); + } fsync(fd); }

1 0

How to make a release build ?
by Cui Lei 30 Mar '12

30 Mar '12

hi everyone, I want to buile a release coreboot , in other words, I don't want my coreboot to print any boot messages when booting. I did not find any options in the "menuconfig menu". Thanks a lot. BRs, Rock Cui

2 1

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coreboot March 2012