coreboot March 2012

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Patch set updated for coreboot: daead29 Fix warnings in coreboot utilities.
by Stefan Reinauer 30 Mar '12

30 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/752 -gerrit commit daead297e74b39a79b5ef2851615b3ac425cd078 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Nov 14 12:40:34 2011 -0800 Fix warnings in coreboot utilities. Fix some poor programming practice (breaks of strict aliasing as well as not checking the return value of read) Change-Id: I08b2e8d1bbc908f6b1f26d25cb3a4b03d818e124 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- util/inteltool/cpu.c | 6 ++++-- util/inteltool/inteltool.c | 4 +++- util/nvramtool/cli/nvramtool.c | 3 ++- 3 files changed, 9 insertions(+), 4 deletions(-) diff --git a/util/inteltool/cpu.c b/util/inteltool/cpu.c index 20748bd..3bffa4e 100644 --- a/util/inteltool/cpu.c +++ b/util/inteltool/cpu.c @@ -67,8 +67,10 @@ msr_t rdmsr(int addr) } if (read(fd_msr, buf, 8) == 8) { - msr.lo = *(uint32_t *)buf; - msr.hi = *(uint32_t *)(buf + 4); + msr.lo = buf[0] | (buf[1] << 8) | + (buf[2] << 16) | (buf[3] << 24); + msr.hi = buf[4] | (buf[5] << 8) | + (buf[6] << 16) | (buf[7] << 24); return msr; } diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 6b99605..e5c2b86 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -21,6 +21,7 @@ #include <stdio.h> #include <stdlib.h> +#include <inttypes.h> #include <getopt.h> #include <fcntl.h> #include <sys/mman.h> @@ -99,7 +100,8 @@ void *map_physical(uint64_t phys_addr, size_t len) fd_mem, (off_t) phys_addr); if (virt_addr == MAP_FAILED) { - printf("Error mapping physical memory 0x%08lx[0x%zx]\n", phys_addr, len); + printf("Error mapping physical memory 0x%08" PRIx64 "[0x%zx]\n", + phys_addr, len); return NULL; } diff --git a/util/nvramtool/cli/nvramtool.c b/util/nvramtool/cli/nvramtool.c index 11a1a70..20097b8 100644 --- a/util/nvramtool/cli/nvramtool.c +++ b/util/nvramtool/cli/nvramtool.c @@ -143,7 +143,8 @@ int main(int argc, char *argv[]) if (fd_stat.st_size < 128) { lseek(fd, 127, SEEK_SET); - write(fd, "\0", 1); + if (write(fd, "\0", 1) != 1) + fprintf(stderr, "Write failed.\n"); fsync(fd); }

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Patch set updated for coreboot: f7d1a96 use movsl for copying resume memory back
by Stefan Reinauer 30 Mar '12

30 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/755 -gerrit commit f7d1a9683d8874c7c6dd3fc6dc763f594d285575 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Nov 17 13:03:38 2011 -0800 use movsl for copying resume memory back It's not significantly faster, but easier to read and smaller. Change-Id: Ibab0b478873912d67bf1f07743f628586353368a Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/x86/boot/wakeup.S | 23 ++++++----------------- 1 files changed, 6 insertions(+), 17 deletions(-) diff --git a/src/arch/x86/boot/wakeup.S b/src/arch/x86/boot/wakeup.S index a1df4d5..8ae337c 100644 --- a/src/arch/x86/boot/wakeup.S +++ b/src/arch/x86/boot/wakeup.S @@ -38,23 +38,12 @@ __wakeup: movw %ax, (__wakeup_segment) /* Then overwrite coreboot with our backed up memory */ - movl 8(%esp), %esi - movl 12(%esp), %edi - movl 16(%esp), %ecx - shrl $4, %ecx -1: - movl 0(%esi),%eax - movl 4(%esi),%edx - movl 8(%esi),%ebx - movl 12(%esi),%ebp - addl $16,%esi - subl $1,%ecx - movl %eax,0(%edi) - movl %edx,4(%edi) - movl %ebx,8(%edi) - movl %ebp,12(%edi) - leal 16(%edi),%edi - jne 1b + cld + movl 8(%esp), %esi + movl 12(%esp), %edi + movl 16(%esp), %ecx + shrl $2, %ecx + rep movsl /* Activate the right segment descriptor real mode. */ ljmp $0x28, $RELOCATED(1f)

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Patch set updated for coreboot: 21277f9 Make MTRR min hole alignment 64MB
by Stefan Reinauer 30 Mar '12

30 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/765 -gerrit commit 21277f9883218c89fba15ebfbac7fcf3236fe9a8 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jan 9 22:05:18 2012 -0800 Make MTRR min hole alignment 64MB This affects the algorithm when determining when to transform a range into a larger range with a hole. It is needed when for when I switch on an 8MB TSEG and cause the memory maps to go crazy. Also add header defines for the SMRR. Change-Id: I1a06ccc28ef139cc79f655a8b19fd3533aca0401 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- src/cpu/x86/mtrr/mtrr.c | 9 ++++++--- src/include/cpu/x86/mtrr.h | 3 +++ 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 5f5e02b..ed7d93b 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -265,13 +265,16 @@ static unsigned int range_to_mtrr(unsigned int reg, return reg; } - if (above4gb == 2 && type == MTRR_TYPE_WRBACK && range_sizek % 0x4000) { +#define MIN_ALIGN 0x10000 /* 64MB */ + + if (above4gb == 2 && type == MTRR_TYPE_WRBACK && + range_sizek > MIN_ALIGN && range_sizek % MIN_ALIGN) { /* - * If this range is not divisible by 16MB then instead + * If this range is not divisible then instead * make a larger range and carve out an uncached hole. */ hole_startk = range_startk + range_sizek; - hole_sizek = 0x4000 - (range_sizek % 0x4000); + hole_sizek = MIN_ALIGN - (range_sizek % MIN_ALIGN); range_sizek += hole_sizek; } diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 62cb8b7..8b5cc28 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -17,6 +17,9 @@ #define MTRRdefTypeEn (1 << 11) #define MTRRdefTypeFixEn (1 << 10) +#define SMRRphysBase_MSR 0x1f2 +#define SMRRphysMask_MSR 0x1f3 + #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg)) #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)

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Patch set updated for coreboot: a3b2c44 Prepare the BIOS data areas before device init.
by Stefan Reinauer 30 Mar '12

30 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/769 -gerrit commit a3b2c440baca27f9275b2e4bb7cb591c565fc08d Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jan 17 09:03:11 2012 -0800 Prepare the BIOS data areas before device init. Since we do not run option roms in normal mode nothing was initializing the BDA/EBDA and yet Linux depends very much on it having sane values here. For the most part the kernel tries to work around this not being initialized, but every once in awhile (1/300 boots or so) it would end up reading something that looked sane from BDA but was not and then it would panic. In this change the EBDA is unconditionally setup before devices are initialized. I'm not set on the location in dev_initialize() but there does not seem to be another place to hook it in so that it runs just once for ALL platforms regardless of whether they use option roms or not. (possibly hardwaremain?) The EBDA setup code has been moved into its own location in arch/x86/lib/ebda.c so it can be compiled in even if the option rom code is not. The low memory size is still set to 1MB which is enough to make linux happy without having to hook into each mainboard to get a more appropriate value. The setup_ebda() function takes inputs so it could be changed for a mainboard if needed. OLD/BROKEN would read garbage. Examples from different boots: ebda_addr=0x75e80 lowmem=0x1553400 ebda_addr=0x5e080 lowmem=0x3e51400 ebda_addr=0x7aa80 lowmem=0x2f8a800 NEW/FIXED now reads consistent values: ebda_addr=0xf6000 lowmem=0x100000 Change-Id: I6cb79f0e3e43cc65f7e5fe98b6cad1a557ccd949 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- src/arch/x86/include/arch/ebda.h | 37 +++++++++++++++++++++++++++++ src/arch/x86/lib/Makefile.inc | 1 + src/arch/x86/lib/ebda.c | 48 ++++++++++++++++++++++++++++++++++++++ src/devices/device.c | 8 ++++++ src/devices/oprom/x86.c | 16 ------------ 5 files changed, 94 insertions(+), 16 deletions(-) diff --git a/src/arch/x86/include/arch/ebda.h b/src/arch/x86/include/arch/ebda.h new file mode 100644 index 0000000..1de6097 --- /dev/null +++ b/src/arch/x86/include/arch/ebda.h @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __ARCH_EBDA_H +#define __ARCH_EBDA_H + +#define X86_BDA_SIZE 0x200 +#define X86_BDA_BASE 0x400 +#define X86_EBDA_SEGMENT 0x40e +#define X86_EBDA_LOWMEM 0x413 + +#define DEFAULT_EBDA_LOWMEM (1024 << 10) +#define DEFAULT_EBDA_SEGMENT 0xF600 +#define DEFAULT_EBDA_SIZE 0x400 + +void setup_ebda(u32 low_memory_size, u16 ebda_segment, u16 ebda_size); +void setup_default_ebda(void); + +#endif diff --git a/src/arch/x86/lib/Makefile.inc b/src/arch/x86/lib/Makefile.inc index 96fb9b0..8f5fd5f 100644 --- a/src/arch/x86/lib/Makefile.inc +++ b/src/arch/x86/lib/Makefile.inc @@ -8,6 +8,7 @@ ramstage-y += exception.c ramstage-$(CONFIG_IOAPIC) += ioapic.c ramstage-y += memset.c ramstage-y += memcpy.c +ramstage-y += ebda.c romstage-y += romstage_console.c romstage-y += cbfs_and_run.c diff --git a/src/arch/x86/lib/ebda.c b/src/arch/x86/lib/ebda.c new file mode 100644 index 0000000..faf1451 --- /dev/null +++ b/src/arch/x86/lib/ebda.c @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <stdint.h> +#include <string.h> +#include <arch/io.h> +#include <arch/ebda.h> + +void setup_ebda(u32 low_memory_size, u16 ebda_segment, u16 ebda_size) +{ + if (!low_memory_size || !ebda_segment || !ebda_size) + return; + + /* clear BIOS DATA AREA */ + memset((void *)X86_BDA_BASE, 0, X86_BDA_SIZE); + + write16(X86_EBDA_LOWMEM, (low_memory_size >> 10)); + write16(X86_EBDA_SEGMENT, ebda_segment); + + /* Set up EBDA */ + memset((void *)(ebda_segment << 4), 0, ebda_size); + write16((ebda_segment << 4), (ebda_size >> 10)); +} + +void setup_default_ebda(void) +{ + setup_ebda(DEFAULT_EBDA_LOWMEM, + DEFAULT_EBDA_SEGMENT, + DEFAULT_EBDA_SIZE); +} diff --git a/src/devices/device.c b/src/devices/device.c index 0d2bf8f..0e9c39e 100644 --- a/src/devices/device.c +++ b/src/devices/device.c @@ -41,6 +41,9 @@ #include <stdlib.h> #include <string.h> #include <smp/spinlock.h> +#if CONFIG_ARCH_X86 +#include <arch/ebda.h> +#endif /** Linked list of ALL devices */ struct device *all_devices = &dev_root; @@ -1102,6 +1105,11 @@ void dev_initialize(void) printk(BIOS_INFO, "Initializing devices...\n"); +#if CONFIG_ARCH_X86 + /* Ensure EBDA is prepared before Option ROMs. */ + setup_default_ebda(); +#endif + /* First call the mainboard init. */ init_dev(&dev_root); diff --git a/src/devices/oprom/x86.c b/src/devices/oprom/x86.c index 0c15b15..564017d 100644 --- a/src/devices/oprom/x86.c +++ b/src/devices/oprom/x86.c @@ -40,19 +40,6 @@ void (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx, u32 edx, u32 esi, u32 edi) __attribute__((regparm(0))) = (void *)&__realmode_interrupt; -static void setup_bda(void) -{ - /* clear BIOS DATA AREA */ - memset((void *)0x400, 0, 0x200); - - write16(0x413, FAKE_MEMORY_SIZE / 1024); - write16(0x40e, INITIAL_EBDA_SEGMENT); - - /* Set up EBDA */ - memset((void *)(INITIAL_EBDA_SEGMENT << 4), 0, INITIAL_EBDA_SIZE); - write16((INITIAL_EBDA_SEGMENT << 4) + 0x0, INITIAL_EBDA_SIZE / 1024); -} - static void setup_rombios(void) { const char date[] = "06/11/99"; @@ -272,9 +259,6 @@ void run_bios(struct device *dev, unsigned long addr) */ setup_i8259(); - /* Set up BIOS Data Area */ - setup_bda(); - /* Set up some legacy information in the F segment */ setup_rombios();

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Patch set updated for coreboot: 9b88d41 Make cpuid functions usable when compiled with PIC
by Stefan Reinauer 30 Mar '12

30 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/764 -gerrit commit 9b88d41751f692f28014537194087f9ac3c360f8 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jan 9 22:00:30 2012 -0800 Make cpuid functions usable when compiled with PIC This avoids using EBX and instead uses EDI where possible, and ESI when necessary to get the EBX value out. This allows me to enable -fpic for SMM TSEG code. Also add a new CPUID extended function to query with ECX set. Change-Id: I10dbded3f3ad98a39ba7b53da59af6ca3145e2e5 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- src/arch/x86/include/arch/cpu.h | 57 ++++++++++++++++++++++++++++++-------- 1 files changed, 45 insertions(+), 12 deletions(-) diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 2dfcd72..891e62b 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -36,12 +36,36 @@ static inline struct cpuid_result cpuid(int op) { struct cpuid_result result; asm volatile( - "cpuid" + "mov %%ebx, %%edi;" + "cpuid;" + "mov %%ebx, %%esi;" + "mov %%edi, %%ebx;" : "=a" (result.eax), - "=b" (result.ebx), + "=S" (result.ebx), "=c" (result.ecx), "=d" (result.edx) - : "0" (op)); + : "0" (op) + : "edi"); + return result; +} + +/* + * Generic Extended CPUID function + */ +static inline struct cpuid_result cpuid_ext(int op, unsigned ecx) +{ + struct cpuid_result result; + asm volatile( + "mov %%ebx, %%edi;" + "cpuid;" + "mov %%ebx, %%esi;" + "mov %%edi, %%ebx;" + : "=a" (result.eax), + "=S" (result.ebx), + "=c" (result.ecx), + "=d" (result.edx) + : "0" (op), "2" (ecx) + : "edi"); return result; } @@ -52,10 +76,12 @@ static inline unsigned int cpuid_eax(unsigned int op) { unsigned int eax; - __asm__("cpuid" + __asm__("mov %%ebx, %%edi;" + "cpuid;" + "mov %%edi, %%ebx;" : "=a" (eax) : "0" (op) - : "ebx", "ecx", "edx"); + : "ecx", "edx", "edi"); return eax; } @@ -63,10 +89,13 @@ static inline unsigned int cpuid_ebx(unsigned int op) { unsigned int eax, ebx; - __asm__("cpuid" - : "=a" (eax), "=b" (ebx) + __asm__("mov %%ebx, %%edi;" + "cpuid;" + "mov %%edi, %%ebx;" + "mov %%edi, %%esi;" + : "=a" (eax), "=S" (ebx) : "0" (op) - : "ecx", "edx" ); + : "ecx", "edx", "edi"); return ebx; } @@ -74,10 +103,12 @@ static inline unsigned int cpuid_ecx(unsigned int op) { unsigned int eax, ecx; - __asm__("cpuid" + __asm__("mov %%ebx, %%edi;" + "cpuid;" + "mov %%edi, %%ebx;" : "=a" (eax), "=c" (ecx) : "0" (op) - : "ebx", "edx" ); + : "edx", "edi"); return ecx; } @@ -85,10 +116,12 @@ static inline unsigned int cpuid_edx(unsigned int op) { unsigned int eax, edx; - __asm__("cpuid" + __asm__("mov %%ebx, %%edi;" + "cpuid;" + "mov %%edi, %%ebx;" : "=a" (eax), "=d" (edx) : "0" (op) - : "ebx", "ecx"); + : "ecx", "edi"); return edx; }

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Patch set updated for coreboot: 099a1d6 Add Kconfig options to enable TSEG and set a size
by Stefan Reinauer 30 Mar '12

30 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/766 -gerrit commit 099a1d65203f9e0529dcfa986639ce91ffdec05d Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jan 9 22:11:25 2012 -0800 Add Kconfig options to enable TSEG and set a size Future CPUs will require TSEG use for SMM Change-Id: I1432569ece4371d6e12c997e90d66c175fa54c5c Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- src/cpu/x86/Kconfig | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-) diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 6894622..0eaee2e 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -43,3 +43,11 @@ config LOGICAL_CPUS config CACHE_ROM bool default n + +config SMM_TSEG + bool + default n + +config SMM_TSEG_SIZE + hex + default 0

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Patch set updated for coreboot: 38173d0 Don't re-init EBDA in S3 resume path.
by Stefan Reinauer 30 Mar '12

30 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/770 -gerrit commit 38173d059962cb600361cbe48af36b11765d73c3 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Jan 18 10:05:18 2012 -0800 Don't re-init EBDA in S3 resume path. I forgot to implement this the first time around. It does not seem to cause noticeable problems but in heavy suspend/resume testing I saw a suspicious crash in the kernel when trying to bring one of the CPUs back online. Change-Id: I950ac260f251e2683693d9bd20a0dd5e041aa26e Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- src/arch/x86/lib/ebda.c | 9 +++++++++ 1 files changed, 9 insertions(+), 0 deletions(-) diff --git a/src/arch/x86/lib/ebda.c b/src/arch/x86/lib/ebda.c index faf1451..fb407b6 100644 --- a/src/arch/x86/lib/ebda.c +++ b/src/arch/x86/lib/ebda.c @@ -23,9 +23,18 @@ #include <string.h> #include <arch/io.h> #include <arch/ebda.h> +#if CONFIG_HAVE_ACPI_RESUME +#include <arch/acpi.h> +#endif void setup_ebda(u32 low_memory_size, u16 ebda_segment, u16 ebda_size) { +#if CONFIG_HAVE_ACPI_RESUME + /* Skip in S3 resume path */ + if (acpi_slp_type == 3) + return; +#endif + if (!low_memory_size || !ebda_segment || !ebda_size) return;

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Patch set updated for coreboot: ea52a94 MTRR: add alternate allocation method for odd memory maps
by Stefan Reinauer 30 Mar '12

30 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/761 -gerrit commit ea52a9429656c8b5004da212f4c2cc1fcfb52db9 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Dec 22 10:59:40 2011 -0800 MTRR: add alternate allocation method for odd memory maps With >= 4GB memory installed we get a memory map split in the middle due to remap that has boundaries that are inconveniently aligned for MTRRs due to the various UMA regions. 0000MB-2780MB 2780MB RAM (writeback) 2780MB-2782MB 2MB TSEG (uncached/SMRR) 2782MB-2784MB 2MB GFX GTT (uncached) 2784MB-2816MB 32MB GFX UMA (uncached) 2816MB-4096MB 1280MB EMPTY (N/A) 4096MB-5368MB 1272MB RAM (writeback) 5368MB-5376MB 8MB ME UMA (uncached) The default MTRR allocation method of trying to cover everything with one MTRR and then carve out a single uncached region does not work for the GPU aperture which needs write-combining type, and it also has issues trying to cover the uneven boundaries in the avaiable variable MTRRs. My goal was to make a minimal set of changes and avoid modifying behavior on existing systems with an algorithm that is not always optimal for a typical memory layout. So the flag 'above4gb=2' will change these allocation behaviors: 1) Detect the number of available variable MTRRs rather than limiting to hardcoded value. We need every last MTRR. 2) Don't try to cover all RAM with one MTRR, instead let each RAM region get covered independently. 3) Don't assume uma_memory_base is part of the last region and increase the size of that region. In this case the UMA region is carved out from the lower memory region and it is already declared as part of the ram region. 4) If a memory region can't be covered with MTRRs >= 16MB then instead make a larger region and trim it with uncached MTRRs. Change-Id: I5a60a44ab6d3ae2f46ea6ffa9e3677aaad2485eb Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- src/cpu/x86/mtrr/mtrr.c | 52 ++++++++++++++++++++++++++++++++++++++++------ 1 files changed, 45 insertions(+), 7 deletions(-) diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 9015ad4..8dccfef 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -179,6 +179,18 @@ static inline unsigned int fls(unsigned int x) #endif #define MTRRS (BIOS_MTRRS + OS_MTRRS) +static int total_mtrrs = MTRRS; +static int bios_mtrrs = BIOS_MTRRS; + +static void detect_var_mtrrs(void) +{ + msr_t msr; + + msr = rdmsr(MTRRcap_MSR); + + total_mtrrs = msr.lo & 0xff; + bios_mtrrs = total_mtrrs - 2; +} static void set_fixed_mtrrs(unsigned int first, unsigned int last, unsigned char type) { @@ -235,6 +247,8 @@ static unsigned int range_to_mtrr(unsigned int reg, unsigned long next_range_startk, unsigned char type, unsigned int address_bits, unsigned int above4gb) { + unsigned long hole_startk = 0, hole_sizek = 0; + if (!range_sizek) { /* If there's no MTRR hole, this function will bail out * here when called for the hole. @@ -243,7 +257,7 @@ static unsigned int range_to_mtrr(unsigned int reg, return reg; } - if (reg >= BIOS_MTRRS) { + if (reg >= bios_mtrrs) { printk(BIOS_ERR, "Warning: Out of MTRRs for base: %4ldMB, range: %ldMB, type %s\n", range_startk >>10, range_sizek >> 10, (type==MTRR_TYPE_UNCACHEABLE)?"UC": @@ -251,6 +265,16 @@ static unsigned int range_to_mtrr(unsigned int reg, return reg; } + if (above4gb == 2 && type == MTRR_TYPE_WRBACK && range_sizek % 0x4000) { + /* + * If this range is not divisible by 16MB then instead + * make a larger range and carve out an uncached hole. + */ + hole_startk = range_startk + range_sizek; + hole_sizek = 0x4000 - (range_sizek % 0x4000); + range_sizek += hole_sizek; + } + while(range_sizek) { unsigned long max_align, align; unsigned long sizek; @@ -274,11 +298,20 @@ static unsigned int range_to_mtrr(unsigned int reg, set_var_mtrr(reg++, range_startk, sizek, type, address_bits); range_startk += sizek; range_sizek -= sizek; - if (reg >= BIOS_MTRRS) { + if (reg >= bios_mtrrs) { printk(BIOS_ERR, "Running out of variable MTRRs!\n"); break; } } + + if (hole_sizek) { + printk(BIOS_DEBUG, "Adding hole at %ldMB-%ldMB\n", + hole_startk, hole_startk + hole_sizek); + reg = range_to_mtrr(reg, hole_startk, hole_sizek, + next_range_startk, MTRR_TYPE_UNCACHEABLE, + address_bits, above4gb); + } + return reg; } @@ -325,7 +358,7 @@ void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res) { struct var_mtrr_state *state = gp; unsigned long basek, sizek; - if (state->reg >= BIOS_MTRRS) + if (state->reg >= bios_mtrrs) return; basek = resk(res->base); sizek = resk(res->size); @@ -341,7 +374,7 @@ void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res) /* Write the range mtrrs */ if (state->range_sizek != 0) { #if CONFIG_VAR_MTRR_HOLE - if (state->hole_sizek == 0) { + if (state->hole_sizek == 0 && state->above4gb != 2) { /* We need to put that on to hole */ unsigned long endk = basek + sizek; state->hole_startk = state->range_startk + state->range_sizek; @@ -424,6 +457,10 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb) var_state.address_bits = address_bits; var_state.above4gb = above4gb; + /* Detect number of variable MTRRs */ + if (above4gb == 2) + detect_var_mtrrs(); + search_global_resources( IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE, set_var_mtrr_resource, &var_state); @@ -435,7 +472,8 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb) } else { #if CONFIG_VAR_MTRR_HOLE // Increase the base range and set up UMA as an UC hole instead - var_state.range_sizek += (uma_memory_size >> 10); + if (above4gb != 2) + var_state.range_sizek += (uma_memory_size >> 10); var_state.hole_startk = (uma_memory_base >> 10); var_state.hole_sizek = (uma_memory_size >> 10); @@ -454,7 +492,7 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb) printk(BIOS_DEBUG, "DONE variable MTRRs\n"); printk(BIOS_DEBUG, "Clear out the extra MTRR's\n"); /* Clear out the extra MTRR's */ - while(var_state.reg < MTRRS) { + while(var_state.reg < total_mtrrs) { set_var_mtrr(var_state.reg++, 0, 0, 0, var_state.address_bits); } @@ -463,7 +501,7 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb) * complete ROM now that we actually have RAM. */ if (boot_cpu() && (acpi_slp_type != 3)) { - set_var_mtrr(7, (4096-4)*1024, 4*1024, + set_var_mtrr(total_mtrrs-1, (4096-4)*1024, 4*1024, MTRR_TYPE_WRPROT, address_bits); } #endif

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Patch set updated for coreboot: ddd6a46 drop use of MAX_PHYSICAL_CPUS and MAX_CPUS where not needed
by Stefan Reinauer 30 Mar '12

30 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/760 -gerrit commit ddd6a46ad0feaf622cfa8db898961aa3c011d7af Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Dec 15 09:24:40 2011 -0800 drop use of MAX_PHYSICAL_CPUS and MAX_CPUS where not needed Change-Id: Idf875ddec417e627f1e72a6d834860e7fd324a50 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/cpu/x86/lapic/lapic_cpu_init.c | 6 ------ src/cpu/x86/pae/Makefile.inc | 2 +- 2 files changed, 1 insertions(+), 7 deletions(-) diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 2e2bb06..ed9940c 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -384,9 +384,7 @@ void secondary_cpu_init(void) { atomic_inc(&active_cpus); #if CONFIG_SERIAL_CPU_INIT == 1 - #if CONFIG_MAX_CPUS>2 spin_lock(&start_cpu_lock); - #endif #endif #ifdef __SSE3__ @@ -401,9 +399,7 @@ void secondary_cpu_init(void) #endif cpu_initialize(); #if CONFIG_SERIAL_CPU_INIT == 1 - #if CONFIG_MAX_CPUS>2 spin_unlock(&start_cpu_lock); - #endif #endif atomic_dec(&active_cpus); @@ -440,9 +436,7 @@ static void start_other_cpus(struct bus *cpu_bus, device_t bsp_cpu) cpu->path.apic.apic_id); } #if CONFIG_SERIAL_CPU_INIT == 1 - #if CONFIG_MAX_CPUS>2 udelay(10); - #endif #endif } diff --git a/src/cpu/x86/pae/Makefile.inc b/src/cpu/x86/pae/Makefile.inc index 0ecec47..060720c 100644 --- a/src/cpu/x86/pae/Makefile.inc +++ b/src/cpu/x86/pae/Makefile.inc @@ -1 +1 @@ -ramstage-y += pgtbl.c +ramstage-$(CONFIG_CPU_AMD_MODEL_FXX) += pgtbl.c

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Patch set updated for coreboot: a1501a2 Fix MB calculation in the reporting of the MTRR hole
by Stefan Reinauer 30 Mar '12

30 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/763 -gerrit commit a1501a284204666eeaa0e2ffca6acacffb233131 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Jan 6 15:49:30 2012 -0800 Fix MB calculation in the reporting of the MTRR hole Change-Id: I34b5c4ffd2a3f3e895d2bffedce1c00ee9aea942 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- src/cpu/x86/mtrr/mtrr.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 8dccfef..5f5e02b 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -306,7 +306,7 @@ static unsigned int range_to_mtrr(unsigned int reg, if (hole_sizek) { printk(BIOS_DEBUG, "Adding hole at %ldMB-%ldMB\n", - hole_startk, hole_startk + hole_sizek); + hole_startk >> 10, (hole_startk + hole_sizek) >> 10); reg = range_to_mtrr(reg, hole_startk, hole_sizek, next_range_startk, MTRR_TYPE_UNCACHEABLE, address_bits, above4gb);

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coreboot March 2012