coreboot March 2012

coreboot@coreboot.org

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Patch merged into coreboot/master: f7d1a96 use movsl for copying resume memory back
by gerrit＠coreboot.org 30 Mar '12

30 Mar '12

the following patch was just integrated into master: commit f7d1a9683d8874c7c6dd3fc6dc763f594d285575 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Nov 17 13:03:38 2011 -0800 use movsl for copying resume memory back It's not significantly faster, but easier to read and smaller. Change-Id: Ibab0b478873912d67bf1f07743f628586353368a Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Fri Mar 30 13:00:03 2012, giving +1 See http://review.coreboot.org/755 for details. -gerrit

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Patch merged into coreboot/master: 799359a Don't unconditionally add support for cardbus and pci-x devices
by gerrit＠coreboot.org 30 Mar '12

30 Mar '12

the following patch was just integrated into master: commit 799359ade73a97a6aa84612b54da3e927f6f6bd7 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Nov 30 12:45:14 2011 -0800 Don't unconditionally add support for cardbus and pci-x devices It's still on by default. Change-Id: I8b6539eaf2f8d6a4fa975deb14789a00f2090d34 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Fri Mar 30 13:57:08 2012, giving +1 See http://review.coreboot.org/756 for details. -gerrit

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Patch merged into coreboot/master: 5d295e5 Add DEBUG_TPM option to Debugging menu
by gerrit＠coreboot.org 30 Mar '12

30 Mar '12

the following patch was just integrated into master: commit 5d295e5cefc3e0650447e8d7fc80eeb12f434aa1 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Nov 17 12:50:54 2011 -0800 Add DEBUG_TPM option to Debugging menu instead of having to edit the source code of tpm.c Change-Id: I519d9ada14dd383e668a2da4219e5373a24c7c3d Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Fri Mar 30 14:13:50 2012, giving +1 See http://review.coreboot.org/757 for details. -gerrit

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Patch merged into coreboot/master: 21277f9 Make MTRR min hole alignment 64MB
by gerrit＠coreboot.org 30 Mar '12

30 Mar '12

the following patch was just integrated into master: commit 21277f9883218c89fba15ebfbac7fcf3236fe9a8 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jan 9 22:05:18 2012 -0800 Make MTRR min hole alignment 64MB This affects the algorithm when determining when to transform a range into a larger range with a hole. It is needed when for when I switch on an 8MB TSEG and cause the memory maps to go crazy. Also add header defines for the SMRR. Change-Id: I1a06ccc28ef139cc79f655a8b19fd3533aca0401 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Build-Tested: build bot (Jenkins) at Fri Mar 30 12:41:09 2012, giving +1 See http://review.coreboot.org/765 for details. -gerrit

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Patch merged into coreboot/master: a1501a2 Fix MB calculation in the reporting of the MTRR hole
by gerrit＠coreboot.org 30 Mar '12

30 Mar '12

the following patch was just integrated into master: commit a1501a284204666eeaa0e2ffca6acacffb233131 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Jan 6 15:49:30 2012 -0800 Fix MB calculation in the reporting of the MTRR hole Change-Id: I34b5c4ffd2a3f3e895d2bffedce1c00ee9aea942 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Build-Tested: build bot (Jenkins) at Fri Mar 30 10:57:02 2012, giving +1 See http://review.coreboot.org/763 for details. -gerrit

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Patch merged into coreboot/master: ea52a94 MTRR: add alternate allocation method for odd memory maps
by gerrit＠coreboot.org 30 Mar '12

30 Mar '12

the following patch was just integrated into master: commit ea52a9429656c8b5004da212f4c2cc1fcfb52db9 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Dec 22 10:59:40 2011 -0800 MTRR: add alternate allocation method for odd memory maps With >= 4GB memory installed we get a memory map split in the middle due to remap that has boundaries that are inconveniently aligned for MTRRs due to the various UMA regions. 0000MB-2780MB 2780MB RAM (writeback) 2780MB-2782MB 2MB TSEG (uncached/SMRR) 2782MB-2784MB 2MB GFX GTT (uncached) 2784MB-2816MB 32MB GFX UMA (uncached) 2816MB-4096MB 1280MB EMPTY (N/A) 4096MB-5368MB 1272MB RAM (writeback) 5368MB-5376MB 8MB ME UMA (uncached) The default MTRR allocation method of trying to cover everything with one MTRR and then carve out a single uncached region does not work for the GPU aperture which needs write-combining type, and it also has issues trying to cover the uneven boundaries in the avaiable variable MTRRs. My goal was to make a minimal set of changes and avoid modifying behavior on existing systems with an algorithm that is not always optimal for a typical memory layout. So the flag 'above4gb=2' will change these allocation behaviors: 1) Detect the number of available variable MTRRs rather than limiting to hardcoded value. We need every last MTRR. 2) Don't try to cover all RAM with one MTRR, instead let each RAM region get covered independently. 3) Don't assume uma_memory_base is part of the last region and increase the size of that region. In this case the UMA region is carved out from the lower memory region and it is already declared as part of the ram region. 4) If a memory region can't be covered with MTRRs >= 16MB then instead make a larger region and trim it with uncached MTRRs. Change-Id: I5a60a44ab6d3ae2f46ea6ffa9e3677aaad2485eb Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Build-Tested: build bot (Jenkins) at Fri Mar 30 11:22:00 2012, giving +1 See http://review.coreboot.org/761 for details. -gerrit

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Patch merged into coreboot/master: 38173d0 Don't re-init EBDA in S3 resume path.
by gerrit＠coreboot.org 30 Mar '12

30 Mar '12

the following patch was just integrated into master: commit 38173d059962cb600361cbe48af36b11765d73c3 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Jan 18 10:05:18 2012 -0800 Don't re-init EBDA in S3 resume path. I forgot to implement this the first time around. It does not seem to cause noticeable problems but in heavy suspend/resume testing I saw a suspicious crash in the kernel when trying to bring one of the CPUs back online. Change-Id: I950ac260f251e2683693d9bd20a0dd5e041aa26e Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Build-Tested: build bot (Jenkins) at Fri Mar 30 11:42:25 2012, giving +1 See http://review.coreboot.org/770 for details. -gerrit

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Patch merged into coreboot/master: a3b2c44 Prepare the BIOS data areas before device init.
by gerrit＠coreboot.org 30 Mar '12

30 Mar '12

the following patch was just integrated into master: commit a3b2c440baca27f9275b2e4bb7cb591c565fc08d Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jan 17 09:03:11 2012 -0800 Prepare the BIOS data areas before device init. Since we do not run option roms in normal mode nothing was initializing the BDA/EBDA and yet Linux depends very much on it having sane values here. For the most part the kernel tries to work around this not being initialized, but every once in awhile (1/300 boots or so) it would end up reading something that looked sane from BDA but was not and then it would panic. In this change the EBDA is unconditionally setup before devices are initialized. I'm not set on the location in dev_initialize() but there does not seem to be another place to hook it in so that it runs just once for ALL platforms regardless of whether they use option roms or not. (possibly hardwaremain?) The EBDA setup code has been moved into its own location in arch/x86/lib/ebda.c so it can be compiled in even if the option rom code is not. The low memory size is still set to 1MB which is enough to make linux happy without having to hook into each mainboard to get a more appropriate value. The setup_ebda() function takes inputs so it could be changed for a mainboard if needed. OLD/BROKEN would read garbage. Examples from different boots: ebda_addr=0x75e80 lowmem=0x1553400 ebda_addr=0x5e080 lowmem=0x3e51400 ebda_addr=0x7aa80 lowmem=0x2f8a800 NEW/FIXED now reads consistent values: ebda_addr=0xf6000 lowmem=0x100000 Change-Id: I6cb79f0e3e43cc65f7e5fe98b6cad1a557ccd949 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Build-Tested: build bot (Jenkins) at Fri Mar 30 12:26:50 2012, giving +1 See http://review.coreboot.org/769 for details. -gerrit

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Patch merged into coreboot/master: 23efb07 vga_io.c is not needed unless CONFIG_VGA is set
by gerrit＠coreboot.org 30 Mar '12

30 Mar '12

the following patch was just integrated into master: commit 23efb0706a5016f07eaa6d67c85a3409aa127edd Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Nov 17 11:13:36 2011 -0800 vga_io.c is not needed unless CONFIG_VGA is set hence disable it. Change-Id: I7b406251a2f3830748140a111f76f2792fe923ed Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Fri Mar 30 13:27:30 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Mar 30 17:49:34 2012, giving +2 See http://review.coreboot.org/753 for details. -gerrit

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Patch merged into coreboot/master: 1fdce7a Allow components smaller than declared size.
by gerrit＠coreboot.org 30 Mar '12

30 Mar '12

the following patch was just integrated into master: commit 1fdce7acdd2228ac20b57c24e2ca8a1f434a1474 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Wed Nov 9 14:11:26 2011 -0800 Allow components smaller than declared size. idftool was failing to add the ME blobs into the output image in case the blob size does not exactly match the size allocated for it in the flashrom structure. It is difficult to set the field in the structure to exactly match the size (for some reason Intel flash tool fails to insert the correct size even when given the exact ME blob). On the other hand there is no harm in using am ME blob smaller than the allocated size, this change modifies the tool building the image to allow for smaller components. Change-Id: I1b04f90051b91157391943c9bad0eb06dd297431 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Build-Tested: build bot (Jenkins) at Fri Mar 30 10:15:52 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Mar 30 17:48:44 2012, giving +2 See http://review.coreboot.org/751 for details. -gerrit

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coreboot March 2012