March 2012 - coreboot - mail.coreboot.org

Patch merged into coreboot/master: 099a1d6 Add Kconfig options to enable TSEG and set a size
by gerrit＠coreboot.org March 30, 2012

March 30, 2012

the following patch was just integrated into master: commit 099a1d65203f9e0529dcfa986639ce91ffdec05d Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jan 9 22:11:25 2012 -0800 Add Kconfig options to enable TSEG and set a size Future CPUs will require TSEG use for SMM Change-Id: I1432569ece4371d6e12c997e90d66c175fa54c5c Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Build-Tested: build bot (Jenkins) at Fri Mar 30 11:55:36 2012, giving +1 See http://review.coreboot.org/766 for details. -gerrit

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Patch merged into coreboot/master: 9b88d41 Make cpuid functions usable when compiled with PIC
by gerrit＠coreboot.org March 30, 2012

March 30, 2012

the following patch was just integrated into master: commit 9b88d41751f692f28014537194087f9ac3c360f8 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jan 9 22:00:30 2012 -0800 Make cpuid functions usable when compiled with PIC This avoids using EBX and instead uses EDI where possible, and ESI when necessary to get the EBX value out. This allows me to enable -fpic for SMM TSEG code. Also add a new CPUID extended function to query with ECX set. Change-Id: I10dbded3f3ad98a39ba7b53da59af6ca3145e2e5 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Build-Tested: build bot (Jenkins) at Fri Mar 30 12:11:24 2012, giving +1 See http://review.coreboot.org/764 for details. -gerrit

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Patch merged into coreboot/master: 8d33657 Revamp cbmem.py to use the coreboot tables.
by gerrit＠coreboot.org March 30, 2012

March 30, 2012

the following patch was just integrated into master: commit 8d336571c89034327cac5bae2c2b9242165e0f48 Author: Gabe Black <gabeblack(a)google.com> Date: Sat Jan 7 01:03:42 2012 -0800 Revamp cbmem.py to use the coreboot tables. This change makes significant changes to cbmem.py to make it use the coreboot tables to find the memory console and timestamp areas instead of looking for the in memory table TOC structure. That appears to be more robust and gets cbmem.py working again after some unrelated changes that affected memory layout. It also introduces some small infrastructure to make accessing C style structures in physical memory easier and more transparent. Change-Id: I51833055a50c2d76423520ba6e059bf8fc50adea Signed-off-by: Gabe Black <gabeblack(a)google.com> Build-Tested: build bot (Jenkins) at Fri Mar 30 10:44:44 2012, giving +1 See http://review.coreboot.org/762 for details. -gerrit

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Patch merged into coreboot/master: ddd6a46 drop use of MAX_PHYSICAL_CPUS and MAX_CPUS where not needed
by gerrit＠coreboot.org March 30, 2012

March 30, 2012

the following patch was just integrated into master: commit ddd6a46ad0feaf622cfa8db898961aa3c011d7af Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Dec 15 09:24:40 2011 -0800 drop use of MAX_PHYSICAL_CPUS and MAX_CPUS where not needed Change-Id: Idf875ddec417e627f1e72a6d834860e7fd324a50 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Fri Mar 30 11:09:53 2012, giving +1 See http://review.coreboot.org/760 for details. -gerrit

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Patch merged into coreboot/master: 6ce4867 Make PCI CONF2 support a compile time option
by gerrit＠coreboot.org March 30, 2012

March 30, 2012

the following patch was just integrated into master: commit 6ce4867bb32b6d1471cad36f8777b817efd5a606 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Nov 17 13:05:31 2011 -0800 Make PCI CONF2 support a compile time option It's not used on any board supported by coreboot but has been detected at run time since ages. No new boards (since 2000?) are using the CONF2 method, so it is unlikely we ever have to turn this on for a board. Change-Id: I17df94a8a77b9338fde10a6b114b44d393776e66 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Fri Mar 30 13:43:19 2012, giving +1 See http://review.coreboot.org/758 for details. -gerrit

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Patch merged into coreboot/master: c2d6e3a Add more timestamps in coreboot.
by gerrit＠coreboot.org March 30, 2012

March 30, 2012

the following patch was just integrated into master: commit c2d6e3adae4e292c4ffc8fbcdb0fe5a5505ebac8 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Nov 4 12:31:58 2011 -0700 Add more timestamps in coreboot. This adds a number of timestamps in ramstage and romstage so we can figure out where execution time goes. Change-Id: Iea17c08774e623fc1ca3fa4505b70523ba4cbf01 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Fri Mar 30 10:27:41 2012, giving +1 See http://review.coreboot.org/749 for details. -gerrit

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Patch set updated for coreboot: 5d295e5 Add DEBUG_TPM option to Debugging menu
by Stefan Reinauer March 30, 2012

March 30, 2012

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/757 -gerrit commit 5d295e5cefc3e0650447e8d7fc80eeb12f434aa1 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Nov 17 12:50:54 2011 -0800 Add DEBUG_TPM option to Debugging menu instead of having to edit the source code of tpm.c Change-Id: I519d9ada14dd383e668a2da4219e5373a24c7c3d Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/Kconfig | 7 +++++++ src/pc80/tpm.c | 9 +-------- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index f7180a9..0696feb 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -862,6 +862,13 @@ config X86EMU_DEBUG_IO If unsure, say N. +config DEBUG_TPM + bool "Output verbose TPM debug messages" + default n + depends on TPM + help + This option enables additional TPM related debug messages. + config LLSHELL bool "Built-in low-level shell" default n diff --git a/src/pc80/tpm.c b/src/pc80/tpm.c index 8e94303..17e1ed7 100644 --- a/src/pc80/tpm.c +++ b/src/pc80/tpm.c @@ -27,7 +27,6 @@ * Infineon slb9635), so this driver provides access to locality 0 only. */ -/* #define DEBUG */ #include <stdlib.h> #include <string.h> #include <delay.h> @@ -37,17 +36,11 @@ #include <pc80/tpm.h> #include <cpu/x86/car.h> -#ifdef DEBUG -#define TPM_DEBUG_ON 1 -#else -#define TPM_DEBUG_ON 0 -#endif - #define PREFIX "lpc_tpm: " /* coreboot wrapper for TPM driver (start) */ #define TPM_DEBUG(fmt, args...) \ - if (TPM_DEBUG_ON) { \ + if (CONFIG_DEBUG_TPM) { \ printk(BIOS_DEBUG, PREFIX); \ printk(BIOS_DEBUG, fmt , ##args); \ }

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Patch set updated for coreboot: 799359a Don't unconditionally add support for cardbus and pci-x devices
by Stefan Reinauer March 30, 2012

March 30, 2012

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/756 -gerrit commit 799359ade73a97a6aa84612b54da3e927f6f6bd7 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Nov 30 12:45:14 2011 -0800 Don't unconditionally add support for cardbus and pci-x devices It's still on by default. Change-Id: I8b6539eaf2f8d6a4fa975deb14789a00f2090d34 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/devices/Makefile.inc | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/devices/Makefile.inc b/src/devices/Makefile.inc index 86b4d21..9ffc0bb 100644 --- a/src/devices/Makefile.inc +++ b/src/devices/Makefile.inc @@ -3,10 +3,10 @@ ramstage-y += root_device.c ramstage-y += device_util.c ramstage-y += pci_device.c ramstage-$(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT) += hypertransport.c -ramstage-y += pcix_device.c +ramstage-$(CONFIG_PCIX_PLUGIN_SUPPORT) += pcix_device.c ramstage-y += pciexp_device.c -ramstage-y += agp_device.c -ramstage-y += cardbus_device.c +ramstage-$(CONFIG_AGP_PLUGIN_SUPPORT) += agp_device.c +ramstage-$(CONFIG_CARDBUS_PLUGIN_SUPPORT) += cardbus_device.c ramstage-y += pnp_device.c ramstage-y += pci_ops.c ramstage-y += smbus_ops.c

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Patch set updated for coreboot: 6ce4867 Make PCI CONF2 support a compile time option
by Stefan Reinauer March 30, 2012

March 30, 2012

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/758 -gerrit commit 6ce4867bb32b6d1471cad36f8777b817efd5a606 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Nov 17 13:05:31 2011 -0800 Make PCI CONF2 support a compile time option It's not used on any board supported by coreboot but has been detected at run time since ages. No new boards (since 2000?) are using the CONF2 method, so it is unlikely we ever have to turn this on for a board. Change-Id: I17df94a8a77b9338fde10a6b114b44d393776e66 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/x86/Kconfig | 4 ++++ src/arch/x86/lib/Makefile.inc | 4 +--- src/arch/x86/lib/pci_ops_auto.c | 9 ++++++++- 3 files changed, 13 insertions(+), 4 deletions(-) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 4ca49cb..f49d09b 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -100,4 +100,8 @@ config IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS bool default n +config PCI_CONF2 + bool + default n + endmenu diff --git a/src/arch/x86/lib/Makefile.inc b/src/arch/x86/lib/Makefile.inc index 3f4dc95..96fb9b0 100644 --- a/src/arch/x86/lib/Makefile.inc +++ b/src/arch/x86/lib/Makefile.inc @@ -1,10 +1,8 @@ ramstage-y += c_start.S ramstage-y += cpu.c ramstage-y += pci_ops_conf1.c -ramstage-y += pci_ops_conf2.c - +ramstage-$(CONFIG_PCI_CONF2) += pci_ops_conf2.c ramstage-$(CONFIG_MMCONF_SUPPORT) += pci_ops_mmconf.c - ramstage-y += pci_ops_auto.c ramstage-y += exception.c ramstage-$(CONFIG_IOAPIC) += ioapic.c diff --git a/src/arch/x86/lib/pci_ops_auto.c b/src/arch/x86/lib/pci_ops_auto.c index 92eedd3..58e098b 100644 --- a/src/arch/x86/lib/pci_ops_auto.c +++ b/src/arch/x86/lib/pci_ops_auto.c @@ -6,6 +6,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> +#if CONFIG_PCI_CONF2 /* * Before we decide to use direct hardware access mechanisms, we try to do some * trivial checks to ensure it at least _seems_ to be working -- we just test @@ -41,7 +42,7 @@ static int pci_sanity_check(const struct pci_bus_operations *o) return 0; } -struct pci_bus_operations *pci_bus_fallback_ops = NULL; +static struct pci_bus_operations *pci_bus_fallback_ops = NULL; static const struct pci_bus_operations *pci_check_direct(void) { @@ -89,6 +90,12 @@ const struct pci_bus_operations *pci_remember_direct(void) pci_bus_fallback_ops = (struct pci_bus_operations *)pci_check_direct(); return pci_bus_fallback_ops; } +#else +const struct pci_bus_operations *pci_remember_direct(void) +{ + return &pci_cf8_conf1; +} +#endif /** Set the method to be used for PCI, type I or type II */

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Patch set updated for coreboot: 23efb07 vga_io.c is not needed unless CONFIG_VGA is set
by Stefan Reinauer March 30, 2012

March 30, 2012

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/753 -gerrit commit 23efb0706a5016f07eaa6d67c85a3409aa127edd Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Nov 17 11:13:36 2011 -0800 vga_io.c is not needed unless CONFIG_VGA is set hence disable it. Change-Id: I7b406251a2f3830748140a111f76f2792fe923ed Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/pc80/vga/Makefile.inc | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/pc80/vga/Makefile.inc b/src/pc80/vga/Makefile.inc index 0ca7896..d4b726a 100644 --- a/src/pc80/vga/Makefile.inc +++ b/src/pc80/vga/Makefile.inc @@ -1,4 +1,4 @@ -ramstage-y += vga_io.c +ramstage-$(CONFIG_VGA) += vga_io.c ramstage-$(CONFIG_VGA) += vga_palette.c ramstage-$(CONFIG_VGA) += vga_font_8x16.c ramstage-$(CONFIG_VGA) += vga.c

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