coreboot March 2012

coreboot@coreboot.org

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Patch set updated for coreboot: 5a56dc0 Add a helper function to determine the number of enabled CPUs
by Stefan Reinauer 31 Mar '12

31 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/821 -gerrit commit 5a56dc038f16242e624c493bffeb0d9b38b85cad Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Mar 30 13:52:58 2012 -0700 Add a helper function to determine the number of enabled CPUs Change-Id: Ia72926002571e0f250849fa5db048bd8b2e92400 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- src/devices/device_util.c | 18 ++++++++++++++++++ src/include/device/device.h | 1 + 2 files changed, 19 insertions(+), 0 deletions(-) diff --git a/src/devices/device_util.c b/src/devices/device_util.c index 526490a..5225938 100644 --- a/src/devices/device_util.c +++ b/src/devices/device_util.c @@ -850,3 +850,21 @@ u32 find_pci_tolm(struct bus *bus) return tolm; } + +/* Count of enabled CPUs */ +int dev_count_cpu(void) +{ + device_t cpu; + int count = 0; + + for (cpu = all_devices; cpu; cpu = cpu->next) { + if ((cpu->path.type != DEVICE_PATH_APIC) || + (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) + continue; + if (!cpu->enabled) + continue; + count++; + } + + return count; +} diff --git a/src/include/device/device.h b/src/include/device/device.h index c097f57..0aea1d6 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -133,6 +133,7 @@ device_t dev_find_class (unsigned int class, device_t from); device_t dev_find_slot (unsigned int bus, unsigned int devfn); device_t dev_find_slot_on_smbus (unsigned int bus, unsigned int addr); device_t dev_find_lapic(unsigned apic_id); +int dev_count_cpu(void); /* Debug functions */ void print_resource_tree(struct device * root, int debug_level,

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New patch to review for coreboot: c876459 [ChromeOS] Don't initialize VGA Option ROM in normal mode
by Stefan Reinauer 31 Mar '12

31 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/829 -gerrit commit c8764595acb4eca89ce7e6d2dabf7c6e8eac7704 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Mar 30 17:10:49 2012 -0700 [ChromeOS] Don't initialize VGA Option ROM in normal mode ChromeOS features two different modes: normal mode and developer mode (aka jailbreak mode). In developer mode, we need to display a warning screen for security reasons. However, in normal mode we want to boot blazingly fast. Therefore we don't run (VGA) option ROMs, unless we have to print something on the screen before the kernel is loaded. Change-Id: I37f63d0b082a48e037e65bde2b380f9b8743ed29 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/devices/pci_device.c | 12 ++++++++++++ 1 files changed, 12 insertions(+), 0 deletions(-) diff --git a/src/devices/pci_device.c b/src/devices/pci_device.c index 0a870b8..c055995 100644 --- a/src/devices/pci_device.c +++ b/src/devices/pci_device.c @@ -54,6 +54,9 @@ #if CONFIG_HAVE_ACPI_RESUME && !CONFIG_S3_VGA_ROM_RUN #include <arch/acpi.h> #endif +#if CONFIG_CHROMEOS +#include <vendorcode/google/chromeos/chromeos.h> +#endif u8 pci_moving_config8(struct device *dev, unsigned int reg) { @@ -667,6 +670,15 @@ void pci_dev_init(struct device *dev) ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA)) return; +#if CONFIG_CHROMEOS + /* In ChromeOS we want to boot blazingly fast. Therefore + * we don't run (VGA) option ROMs, unless we have to print + * something on the screen before the kernel is loaded. + */ + if (!developer_mode_enabled() && !recovery_mode_enabled()) + return; +#endif + rom = pci_rom_probe(dev); if (rom == NULL) return;

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New patch to review for coreboot: fe54f4a Add EC component for SMSC MEC1308/1310
by Stefan Reinauer 31 Mar '12

31 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/828 -gerrit commit fe54f4a827ed92e40946633a217d0ad97055187e Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Mar 30 17:06:43 2012 -0700 Add EC component for SMSC MEC1308/1310 Change-Id: I92109fb633a1a3090b4b1767dd119b8c8a1b5f81 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/ec/Kconfig | 1 + src/ec/Makefile.inc | 2 +- src/ec/smsc/Kconfig | 1 + src/ec/smsc/Makefile.inc | 1 + src/ec/smsc/mec1308/Kconfig | 4 + src/ec/smsc/mec1308/Makefile.inc | 2 + src/ec/smsc/mec1308/acpi/ac.asl | 38 +++++ src/ec/smsc/mec1308/acpi/battery.asl | 196 ++++++++++++++++++++++++ src/ec/smsc/mec1308/acpi/ec.asl | 272 ++++++++++++++++++++++++++++++++++ src/ec/smsc/mec1308/chip.h | 33 ++++ src/ec/smsc/mec1308/ec.c | 135 +++++++++++++++++ src/ec/smsc/mec1308/ec.h | 41 +++++ 12 files changed, 725 insertions(+), 1 deletions(-) diff --git a/src/ec/Kconfig b/src/ec/Kconfig index 2a36a32..935b40b 100644 --- a/src/ec/Kconfig +++ b/src/ec/Kconfig @@ -1,2 +1,3 @@ source src/ec/acpi/Kconfig source src/ec/lenovo/Kconfig +source src/ec/smsc/Kconfig diff --git a/src/ec/Makefile.inc b/src/ec/Makefile.inc index 69d0435..b334c1f 100644 --- a/src/ec/Makefile.inc +++ b/src/ec/Makefile.inc @@ -1,2 +1,2 @@ subdirs-$(CONFIG_EC_ACPI) += acpi -subdirs-y += lenovo +subdirs-y += lenovo smsc diff --git a/src/ec/smsc/Kconfig b/src/ec/smsc/Kconfig new file mode 100644 index 0000000..afc6e4b --- /dev/null +++ b/src/ec/smsc/Kconfig @@ -0,0 +1 @@ +source src/ec/smsc/mec1308/Kconfig diff --git a/src/ec/smsc/Makefile.inc b/src/ec/smsc/Makefile.inc new file mode 100644 index 0000000..3dd9cce --- /dev/null +++ b/src/ec/smsc/Makefile.inc @@ -0,0 +1 @@ +subdirs-$(CONFIG_EC_SMSC_MEC1308) += mec1308 diff --git a/src/ec/smsc/mec1308/Kconfig b/src/ec/smsc/mec1308/Kconfig new file mode 100644 index 0000000..0a0b04a --- /dev/null +++ b/src/ec/smsc/mec1308/Kconfig @@ -0,0 +1,4 @@ +config EC_SMSC_MEC1308 + bool + help + Shared memory mailbox interface to SMSC MEC1308 Embedded Controller. diff --git a/src/ec/smsc/mec1308/Makefile.inc b/src/ec/smsc/mec1308/Makefile.inc new file mode 100644 index 0000000..95c6c03 --- /dev/null +++ b/src/ec/smsc/mec1308/Makefile.inc @@ -0,0 +1,2 @@ +driver-y += ec.c +smm-y += ec.c diff --git a/src/ec/smsc/mec1308/acpi/ac.asl b/src/ec/smsc/mec1308/acpi/ac.asl new file mode 100644 index 0000000..d14f3a4 --- /dev/null +++ b/src/ec/smsc/mec1308/acpi/ac.asl @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +// Scope (EC0) + +Device (AC) +{ + Name (_HID, "ACPI0003") + Name (_PCL, Package () { \_SB }) + + Method (_PSR) + { + Return (ACEX) + } + + Method (_STA) + { + Return (0x0F) + } +} diff --git a/src/ec/smsc/mec1308/acpi/battery.asl b/src/ec/smsc/mec1308/acpi/battery.asl new file mode 100644 index 0000000..9b2f93b --- /dev/null +++ b/src/ec/smsc/mec1308/acpi/battery.asl @@ -0,0 +1,196 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* + * The mainboard must define strings in the root scope to + * report device-specific battery information to the OS. + * + * BATM: Model + * BATS: Serial + * BATV: Vendor + */ + +// Scope (EC0) + +Device (BAT0) +{ + Name (_HID, EISAID ("PNP0C0A")) + Name (_UID, 1) + Name (_PCL, Package () { \_SB }) + + Name (PBIF, Package () { + 0x00000001, // Power Unit: mAh + 0xFFFFFFFF, // Design Capacity + 0xFFFFFFFF, // Last Full Charge Capacity + 0x00000001, // Battery Technology: Rechargeable + 0xFFFFFFFF, // Design Voltage + 0x00000003, // Design Capacity of Warning + 0xFFFFFFFF, // Design Capacity of Low + 0x00000001, // Capacity Granularity 1 + 0x00000001, // Capacity Granularity 2 + "", // Model Number + "", // Serial Number + "LION", // Battery Type + "" // OEM Information + }) + + Name (PBST, Package () { + 0x00000000, // Battery State + 0xFFFFFFFF, // Battery Present Rate + 0xFFFFFFFF, // Battery Remaining Capacity + 0xFFFFFFFF, // Battery Present Voltage + }) + Name (BSTP, Zero) + + // Workaround for full battery status, enabled by default + Name (BFWK, One) + + // Method to enable full battery workaround + Method (BFWE) + { + Store (One, BFWK) + } + + // Method to disable full battery workaround + Method (BFWD) + { + Store (Zero, BFWK) + } + + // Swap bytes in a word + Method (SWAB, 1, NotSerialized) + { + ShiftRight (Arg0, 8, Local0) + ShiftLeft (Arg0, 8, Local1) + And (Local1, 0xFF00, Local1) + Or (Local0, Local1, Local0) + If (LEqual (Local0, 0xFFFF)) { + Store (0xFFFFFFFF, Local0) + } + Return (Local0) + } + + Method (_STA, 0, Serialized) + { + If (BTEX) { + Return (0x1F) + } Else { + Return (0x0F) + } + } + + Method (_BIF, 0, Serialized) + { + // Update fields from EC + Store (SWAB (BTDA), Index (PBIF, 1)) + Store (SWAB (BTDF), Index (PBIF, 2)) + Store (SWAB (BTDV), Index (PBIF, 4)) + Store (SWAB (BTDL), Index (PBIF, 6)) + + // Get battery info from mainboard + Store (\BATM, Index (PBIF, 9)) + Store (\BATS, Index (PBIF, 10)) + Store (\BATV, Index (PBIF, 12)) + + Return (PBIF) + } + + Method (_BST, 0, Serialized) + { + // + // 0: BATTERY STATE + // + // bit 0 = discharging + // bit 1 = charging + // bit 2 = critical level + // + + // Get battery state from EC + Store (BTST, Local0) + Store (Zero, Local1) + + // Check if AC is present + If (ACEX) { + // Set only charging/discharging bits + And (Local0, 0x03, Local1) + } Else { + // Always discharging when on battery power + Store (0x01, Local1) + } + + // Flag if the battery level is critical + And (Local0, 0x04, Local4) + Or (Local1, Local4, Local1) + Store (Local1, Index (PBST, 0)) + + // Notify if battery state has changed since last time + If (LNotEqual (Local1, BSTP)) { + Store (Local1, BSTP) + Notify (BAT0, 0x80) + } + + // + // 1: BATTERY PRESENT RATE + // + + Store (SWAB (BTPR), Local1) + If (LAnd (LNotEqual (Local1, 0xFFFFFFFF), + LGreaterEqual (Local1, 0x8000))) { + Xor (Local1, 0xFFFF, Local1) + Increment (Local1) + } + Store (Local1, Index (PBST, 1)) + + // + // 2: BATTERY REMAINING CAPACITY + // + Store (SWAB (BTRA), Local1) + If (LAnd (LNotEqual (Local1, 0xFFFFFFFF), + LGreaterEqual (Local1, 0x8000))) { + Xor (Local1, 0xFFFF, Local1) + Increment (Local1) + } + + If (LAnd (BFWK, LAnd (ACEX, LNot (Local0)))) { + // On AC power and battery is neither charging + // nor discharging. Linux expects a full battery + // to report same capacity as last full charge. + // https://bugzilla.kernel.org/show_bug.cgi?id=12632 + Store (SWAB (BTDF), Local2) + + // See if within ~3% of full + ShiftRight (Local2, 5, Local3) + If (LAnd (LGreater (Local1, Subtract (Local2, Local3)), + LLess (Local1, Add (Local2, Local3)))) + { + Store (Local2, Local1) + } + } + Store (Local1, Index (PBST, 2)) + + // + // 3: BATTERY PRESENT VOLTAGE + // + Store (SWAB (BTVO), Index (PBST, 3)) + + Return (PBST) + } +} diff --git a/src/ec/smsc/mec1308/acpi/ec.asl b/src/ec/smsc/mec1308/acpi/ec.asl new file mode 100644 index 0000000..f0b77c2 --- /dev/null +++ b/src/ec/smsc/mec1308/acpi/ec.asl @@ -0,0 +1,272 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * The mainboard must define a PNOT method to handle power + * state notifications and Notify CPU device objects to + * re-evaluate their _PPC and _CST tables. + */ + +Device (EC0) +{ + Name (_HID, EISAID ("PNP0C09")) + Name (_UID, 1) + Name (_GPE, EC_GPE) // GPE for Runtime SCI + + OperationRegion (ERAM, EmbeddedControl, 0x00, 0xff) + Field (ERAM, ByteAcc, Lock, Preserve) + { + Offset (0x80), + BTEX, 1, // Battery Exists + , 1, + ACEX, 1, // AC Exists + , 5, + Offset (0x83), + LIDS, 1, // Lid Switch State + , 7, + BTST, 8, // Battery State + Offset (0xA2), + BTRA, 16, // Battery Remaining Capacity + BTPR, 16, // Battery Present Rate + BTVO, 16, // Battery Present Voltage + Offset (0xB0), + BTDA, 16, // Battery Design Capacity + BTDF, 16, // Battery Last Full Charge Capacity + BTDV, 16, // Battery Design Voltage + BTDL, 16, // Battery Design Low + Offset (0xC0), + CPUT, 8, // CPU Temperature + Offset (0xCA), + FSL0, 1, // Fan Speed Level 0 + FSL1, 1, // Fan Speed Level 1 + FSL2, 1, // Fan Speed Level 2 + FSL3, 1, // Fan Speed Level 3 + FSL4, 1, // Fan Speed Level 4 + , 2, + FCOS, 1, // Fan Speed OS Control + } + + Method (_CRS, 0, NotSerialized) + { + Name (ECMD, ResourceTemplate() + { + IO (Decode16, 0x62, 0x62, 0, 1) + IO (Decode16, 0x66, 0x66, 0, 1) + }) + Return (ECMD) + } + + Method (_REG, 2, NotSerialized) + { + // Initialize AC power state + Store (ACEX, \PWRS) + + // Initialize LID switch state + Store (LIDS, \LIDS) + + // Enable OS control of fan speed + Store (One, FCOS) + + // Force a read of CPU temperature + Store (CPUT, Local0) + } + + PowerResource (FNP0, 0, 0) + { + Method (_STA) { Return (FSL0) } + Method (_ON) { + If (FCOS) { + Store (One, FSL0) + Store (0, \FLVL) + Notify (\_TZ.THRM, 0x81) + } + } + Method (_OFF) { + If (FCOS) { + Store (Zero, FSL0) + Store (1, \FLVL) + Notify (\_TZ.THRM, 0x81) + } + } + } + + PowerResource (FNP1, 0, 0) + { + Method (_STA) { Return (FSL1) } + Method (_ON) { + If (FCOS) { + Store (One, FSL1) + Store (1, \FLVL) + Notify (\_TZ.THRM, 0x81) + } + } + Method (_OFF) { + If (FCOS) { + Store (Zero, FSL1) + Store (2, \FLVL) + Notify (\_TZ.THRM, 0x81) + } + } + } + + PowerResource (FNP2, 0, 0) + { + Method (_STA) { Return (FSL2) } + Method (_ON) { + If (FCOS) { + Store (One, FSL2) + Store (2, \FLVL) + Notify (\_TZ.THRM, 0x81) + } + } + Method (_OFF) { + If (FCOS) { + Store (Zero, FSL2) + Store (3, \FLVL) + Notify (\_TZ.THRM, 0x81) + } + } + } + + PowerResource (FNP3, 0, 0) + { + Method (_STA) { Return (FSL3) } + Method (_ON) { + If (FCOS) { + Store (One, FSL3) + Store (3, \FLVL) + Notify (\_TZ.THRM, 0x81) + } + } + Method (_OFF) { + If (FCOS) { + Store (Zero, FSL3) + Store (4, \FLVL) + Notify (\_TZ.THRM, 0x81) + } + } + } + + PowerResource (FNP4, 0, 0) + { + Method (_STA) { Return (FSL4) } + Method (_ON) { + If (FCOS) { + Store (One, FSL4) + Store (4, \FLVL) + Notify (\_TZ.THRM, 0x81) + } + } + Method (_OFF) { + If (FCOS) { + Store (Zero, FSL4) + Store (5, \FLVL) + Notify (\_TZ.THRM, 0x81) + } + } + } + + Device (FAN0) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 0) + Name (_PR0, Package () { FNP0 }) + } + + Device (FAN1) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 1) + Name (_PR0, Package () { FNP1 }) + } + + Device (FAN2) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 2) + Name (_PR0, Package () { FNP2 }) + } + + Device (FAN3) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 3) + Name (_PR0, Package () { FNP3 }) + } + + Device (FAN4) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 4) + Name (_PR0, Package () { FNP4 }) + } + + // AC Power Connected + Method (_Q51, 0, NotSerialized) + { + Store (One, \PWRS) + Notify (AC, 0x80) + \PNOT () + } + + // AC Power Removed + Method (_Q52, 0, NotSerialized) + { + Store (Zero, \PWRS) + Notify (AC, 0x80) + \PNOT () + } + + // Battery State Change + Method (_Q53, 0, NotSerialized) + { + Notify (BAT0, 0x80) + Notify (BAT0, 0x81) + } + + // Battery State Change + Method (_Q54, 0, NotSerialized) + { + Notify (BAT0, 0x80) + Notify (BAT0, 0x81) + } + + // Power State Change + Method (_Q55, 0, NotSerialized) + { + \PNOT () + } + + // Lid Switch Event + Method (_Q5E, 0, NotSerialized) + { + Store (LIDS, \LIDS) + Notify (\_SB.LID0, 0x80) + } + + // Lid Switch Event + Method (_Q5F, 0, NotSerialized) + { + Store (LIDS, \LIDS) + Notify (\_SB.LID0, 0x80) + } + + #include "ac.asl" + #include "battery.asl" +} diff --git a/src/ec/smsc/mec1308/chip.h b/src/ec/smsc/mec1308/chip.h new file mode 100644 index 0000000..3a8eae8 --- /dev/null +++ b/src/ec/smsc/mec1308/chip.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _EC_SMSC_MEC1308_CHIP_H +#define _EC_SMSC_MEC1308_CHIP_H + +struct ec_smsc_mec1308_config +{ + u16 mailbox_port; +}; + +struct chip_operations; +extern struct chip_operations ec_smsc_mec1308_ops; + +#endif /* _EC_SMSC_MEC1308_CHIP_H */ diff --git a/src/ec/smsc/mec1308/ec.c b/src/ec/smsc/mec1308/ec.c new file mode 100644 index 0000000..bfd3c14 --- /dev/null +++ b/src/ec/smsc/mec1308/ec.c @@ -0,0 +1,135 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <arch/io.h> +#include <delay.h> +#include "ec.h" +#include "chip.h" + +static u16 ec_cmd_reg = 0; +static u16 ec_data_reg = 0; + +static inline u8 __ec_read(u8 addr) +{ + outb(addr, ec_cmd_reg); + return inb(ec_data_reg); +} + +static inline void __ec_write(u8 addr, u8 data) +{ + outb(addr, ec_cmd_reg); + outb(data, ec_data_reg); +} + +static int ec_ready(void) +{ + u16 timeout = EC_TIMEOUT; + + if (!ec_cmd_reg || !ec_data_reg) { + printk(BIOS_DEBUG, "Invalid ports: cmd=0x%x data=0x%x\n", + ec_cmd_reg, ec_data_reg); + return -1; + } + + while (__ec_read(EC_MAILBOX_COMMAND) != 0 && --timeout) { + udelay(10); + if ((timeout & 0xff) == 0) + printk(BIOS_SPEW, "."); + } + if (!timeout) { + printk(BIOS_DEBUG, "Timeout waiting for EC to be ready.\n"); + return -1; + } + return 0; +} + +int send_ec_command(u8 command) +{ + if (ec_ready() < 0) + return -1; + __ec_write(EC_MAILBOX_COMMAND, command); + return ec_ready(); +} + +int send_ec_command_data(u8 command, u8 data) +{ + if (ec_ready() < 0) + return -1; + __ec_write(EC_MAILBOX_DATA, data); + __ec_write(EC_MAILBOX_COMMAND, command); + return ec_ready(); +} + +u8 read_ec_command_byte(u8 command) +{ + send_ec_command(command); + return __ec_read(EC_MAILBOX_DATA); +} + +u8 ec_read(u8 addr) +{ + if (send_ec_command_data(EC_RAM_READ, addr) < 0) + return 0; + return __ec_read(EC_MAILBOX_DATA); +} + +int ec_write(u8 addr, u8 data) +{ + if (ec_ready() < 0) + return -1; + __ec_write(EC_MAILBOX_DATA, addr); + __ec_write(EC_MAILBOX_DATA_H, data); + __ec_write(EC_MAILBOX_COMMAND, EC_RAM_WRITE); + return ec_ready(); +} + +void ec_set_bit(u8 addr, u8 bit) +{ + ec_write(addr, ec_read(addr) | (1 << bit)); +} + +void ec_clr_bit(u8 addr, u8 bit) +{ + ec_write(addr, ec_read(addr) & ~(1 << bit)); +} + +void ec_set_ports(u16 cmd_reg, u16 data_reg) +{ + ec_cmd_reg = cmd_reg; + ec_data_reg = data_reg; +} + +static void mec1308_enable(device_t dev) +{ + struct ec_smsc_mec1308_config *conf = dev->chip_info; + + if (conf->mailbox_port) { + ec_cmd_reg = conf->mailbox_port; + ec_data_reg = conf->mailbox_port + 1; + } +} + +struct chip_operations ec_smsc_mec1308_ops = { + CHIP_NAME("SMSC MEC1308 EC Mailbox Interface") + .enable_dev = mec1308_enable +}; diff --git a/src/ec/smsc/mec1308/ec.h b/src/ec/smsc/mec1308/ec.h new file mode 100644 index 0000000..07bfc4f --- /dev/null +++ b/src/ec/smsc/mec1308/ec.h @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + * Mailbox EC communication interface for SMSC MEC1308 Embedded Controller. + */ + +#ifndef _EC_SMSC_MEC1308_EC_H +#define _EC_SMSC_MEC1308_EC_H + +#define EC_TIMEOUT 0xfff +#define EC_MAILBOX_COMMAND 0x82 // Send a command +#define EC_MAILBOX_DATA 0x84 // Send data with a command +#define EC_MAILBOX_DATA_H 0x85 // Send data with a command +#define EC_RAM_READ 0x88 // Read from RAM +#define EC_RAM_WRITE 0x89 // Write to RAM + +int send_ec_command(u8 command); +int send_ec_command_data(u8 command, u8 data); +u8 read_ec_command_byte(u8 command); +u8 ec_read(u8 addr); +int ec_write(u8 addr, u8 data); +void ec_set_bit(u8 addr, u8 bit); +void ec_clr_bit(u8 addr, u8 bit); +void ec_set_ports(u16 cmd_reg, u16 data_reg); + +#endif /* _EC_SMSC_MEC1308_EC_H */

1 0

New patch to review for coreboot: 2a561db Don't loop infinitely long on serial comm failures
by Stefan Reinauer 31 Mar '12

31 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/826 -gerrit commit 2a561dbd95074be053c7c3349a7a62b16889a01d Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Mar 30 16:19:31 2012 -0700 Don't loop infinitely long on serial comm failures If serial uart (8250/16x50) takes abnormally long to respond, give up on logging to serial console and instead let the system boot. Also reference bit in LSR register with correct name. Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Ported from 9dd3ef165a1bf1bc404056d3e54337de1a15ac90 to uart8250mem.c: Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Change-Id: Iaca4f57389c887110e6406d45053935891c96838 --- src/lib/uart8250mem.c | 30 +++++++++++++++++++++--------- 1 files changed, 21 insertions(+), 9 deletions(-) diff --git a/src/lib/uart8250mem.c b/src/lib/uart8250mem.c index a38623e..122e475 100644 --- a/src/lib/uart8250mem.c +++ b/src/lib/uart8250mem.c @@ -30,21 +30,30 @@ /* Should support 8250, 16450, 16550, 16550A type UARTs */ +/* Expected character delay at 1200bps is 9ms for a working UART + * and no flow-control. Assume UART as stuck if shift register + * or FIFO takes more than 50ms per character to appear empty. + * + * Estimated that inb() from UART takes 1 microsecond. + */ +#define SINGLE_CHAR_TIMEOUT (50 * 1000) +#define FIFO_TIMEOUT (16 * SINGLE_CHAR_TIMEOUT) + static inline int uart8250_mem_can_tx_byte(unsigned base_port) { - return read8(base_port + UART_LSR) & UART_MSR_DSR; + return read8(base_port + UART_LSR) & UART_LSR_THRE; } static inline void uart8250_mem_wait_to_tx_byte(unsigned base_port) { - while(!uart8250_mem_can_tx_byte(base_port)) - ; + unsigned long int i = SINGLE_CHAR_TIMEOUT; + while(i-- && !uart8250_mem_can_tx_byte(base_port)); } static inline void uart8250_mem_wait_until_sent(unsigned base_port) { - while(!(read8(base_port + UART_LSR) & UART_LSR_TEMT)) - ; + unsigned long int i = FIFO_TIMEOUT; + while(i-- && !(read8(base_port + UART_LSR) & UART_LSR_TEMT)); } void uart8250_mem_tx_byte(unsigned base_port, unsigned char data) @@ -65,9 +74,12 @@ int uart8250_mem_can_rx_byte(unsigned base_port) unsigned char uart8250_mem_rx_byte(unsigned base_port) { - while(!uart8250_mem_can_rx_byte(base_port)) - ; - return read8(base_port + UART_RBR); + unsigned long int i = SINGLE_CHAR_TIMEOUT; + while(i-- & !uart8250_mem_can_rx_byte(base_port)) ; + if (i) + return read8(base_port + UART_RBR); + else + return 0x0; } void uart8250_mem_init(unsigned base_port, unsigned divisor) @@ -83,7 +95,7 @@ void uart8250_mem_init(unsigned base_port, unsigned divisor) /* DLAB on */ write8(base_port + UART_LCR, UART_LCR_DLAB | CONFIG_TTYS0_LCS); - /* Set Baud Rate Divisor. 12 ==> 115200 Baud */ + /* Set Baud Rate Divisor. 12 ==> 9600 Baud */ write8(base_port + UART_DLL, divisor & 0xFF); write8(base_port + UART_DLM, (divisor >> 8) & 0xFF);

1 0

New patch to review for coreboot: c39f9f6 Add support for SMSC MEC1308/1310 SuperI/O EC
by Stefan Reinauer 31 Mar '12

31 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/825 -gerrit commit c39f9f6ac75e9f220e6bb2404cf7f48eafc4a825 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Mar 30 15:12:22 2012 -0700 Add support for SMSC MEC1308/1310 SuperI/O EC Change-Id: If7921a66bab35f72c8455d5f0befc32a514ab417 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/superio/smsc/Kconfig | 2 + src/superio/smsc/Makefile.inc | 1 + src/superio/smsc/mec1308/Makefile.inc | 20 ++ src/superio/smsc/mec1308/acpi/superio.asl | 261 +++++++++++++++++++++++++ src/superio/smsc/mec1308/chip.h | 34 ++++ src/superio/smsc/mec1308/mec1308.h | 27 +++ src/superio/smsc/mec1308/mec1308_early_init.c | 29 +++ src/superio/smsc/mec1308/superio.c | 121 ++++++++++++ 8 files changed, 495 insertions(+), 0 deletions(-) diff --git a/src/superio/smsc/Kconfig b/src/superio/smsc/Kconfig index 224376b..8d66fc5 100644 --- a/src/superio/smsc/Kconfig +++ b/src/superio/smsc/Kconfig @@ -40,6 +40,8 @@ config SUPERIO_SMSC_SIO1007 bool config SUPERIO_SMSC_KBC1100 bool +config SUPERIO_SMSC_MEC1308 + bool config SUPERIO_SMSC_SMSCSUPERIO bool config SUPERIO_SMSC_SIO1036 diff --git a/src/superio/smsc/Makefile.inc b/src/superio/smsc/Makefile.inc index bb4bf1d..8ebdf05 100644 --- a/src/superio/smsc/Makefile.inc +++ b/src/superio/smsc/Makefile.inc @@ -29,6 +29,7 @@ subdirs-y += lpc47n227 subdirs-y += sio10n268 subdirs-y += sio1007 subdirs-y += kbc1100 +subdirs-y += mec1308 subdirs-y += smscsuperio subdirs-y += sio1036 subdirs-y += sch4037 diff --git a/src/superio/smsc/mec1308/Makefile.inc b/src/superio/smsc/mec1308/Makefile.inc new file mode 100644 index 0000000..b2b7baa --- /dev/null +++ b/src/superio/smsc/mec1308/Makefile.inc @@ -0,0 +1,20 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Google Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +ramstage-$(CONFIG_SUPERIO_SMSC_MEC1308) += superio.c diff --git a/src/superio/smsc/mec1308/acpi/superio.asl b/src/superio/smsc/mec1308/acpi/superio.asl new file mode 100644 index 0000000..96f2ef8 --- /dev/null +++ b/src/superio/smsc/mec1308/acpi/superio.asl @@ -0,0 +1,261 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Scope is \_SB.PCI0.LPCB + +Device (SIO) { + OperationRegion (SIOA, SystemIO, 0x2E, 0x02) + Field (SIOA, ByteAcc, NoLock, Preserve) + { + SI2E, 8, + SI2F, 8, + } + + IndexField (SI2E, SI2F, ByteAcc, NoLock, Preserve) + { + Offset (0x07), + SLDN, 8, /* Logical Device Number */ + Offset (0x30), + SACT, 8, /* Activate */ + Offset (0x60), + IO0H, 8, /* Base Address 0 MSB */ + IO0L, 8, /* Base Address 0 LSB */ + Offset (0x62), + IO1H, 8, /* Base Address 1 MSB */ + IO1L, 8, /* Base Address 1 LSB */ + Offset (0x70), + IQ00, 8, /* Interrupt Select */ + } + + Name (LPM1, 1) /* ACPI PM1 */ + Name (LEC1, 2) /* EC 1 */ + Name (LEC2, 3) /* EC 2 */ + Name (LSP1, 4) /* Serial Port */ + Name (LKBC, 7) /* Keyboard */ + Name (LEC0, 8) /* EC 0 */ + Name (LMBX, 9) /* Mailbox */ + + Method (ENTR, 0, NotSerialized) + { + Store (0x55, SI2E) + } + + Method (EXIT, 0, NotSerialized) + { + Store (0xaa, SI2E) + } + + /* Parse activate register for an LDN */ + Method (ISEN, 1, NotSerialized) + { + ENTR () + Store (Arg0, SLDN) + Store (SACT, Local0) + EXIT () + + /* Check if it exists */ + If (LEqual (Local0, 0xFF)) + { + Return (0x00) + } + + /* Check if activated */ + If (LEqual (Local0, One)) + { + Return (0x0F) + } + Else + { + Return (0x0D) + } + } + + /* Enable an LDN via the activate register */ + Method (SENA, 1, NotSerialized) + { + ENTR () + Store (Arg0, SLDN) + Store (One, SACT) + EXIT () + } + + /* Disable an LDN via the activate register */ + Method (SDIS, 1, NotSerialized) + { + ENTR () + Store (Arg0, SLDN) + Store (Zero, SACT) + EXIT () + } + +#ifdef SIO_ENABLE_SPM1 + Device (SPM1) { + Name (_HID, EISAID ("PNP0C02")) + Name (_UID, 1) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (LPM1)) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, SIO_SPM1_IO0, SIO_SPM1_IO0, 0x08, 0x08) + }) + + Name (_PRS, ResourceTemplate () + { + IO (Decode16, SIO_SPM1_IO0, SIO_SPM1_IO0, 0x08, 0x08) + }) + } +#endif + +#ifdef SIO_ENABLE_SEC1 + Device (SEC1) { + Name (_HID, EISAID ("PNP0C09")) + Name (_UID, 2) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (LEC1)) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, SIO_SEC1_IO0, SIO_SEC1_IO0, 0x04, 0x04) + }) + + Name (_PRS, ResourceTemplate () + { + IO (Decode16, SIO_SEC1_IO0, SIO_SEC1_IO0, 0x04, 0x04) + }) + } +#endif + +#ifdef SIO_ENABLE_SEC2 + Device (SEC2) { + Name (_HID, EISAID ("PNP0C09")) + Name (_UID, 3) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (LEC2)) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, SIO_SEC2_IO0, SIO_SEC2_IO0, 0x04, 0x04) + }) + + Name (_PRS, ResourceTemplate () + { + IO (Decode16, SIO_SEC2_IO0, SIO_SEC2_IO0, 0x04, 0x04) + }) + } +#endif + +#ifdef SIO_ENABLE_SSP1 + Device (SSP1) { + Name (_HID, EISAID ("PNP0501")) + Name (_UID, 4) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (LSP1)) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, SIO_SSP1_IO0, SIO_SSP1_IO0, 0x08, 0x08) + IRQNoFlags () {SIO_SSP1_IRQ} + }) + + Name (_PRS, ResourceTemplate () + { + IO (Decode16, SIO_SSP1_IO0, SIO_SSP1_IO0, 0x08, 0x08) + IRQNoFlags () {SIO_SSP1_IRQ} + }) + } +#endif + +#ifdef SIO_ENABLE_SKBC + Device (SKBC) // Keyboard + { + Name (_HID, EISAID("PNP0303")) + Name (_CID, EISAID("PNP030B")) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (LKBC)) + } + + Name (_CRS, ResourceTemplate() + { + IO (Decode16, 0x60, 0x60, 0x01, 0x01) + IO (Decode16, 0x64, 0x64, 0x01, 0x01) + IRQNoFlags () {1} + }) + + Name (_PRS, ResourceTemplate() + { + IO (Decode16, 0x60, 0x60, 0x01, 0x01) + IO (Decode16, 0x64, 0x64, 0x01, 0x01) + IRQNoFlags () {1} + }) + } +#endif + +#ifdef SIO_ENABLE_SEC0 + Device (SEC0) { + Name (_HID, EISAID ("PNP0C09")) + Name (_UID, 8) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (LEC0)) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, SIO_SEC0_IO0, SIO_SEC0_IO0, 0x04, 0x04) + }) + + Name (_PRS, ResourceTemplate () + { + IO (Decode16, SIO_SEC0_IO0, SIO_SEC0_IO0, 0x04, 0x04) + }) + } +#endif + +#ifdef SIO_ENABLE_SMBX + Device (SMBX) // Mailbox + { + Name (_HID, EISAID("PNP0C02")) + Name (_UID, 9) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (LMBX)) + } + + Name (_CRS, ResourceTemplate() + { + IO (Decode16, SIO_SMBX_IO0, SIO_SMBX_IO0, 0x34, 0x34) + }) + + Name (_PRS, ResourceTemplate() + { + IO (Decode16, SIO_SMBX_IO0, SIO_SMBX_IO0, 0x34, 0x34) + }) + } +#endif +} diff --git a/src/superio/smsc/mec1308/chip.h b/src/superio/smsc/mec1308/chip.h new file mode 100644 index 0000000..04e829d --- /dev/null +++ b/src/superio/smsc/mec1308/chip.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_SMSC_MEC1308_CHIP_H +#define SUPERIO_SMSC_MEC1308_CHIP_H + +#include <pc80/keyboard.h> +#include <uart8250.h> + +struct chip_operations; +extern struct chip_operations superio_smsc_mec1308_ops; + +struct superio_smsc_mec1308_config { + + struct pc_keyboard keyboard; +}; + +#endif diff --git a/src/superio/smsc/mec1308/mec1308.h b/src/superio/smsc/mec1308/mec1308.h new file mode 100644 index 0000000..2b61234 --- /dev/null +++ b/src/superio/smsc/mec1308/mec1308.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define MEC1308_PM1 1 +#define MEC1308_EC1 2 +#define MEC1308_EC2 3 +#define MEC1308_UART 4 +#define MEC1308_KBC 7 +#define MEC1308_EC0 8 +#define MEC1308_MBX 9 + diff --git a/src/superio/smsc/mec1308/mec1308_early_init.c b/src/superio/smsc/mec1308/mec1308_early_init.c new file mode 100644 index 0000000..60d43a7 --- /dev/null +++ b/src/superio/smsc/mec1308/mec1308_early_init.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Pre-RAM driver for the SMSC MEC1308 EC chip */ + +#include <arch/romcc_io.h> +#include "mec1308.h" + +static inline void mec1308_early_init(unsigned port) +{ + +} + diff --git a/src/superio/smsc/mec1308/superio.c b/src/superio/smsc/mec1308/superio.c new file mode 100644 index 0000000..dfa155f --- /dev/null +++ b/src/superio/smsc/mec1308/superio.c @@ -0,0 +1,121 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* RAM driver for the SMSC KBC1100 Super I/O chip */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pnp.h> +#include <console/console.h> +#include <device/smbus.h> +#include <string.h> +#include <bitops.h> +#include <pc80/keyboard.h> +#include <stdlib.h> +#include "chip.h" +#include "mec1308.h" +#if CONFIG_HAVE_ACPI_RESUME +#include <arch/acpi.h> +#endif + +static void pnp_enter_conf_state(device_t dev) +{ + outb(0x55, dev->path.pnp.port); +} + +static void pnp_exit_conf_state(device_t dev) +{ + outb(0xaa, dev->path.pnp.port); +} + +static void mec1308_pnp_set_resources(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_set_resources(dev); + pnp_exit_conf_state(dev); +} + +static void mec1308_pnp_enable_resources(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_enable_resources(dev); + pnp_exit_conf_state(dev); +} + +static void mec1308_pnp_enable(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + + if(dev->enabled) { + pnp_set_enable(dev, 1); + } + else { + pnp_set_enable(dev, 0); + } + pnp_exit_conf_state(dev); +} + +static void mec1308_init(device_t dev) +{ + struct superio_smsc_mec1308_config *conf = dev->chip_info; + + if (!dev->enabled) + return; + + switch(dev->path.pnp.device) { + case MEC1308_KBC: +#if CONFIG_HAVE_ACPI_RESUME + if (acpi_slp_type == 3) + return; +#endif + pc_keyboard_init(&conf->keyboard); + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = mec1308_pnp_set_resources, + .enable_resources = mec1308_pnp_enable_resources, + .enable = mec1308_pnp_enable, + .init = mec1308_init, +}; + +static struct pnp_info pnp_dev_info[] = { + { &ops, MEC1308_PM1, PNP_IO0, { 0x7ff, 0 } }, + { &ops, MEC1308_EC1, PNP_IO0, { 0x7ff, 0 } }, + { &ops, MEC1308_EC2, PNP_IO0, { 0x7ff, 0 } }, + { &ops, MEC1308_UART, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, + { &ops, MEC1308_KBC, PNP_IRQ0, { 0, 0 } /* IO Fixed at 0x60/0x64 */ }, + { &ops, MEC1308_EC0, PNP_IO0, { 0x7ff, 0 } }, + { &ops, MEC1308_MBX, PNP_IO0, { 0x7ff, 0 } }, +}; + +static void enable_dev(device_t dev) +{ + pnp_enable_devices(dev, &pnp_ops, + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_smsc_mec1308_ops = { + CHIP_NAME("SMSC MEC1308 EC SuperIO Interface") + .enable_dev = enable_dev +}; +

1 0

New patch to review for coreboot: af1b954 Add initial support for SMSC SIO1007 SuperI/O chip
by Stefan Reinauer 31 Mar '12

31 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/824 -gerrit commit af1b9542e7088f428e64d53e5d3adc665a3601cf Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Mar 30 15:10:07 2012 -0700 Add initial support for SMSC SIO1007 SuperI/O chip early_serial and some ACPI needed for compilation Change-Id: I5dd970676488697156e0630392884f31149ac85b Signed-off-by: Gabe Black <gabeblack(a)google.com> --- src/superio/smsc/Kconfig | 2 + src/superio/smsc/Makefile.inc | 1 + src/superio/smsc/sio1007/acpi/superio.asl | 299 +++++++++++++++++++++++++++++ src/superio/smsc/sio1007/early_serial.c | 64 ++++++ 4 files changed, 366 insertions(+), 0 deletions(-) diff --git a/src/superio/smsc/Kconfig b/src/superio/smsc/Kconfig index d4f07ec..224376b 100644 --- a/src/superio/smsc/Kconfig +++ b/src/superio/smsc/Kconfig @@ -36,6 +36,8 @@ config SUPERIO_SMSC_LPC47N227 bool config SUPERIO_SMSC_SIO10N268 bool +config SUPERIO_SMSC_SIO1007 + bool config SUPERIO_SMSC_KBC1100 bool config SUPERIO_SMSC_SMSCSUPERIO diff --git a/src/superio/smsc/Makefile.inc b/src/superio/smsc/Makefile.inc index d07afea..bb4bf1d 100644 --- a/src/superio/smsc/Makefile.inc +++ b/src/superio/smsc/Makefile.inc @@ -27,6 +27,7 @@ subdirs-y += lpc47m15x subdirs-y += lpc47n217 subdirs-y += lpc47n227 subdirs-y += sio10n268 +subdirs-y += sio1007 subdirs-y += kbc1100 subdirs-y += smscsuperio subdirs-y += sio1036 diff --git a/src/superio/smsc/sio1007/acpi/superio.asl b/src/superio/smsc/sio1007/acpi/superio.asl new file mode 100644 index 0000000..5bb45fa --- /dev/null +++ b/src/superio/smsc/sio1007/acpi/superio.asl @@ -0,0 +1,299 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Scope is \_SB.PCI0.LPCB + +Device (SIO) { + Name (_ADR, 0x2E) + OperationRegion (SIOA, SystemIO, 0x2E, 0x02) + Field (SIOA, ByteAcc, NoLock, Preserve) + { + SI2E, 8, + SI2F, 8, + } + + IndexField (SI2E, SI2F, ByteAcc, NoLock, Preserve) + { + Offset (0x02), + SCNT, 8, /* Configure Control */ + Offset (0x07), + SLDN, 8, /* Logical Device Number */ + Offset (0x30), + SACT, 8, /* Activate */ + Offset (0x60), + IO0H, 8, /* Base Address 0 MSB */ + IO0L, 8, /* Base Address 0 LSB */ + Offset (0x62), + IO1H, 8, /* Base Address 1 MSB */ + IO1L, 8, /* Base Address 1 LSB */ + Offset (0x70), + IQ00, 8, /* Interrupt Select */ + } + + Name (SFDC, 0) /* Floppy Disk Controller */ + Name (SSP1, 1) /* Serial Port 1 */ + Name (SENV, 4) /* Environment Controller */ + Name (SKBC, 5) /* Keyboard */ + Name (SKBM, 6) /* Mouse */ + Name (SGPI, 7) /* GPIO */ + Name (SINF, 10) /* Consumer IR */ + + Method (ENTR, 0, NotSerialized) + { + Store (0x87, SI2E) + Store (0x01, SI2E) + Store (0x55, SI2E) + Store (0x55, SI2E) + } + + Method (EXIT, 0, NotSerialized) + { + Store (0x02, SCNT) + } + + /* Parse activate register for an LDN */ + Method (ISEN, 1, NotSerialized) + { + ENTR () + Store (Arg0, SLDN) + Store (SACT, Local0) + EXIT () + + /* Check if it exists */ + If (LEqual (Local0, 0xFF)) + { + Return (0x00) + } + + /* Check if activated */ + If (LEqual (Local0, One)) + { + Return (0x0F) + } + Else + { + Return (0x0D) + } + } + + /* Enable an LDN via the activate register */ + Method (SENA, 1, NotSerialized) + { + ENTR () + Store (Arg0, SLDN) + Store (One, SACT) + EXIT () + } + + /* Disable an LDN via the activate register */ + Method (SDIS, 1, NotSerialized) + { + ENTR () + Store (Arg0, SLDN) + Store (Zero, SACT) + EXIT () + } + +#ifdef SIO_ENABLE_ENVC + Device (ENVC) { + Name (_HID, EISAID ("PNP0C02")) + Name (_UID, 10) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (SENV)) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, SIO_ENVC_IO0, SIO_ENVC_IO0, 0x08, 0x08) + IO (Decode16, SIO_ENVC_IO1, SIO_ENVC_IO1, 0x04, 0x04) + }) + + Name (_PRS, ResourceTemplate () + { + IO (Decode16, SIO_ENVC_IO0, SIO_ENVC_IO0, 0x08, 0x08) + IO (Decode16, SIO_ENVC_IO1, SIO_ENVC_IO1, 0x04, 0x04) + }) + + OperationRegion (ECAP, SystemIO, SIO_ENVC_IO0, 0x07) + Field (ECAP, ByteAcc, NoLock, Preserve) + { + Offset (0x05), + ECAI, 8, // Address Index Register + ECAD, 8, // Address Data Register + } + + // Registers for thermal zone implementations + IndexField (ECAI, ECAD, ByteAcc, NoLock, Preserve) + { + Offset (0x29), + TIN1, 8, // TMPIN1 Reading + TIN2, 8, // TMPIN2 Reading + TIN3, 8, // TMPIN3 Reading + Offset (0x6b), + F2PS, 8, // FAN2 PWM Setting + Offset (0x73), + F3PS, 8, // FAN3 PWM Setting + } + } +#endif + +#ifdef SIO_ENABLE_GPIO + Device (GPIO) { + Name (_HID, EISAID ("PNP0C02")) + Name (_UID, 11) + + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, SIO_GPIO_IO0, SIO_GPIO_IO0, 0x01, 0x01) + IO (Decode16, SIO_GPIO_IO1, SIO_GPIO_IO1, 0x08, 0x08) + }) + + Name (_PRS, ResourceTemplate () + { + IO (Decode16, SIO_GPIO_IO0, SIO_GPIO_IO0, 0x01, 0x01) + IO (Decode16, SIO_GPIO_IO1, SIO_GPIO_IO1, 0x08, 0x08) + }) + } +#endif + +#ifdef SIO_ENABLE_COM1 + Device (COM1) { + Name (_HID, EISAID ("PNP0501")) + Name (_UID, 1) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (SSP1)) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08) + IRQNoFlags () {4} + }) + + Name (_PRS, ResourceTemplate () + { + IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08) + IRQNoFlags () {4} + }) + } +#endif + +#ifdef SIO_ENABLE_PS2K + Device (PS2K) // Keyboard + { + Name (_HID, EISAID("PNP0303")) + Name (_CID, EISAID("PNP030B")) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (SKBC)) + } + + Name (_CRS, ResourceTemplate() + { + IO (Decode16, 0x60, 0x60, 0x01, 0x01) + IO (Decode16, 0x64, 0x64, 0x01, 0x01) + IRQNoFlags () {1} + }) + + Name (_PRS, ResourceTemplate() + { + IO (Decode16, 0x60, 0x60, 0x01, 0x01) + IO (Decode16, 0x64, 0x64, 0x01, 0x01) + IRQNoFlags () {1} + }) + } +#endif + +#ifdef SIO_ENABLE_PS2M + Device (PS2M) // Mouse + { + Name (_HID, EISAID("PNP0F13")) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (SKBM)) + } + + Name (_CRS, ResourceTemplate() + { + IRQNoFlags () {12} + }) + + Name (_PRS, ResourceTemplate() + { + IRQNoFlags () {12} + }) + } +#endif + +#ifdef SIO_ENABLE_FDC0 + Device (FDC0) // Floppy controller + { + Name (_HID, EISAID ("PNP0700")) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (SFDC)) + } + + Name (_CRS, ResourceTemplate() + { + IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06) + IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01) + IRQNoFlags () {6} + DMA (Compatibility, NotBusMaster, Transfer8) {2} + }) + + Name (_PRS, ResourceTemplate() + { + IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06) + IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01) + IRQNoFlags () {6} + DMA (Compatibility, NotBusMaster, Transfer8) {2} + }) + } +#endif + +#ifdef SIO_ENABLE_INFR + Device (INFR) // Infrared controller + { + Name (_HID, EISAID ("PNP0510")) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (SINF)) + } + + Name (_CRS, ResourceTemplate() + { + IO (Decode16, SIO_INFR_IO0, SIO_INFR_IO0, 0x08, 0x08) + IRQNoFlags () { SIO_INFR_IRQ } + }) + + Name (_PRS, ResourceTemplate() + { + IO (Decode16, SIO_INFR_IO0, SIO_INFR_IO0, 0x08, 0x08) + IRQNoFlags () { SIO_INFR_IRQ } + }) + } +#endif +} diff --git a/src/superio/smsc/sio1007/early_serial.c b/src/superio/smsc/sio1007/early_serial.c new file mode 100644 index 0000000..859e351 --- /dev/null +++ b/src/superio/smsc/sio1007/early_serial.c @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * The chip could be bootstrap mapped to one of four LPC addresses: + * 0x2e, 0x4e, 0x162e, and 0x164e. + */ +const u16 sio1007_lpc_ports[] = {0x2e, 0x4e, 0x162e, 0x164e}; + +static void sio1007_setreg(u16 lpc_port, u8 reg, u8 value, u8 mask) +{ + u8 reg_value; + + outb(reg, lpc_port); + reg_value = inb(lpc_port + 1); + reg_value &= ~mask; + reg_value |= (value & mask); + outb(reg_value, lpc_port + 1); +} + +static int sio1007_enable_uart_at(u16 port) +{ + /* Enable config mode. */ + outb(0x55, port); + if (inb(port) != 0x55) + return 0; /* There is no LPC device at this address. */ + + /* Registers 12 and 13 hold config address, look for a match. */ + outb(0x12, port); + if (inb(port + 1) != (port & 0xff)) + return 0; + + outb(0x13, port); + if (inb(port + 1) != (port >> 8)) + return 0; + + /* This must be the sio1007, enable the UART. */ + /* turn on power */ + sio1007_setreg(port, 0x2, 1 << 3, 1 << 3); + /* enable high speed */ + sio1007_setreg(port, 0xc, 1 << 6, 1 << 6); + /* set the base address */ + sio1007_setreg(port, 0x24, CONFIG_TTYS0_BASE >> 2, 0xff); + + /* Disable config mode. */ + outb(0xaa, port); + return 1; +}

1 0

New patch to review for coreboot: 56eca08 Add support for SMSC LPC47N207 SuperI/O chip
by Stefan Reinauer 31 Mar '12

31 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/823 -gerrit commit 56eca08e465dce889c18eba8020196fa41d3bfff Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Mar 30 15:06:04 2012 -0700 Add support for SMSC LPC47N207 SuperI/O chip This includes only early serial support for now. Change-Id: I9a2a439e1d17a989428033fdb4a4b813553dab6d Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/superio/smsc/lpc47n207/early_serial.c | 122 +++++++++++++++++++++++++++++ src/superio/smsc/lpc47n207/lpc47n207.h | 25 ++++++ 2 files changed, 147 insertions(+), 0 deletions(-) diff --git a/src/superio/smsc/lpc47n207/early_serial.c b/src/superio/smsc/lpc47n207/early_serial.c new file mode 100644 index 0000000..41e1b10 --- /dev/null +++ b/src/superio/smsc/lpc47n207/early_serial.c @@ -0,0 +1,122 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * This code tries to discover the SMSC LPC47N207 superio chip which can be + * connected over an LPC dongle. The chip could be bootstrap mapped to one of + * four LPC addresses: 0x2e, 0x4e, 0x162e, and 0x164e. + * + * Initializing the UART requires accesses to a few control registers. This + * structure includes the register offset and the value to write (along with + * the mask). + */ +typedef struct { + u8 conf_reg; + u8 value; + u8 mask; +} uart_conf; + +/* All regs/values to write to initialize the LPC47N207 UART */ +static const uart_conf uart_conf_data [] = { + {2, (1 << 3), (1 << 3)}, /* cr02, enable Primary UART power */ + {0xc, (1 << 6), (1 << 6)}, /* cr0c, enable Primary UART high speed */ + {0x24, (CONFIG_TTYS0_BASE >> 3) << 1, 0xff}, /* cr24, base addr */ +}; + +void try_enabling_LPC47N207_uart(void) +{ + device_t dev = PCH_LPC_DEV; + u16 saved_basic_config; + u16 saved_extended_config; + u8 reg_value; + const uart_conf* conf_item; + u16 lpc_ports[] = {0x2e, 0x4e, 0x162e, 0x164e}; + u16 lpc_port; + int i, j; + + /* preserve the LPC controller conffguration */ + saved_basic_config = pci_read_config16(dev, LPC_EN); + saved_extended_config = pci_read_config32(dev, LPC_GEN1_DEC); + + /* enable COMA mapping and all possible LPC addresses of 47N207 */ + pci_write_config16(dev, LPC_EN, + saved_basic_config | + CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN); + + /* map full 256 bytes at 0x1600 to the LPC bus */ + pci_write_config32(dev, LPC_GEN1_DEC, 0xfc1601); + + /* Set COM1/COM2 decode range */ + pci_write_config16(dev, LPC_IO_DEC, 0x0010); + +#define CONFIG_ENABLE 0x55 +#define CONFIG_DISABLE 0xaa + + for (j = 0; j < ARRAY_SIZE(lpc_ports); j++) { + lpc_port = lpc_ports[j]; + + /* enable CONFIG mode */ + outb(CONFIG_ENABLE, lpc_port); + reg_value=inb(lpc_port); + if (reg_value != CONFIG_ENABLE) { + continue; /* There is no LPC device at this address */ + } + + do { + /* + * Registers 12 and 13 hold config address, look for a + * match. + */ + outb(0x12, lpc_port); + reg_value=inb(lpc_port + 1); + if (reg_value != (lpc_port & 0xff)) + break; + + outb(0x13, lpc_port); + reg_value=inb(lpc_port + 1); + if (reg_value != (lpc_port >> 8)) + break; + + /* This must be the SMSC LPC 47N207, enable the UART. */ + for (i = 0; i < ARRAY_SIZE(uart_conf_data); i++) { + u8 reg, value, mask; + + conf_item = uart_conf_data + i; + + reg = conf_item->conf_reg; + value = conf_item->value; + mask = conf_item->mask; + + outb(reg, lpc_port); + reg_value = inb(lpc_port + 1); + reg_value &= ~mask; + reg_value |= (value & mask); + outb(reg_value, lpc_port + 1); + } + /* Keep COMA UART enable bit on */ + saved_basic_config |= COMA_LPC_EN; + } while (0); + outb(CONFIG_DISABLE, lpc_port); + } + + /* Restore PCH config state. */ + pci_write_config16(dev, LPC_EN, saved_basic_config); + pci_write_config32(dev, LPC_GEN1_DEC, saved_extended_config); + +} diff --git a/src/superio/smsc/lpc47n207/lpc47n207.h b/src/superio/smsc/lpc47n207/lpc47n207.h new file mode 100644 index 0000000..69689a4 --- /dev/null +++ b/src/superio/smsc/lpc47n207/lpc47n207.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_SMSC_LPC47N207_LPC47N207_H +#define SUPERIO_SMSC_LPC47N207_LPC47N207_H + +extern void try_enabling_LPC47N207_uart(void); + +#endif

1 0

New patch to review for coreboot: e64d0f0 Add support for ITE IT8772F SuperI/O chip
by Stefan Reinauer 31 Mar '12

31 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/822 -gerrit commit e64d0f030058c17549a2e5f5150612b69a2a02ab Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Mar 30 15:04:07 2012 -0700 Add support for ITE IT8772F SuperI/O chip Change-Id: I8e80c22eb0f3cb68f2457be6b2e7894df60ed632 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/superio/ite/Kconfig | 2 + src/superio/ite/Makefile.inc | 1 + src/superio/ite/it8772f/Makefile.inc | 21 ++ src/superio/ite/it8772f/acpi/superio.asl | 299 ++++++++++++++++++++++++++++++ src/superio/ite/it8772f/chip.h | 57 ++++++ src/superio/ite/it8772f/early_serial.c | 131 +++++++++++++ src/superio/ite/it8772f/it8772f.h | 120 ++++++++++++ src/superio/ite/it8772f/superio.c | 250 +++++++++++++++++++++++++ 8 files changed, 881 insertions(+), 0 deletions(-) diff --git a/src/superio/ite/Kconfig b/src/superio/ite/Kconfig index d045bf4..5d92a96 100644 --- a/src/superio/ite/Kconfig +++ b/src/superio/ite/Kconfig @@ -38,3 +38,5 @@ config SUPERIO_ITE_IT8718F bool config SUPERIO_ITE_IT8721F bool +config SUPERIO_ITE_IT8772F + bool diff --git a/src/superio/ite/Makefile.inc b/src/superio/ite/Makefile.inc index 1e734fe..fa44ff8 100644 --- a/src/superio/ite/Makefile.inc +++ b/src/superio/ite/Makefile.inc @@ -25,3 +25,4 @@ subdirs-y += it8712f subdirs-y += it8716f subdirs-y += it8718f subdirs-y += it8721f +subdirs-y += it8772f diff --git a/src/superio/ite/it8772f/Makefile.inc b/src/superio/ite/it8772f/Makefile.inc new file mode 100644 index 0000000..d001c61 --- /dev/null +++ b/src/superio/ite/it8772f/Makefile.inc @@ -0,0 +1,21 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +ramstage-$(CONFIG_SUPERIO_ITE_IT8772F) += superio.c diff --git a/src/superio/ite/it8772f/acpi/superio.asl b/src/superio/ite/it8772f/acpi/superio.asl new file mode 100644 index 0000000..5bb45fa --- /dev/null +++ b/src/superio/ite/it8772f/acpi/superio.asl @@ -0,0 +1,299 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Scope is \_SB.PCI0.LPCB + +Device (SIO) { + Name (_ADR, 0x2E) + OperationRegion (SIOA, SystemIO, 0x2E, 0x02) + Field (SIOA, ByteAcc, NoLock, Preserve) + { + SI2E, 8, + SI2F, 8, + } + + IndexField (SI2E, SI2F, ByteAcc, NoLock, Preserve) + { + Offset (0x02), + SCNT, 8, /* Configure Control */ + Offset (0x07), + SLDN, 8, /* Logical Device Number */ + Offset (0x30), + SACT, 8, /* Activate */ + Offset (0x60), + IO0H, 8, /* Base Address 0 MSB */ + IO0L, 8, /* Base Address 0 LSB */ + Offset (0x62), + IO1H, 8, /* Base Address 1 MSB */ + IO1L, 8, /* Base Address 1 LSB */ + Offset (0x70), + IQ00, 8, /* Interrupt Select */ + } + + Name (SFDC, 0) /* Floppy Disk Controller */ + Name (SSP1, 1) /* Serial Port 1 */ + Name (SENV, 4) /* Environment Controller */ + Name (SKBC, 5) /* Keyboard */ + Name (SKBM, 6) /* Mouse */ + Name (SGPI, 7) /* GPIO */ + Name (SINF, 10) /* Consumer IR */ + + Method (ENTR, 0, NotSerialized) + { + Store (0x87, SI2E) + Store (0x01, SI2E) + Store (0x55, SI2E) + Store (0x55, SI2E) + } + + Method (EXIT, 0, NotSerialized) + { + Store (0x02, SCNT) + } + + /* Parse activate register for an LDN */ + Method (ISEN, 1, NotSerialized) + { + ENTR () + Store (Arg0, SLDN) + Store (SACT, Local0) + EXIT () + + /* Check if it exists */ + If (LEqual (Local0, 0xFF)) + { + Return (0x00) + } + + /* Check if activated */ + If (LEqual (Local0, One)) + { + Return (0x0F) + } + Else + { + Return (0x0D) + } + } + + /* Enable an LDN via the activate register */ + Method (SENA, 1, NotSerialized) + { + ENTR () + Store (Arg0, SLDN) + Store (One, SACT) + EXIT () + } + + /* Disable an LDN via the activate register */ + Method (SDIS, 1, NotSerialized) + { + ENTR () + Store (Arg0, SLDN) + Store (Zero, SACT) + EXIT () + } + +#ifdef SIO_ENABLE_ENVC + Device (ENVC) { + Name (_HID, EISAID ("PNP0C02")) + Name (_UID, 10) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (SENV)) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, SIO_ENVC_IO0, SIO_ENVC_IO0, 0x08, 0x08) + IO (Decode16, SIO_ENVC_IO1, SIO_ENVC_IO1, 0x04, 0x04) + }) + + Name (_PRS, ResourceTemplate () + { + IO (Decode16, SIO_ENVC_IO0, SIO_ENVC_IO0, 0x08, 0x08) + IO (Decode16, SIO_ENVC_IO1, SIO_ENVC_IO1, 0x04, 0x04) + }) + + OperationRegion (ECAP, SystemIO, SIO_ENVC_IO0, 0x07) + Field (ECAP, ByteAcc, NoLock, Preserve) + { + Offset (0x05), + ECAI, 8, // Address Index Register + ECAD, 8, // Address Data Register + } + + // Registers for thermal zone implementations + IndexField (ECAI, ECAD, ByteAcc, NoLock, Preserve) + { + Offset (0x29), + TIN1, 8, // TMPIN1 Reading + TIN2, 8, // TMPIN2 Reading + TIN3, 8, // TMPIN3 Reading + Offset (0x6b), + F2PS, 8, // FAN2 PWM Setting + Offset (0x73), + F3PS, 8, // FAN3 PWM Setting + } + } +#endif + +#ifdef SIO_ENABLE_GPIO + Device (GPIO) { + Name (_HID, EISAID ("PNP0C02")) + Name (_UID, 11) + + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, SIO_GPIO_IO0, SIO_GPIO_IO0, 0x01, 0x01) + IO (Decode16, SIO_GPIO_IO1, SIO_GPIO_IO1, 0x08, 0x08) + }) + + Name (_PRS, ResourceTemplate () + { + IO (Decode16, SIO_GPIO_IO0, SIO_GPIO_IO0, 0x01, 0x01) + IO (Decode16, SIO_GPIO_IO1, SIO_GPIO_IO1, 0x08, 0x08) + }) + } +#endif + +#ifdef SIO_ENABLE_COM1 + Device (COM1) { + Name (_HID, EISAID ("PNP0501")) + Name (_UID, 1) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (SSP1)) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08) + IRQNoFlags () {4} + }) + + Name (_PRS, ResourceTemplate () + { + IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08) + IRQNoFlags () {4} + }) + } +#endif + +#ifdef SIO_ENABLE_PS2K + Device (PS2K) // Keyboard + { + Name (_HID, EISAID("PNP0303")) + Name (_CID, EISAID("PNP030B")) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (SKBC)) + } + + Name (_CRS, ResourceTemplate() + { + IO (Decode16, 0x60, 0x60, 0x01, 0x01) + IO (Decode16, 0x64, 0x64, 0x01, 0x01) + IRQNoFlags () {1} + }) + + Name (_PRS, ResourceTemplate() + { + IO (Decode16, 0x60, 0x60, 0x01, 0x01) + IO (Decode16, 0x64, 0x64, 0x01, 0x01) + IRQNoFlags () {1} + }) + } +#endif + +#ifdef SIO_ENABLE_PS2M + Device (PS2M) // Mouse + { + Name (_HID, EISAID("PNP0F13")) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (SKBM)) + } + + Name (_CRS, ResourceTemplate() + { + IRQNoFlags () {12} + }) + + Name (_PRS, ResourceTemplate() + { + IRQNoFlags () {12} + }) + } +#endif + +#ifdef SIO_ENABLE_FDC0 + Device (FDC0) // Floppy controller + { + Name (_HID, EISAID ("PNP0700")) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (SFDC)) + } + + Name (_CRS, ResourceTemplate() + { + IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06) + IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01) + IRQNoFlags () {6} + DMA (Compatibility, NotBusMaster, Transfer8) {2} + }) + + Name (_PRS, ResourceTemplate() + { + IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06) + IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01) + IRQNoFlags () {6} + DMA (Compatibility, NotBusMaster, Transfer8) {2} + }) + } +#endif + +#ifdef SIO_ENABLE_INFR + Device (INFR) // Infrared controller + { + Name (_HID, EISAID ("PNP0510")) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (SINF)) + } + + Name (_CRS, ResourceTemplate() + { + IO (Decode16, SIO_INFR_IO0, SIO_INFR_IO0, 0x08, 0x08) + IRQNoFlags () { SIO_INFR_IRQ } + }) + + Name (_PRS, ResourceTemplate() + { + IO (Decode16, SIO_INFR_IO0, SIO_INFR_IO0, 0x08, 0x08) + IRQNoFlags () { SIO_INFR_IRQ } + }) + } +#endif +} diff --git a/src/superio/ite/it8772f/chip.h b/src/superio/ite/it8772f/chip.h new file mode 100644 index 0000000..e91f6fa --- /dev/null +++ b/src/superio/ite/it8772f/chip.h @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_ITE_IT8772F_CHIP_H +#define SUPERIO_ITE_IT8772F_CHIP_H + +#include <device/device.h> +#include <pc80/keyboard.h> +#include <uart8250.h> + +extern struct chip_operations superio_ite_it8772f_ops; + +struct superio_ite_it8772f_config { + struct pc_keyboard keyboard; + + /* GPIO SimpleIO register values via devicetree.cb */ + u8 gpio_set1; + u8 gpio_set2; + u8 gpio_set3; + u8 gpio_set4; + u8 gpio_set5; + u8 gpio_set6; + + u8 skip_keyboard; + + /* + * Enable external temperature sensor to use PECI GetTemp() + * command and store in register TMPIN 1, 2, or 3. + */ + u8 peci_tmpin; + + /* + * Enable a FAN for sofware control. + */ + u8 fan1_enable; + u8 fan2_enable; + u8 fan3_enable; +}; + +#endif diff --git a/src/superio/ite/it8772f/early_serial.c b/src/superio/ite/it8772f/early_serial.c new file mode 100644 index 0000000..0721060 --- /dev/null +++ b/src/superio/ite/it8772f/early_serial.c @@ -0,0 +1,131 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/romcc_io.h> +#include <device/pnp_def.h> +#include "it8772f.h" + +/* The base address is 0x2e or 0x4e, depending on config bytes. */ +#define SIO_BASE IT8772F_BASE +#define SIO_INDEX SIO_BASE +#define SIO_DATA (SIO_BASE + 1) + +/* Global configuration registers. */ +#define IT8772F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ +#define IT8772F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ +#define IT8772F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ +#define IT8772F_CONFIG_REG_MFC 0x2a /* Multi-function control */ +#define IT8772F_CONFIG_REG_WATCHDOG 0x72 /* Watchdog control. */ + +u8 it8772f_sio_read(u8 index) +{ + outb(index, SIO_BASE); + return inb(SIO_DATA); +} + +void it8772f_sio_write(u8 index, u8 value) +{ + outb(index, SIO_BASE); + outb(value, SIO_DATA); +} + +static void it8772f_enter_conf(void) +{ + u16 port = SIO_BASE; + + outb(0x87, port); + outb(0x01, port); + outb(0x55, port); + outb((port == 0x4e) ? 0xaa : 0x55, port); +} + +static void it8772f_exit_conf(void) +{ + it8772f_sio_write(IT8772F_CONFIG_REG_CC, 0x02); +} + +/* Select 24MHz CLKIN (48MHz is the default). */ +void it8772f_24mhz_clkin(void) +{ + it8772f_enter_conf(); + it8772f_sio_write(IT8772F_CONFIG_REG_LDN, 0x00); + it8772f_sio_write(IT8772F_CONFIG_REG_CLOCKSEL, 0x1); + it8772f_exit_conf(); +} + +/* + * LDN 7, reg 0x2a - needed for S3, or memory power will be cut off. + * + * Enable 3VSBSW#. (For System Suspend-to-RAM) + * 0: 3VSBSW# will be always inactive. + * 1: 3VSBSW# enabled. It will be (NOT SUSB#) NAND SUSC#. + */ +void it8772f_enable_3vsbsw(void) +{ + it8772f_enter_conf(); + it8772f_sio_write(IT8772F_CONFIG_REG_LDN, IT8772F_GPIO); + it8772f_sio_write(IT8772F_CONFIG_REG_MFC, 0x80); + it8772f_exit_conf(); +} + +void it8772f_kill_watchdog(void) +{ + it8772f_enter_conf(); + it8772f_sio_write(IT8772F_CONFIG_REG_LDN, IT8772F_GPIO); + it8772f_sio_write(IT8772F_CONFIG_REG_WATCHDOG, 0x00); + it8772f_exit_conf(); +} + +/* Enable the serial port(s). */ +void it8772f_enable_serial(device_t dev, u16 iobase) +{ + it8772f_enter_conf(); + it8772f_sio_write(IT8772F_CONFIG_REG_LDN, dev & 0xff); + it8772f_sio_write(PNP_IDX_IO0, (iobase >> 8) & 0xff); + it8772f_sio_write(PNP_IDX_IO0+1, iobase & 0xff); + it8772f_sio_write(PNP_IDX_EN, 1); + it8772f_exit_conf(); +} + +/* Set AC resume to be up to the Southbridge */ +void it8772f_ac_resume_southbridge(void) +{ + it8772f_enter_conf(); + it8772f_sio_write(IT8772F_CONFIG_REG_LDN, IT8772F_EC); + it8772f_sio_write(0xf4, 0x60); + it8772f_exit_conf(); +} + +/* Configure a set of GPIOs */ +void it8772f_gpio_setup(int set, u8 select, u8 polarity, u8 pullup, + u8 output, u8 enable) +{ + set--; /* Set 1 is offset 0 */ + it8772f_enter_conf(); + it8772f_sio_write(IT8772F_CONFIG_REG_LDN, IT8772F_GPIO); + if (set < 5) { + it8772f_sio_write(GPIO_REG_SELECT(set), select); + it8772f_sio_write(GPIO_REG_ENABLE(set), enable); + it8772f_sio_write(GPIO_REG_POLARITY(set), polarity); + } + it8772f_sio_write(GPIO_REG_OUTPUT(set), output); + it8772f_sio_write(GPIO_REG_PULLUP(set), pullup); + it8772f_exit_conf(); +} diff --git a/src/superio/ite/it8772f/it8772f.h b/src/superio/ite/it8772f/it8772f.h new file mode 100644 index 0000000..1ec82e1 --- /dev/null +++ b/src/superio/ite/it8772f/it8772f.h @@ -0,0 +1,120 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_ITE_IT8772F_IT8772F_H +#define SUPERIO_ITE_IT8772F_IT8772F_H + +#define IT8772F_BASE 0x2e + +#define IT8772F_FDC 0x00 /* Floppy disk controller */ +#define IT8772F_SP1 0x01 /* Com1 */ +#define IT8772F_EC 0x04 /* Environment controller */ +#define IT8772F_KBCK 0x05 /* Keyboard */ +#define IT8772F_KBCM 0x06 /* Mouse */ +#define IT8772F_GPIO 0x07 /* GPIO */ +#define IT8772F_IR 0x0a /* Consumer IR */ + +/* Environmental Controller interface */ +#define IT8772F_INTERFACE_SELECT 0x0a +#define IT8772F_INTERFACE_PSEUDO_EOC (1 << 7) +#define IT8772F_INTERFACE_SMB_ENABLE (1 << 6) +#define IT8772F_INTERFACE_SEL_DISABLE (0 << 4) +#define IT8772F_INTERFACE_SEL_SST_SLAVE (1 << 4) +#define IT8772F_INTERFACE_SEL_PECI (2 << 4) +#define IT8772F_INTERFACE_SEL_SST_HOST (3 << 4) +#define IT8772F_INTERFACE_CLOCK_32MHZ (0 << 3) +#define IT8772F_INTERFACE_CLOCK_24MHZ (1 << 3) +#define IT8772F_INTERFACE_SPEED_TOLERANCE (1 << 2) +#define IT8772F_INTERFACE_PECI_AWFCS (1 << 0) +#define IT8772F_FAN_TAC2_READ 0x0e +#define IT8772F_FAN_TAC3_READ 0x0f +#define IT8772F_FAN_MAIN_CTL 0x13 +#define IT8772F_FAN_MAIN_CTL_TAC_SMART(x) (1 << ((x)-1)) +#define IT8772F_FAN_MAIN_CTL_TAC_EN(x) (1 << ((x)+3)) +#define IT8772F_FAN_CTL_MODE 0x14 +#define IT8772F_FAN_CTL_ON(x) (1 << ((x)-1)) +#define IT8772F_FAN_PWM_MIN_DUTY (1 << 3) +#define IT8772F_FAN_PWM_CLOCK_48MHZ (0 << 4) +#define IT8772F_FAN_PWM_CLOCK_24MHZ (1 << 4) +#define IT8772F_FAN_PWM_CLOCK_8MHZ (3 << 4) +#define IT8772F_FAN_PWM_CLOCK_6MHZ (4 << 4) +#define IT8772F_FAN_PWM_CLOCK_3MHZ (5 << 4) +#define IT8772F_FAN_PWM_CLOCK_1_5MHZ (6 << 4) +#define IT8772F_FAN_PWM_CLOCK_51KHZ (7 << 4) +#define IT8772F_FAN_CTL_POLARITY_LOW (0 << 7) +#define IT8772F_FAN_CTL_POLARITY_HIGH (1 << 7) +#define IT8772F_FAN_CTL2_PWM_MODE 0x16 +#define IT8772F_FAN_CTL3_PWM_MODE 0x17 +#define IT8772F_FAN_CTL_PWM_MODE_SOFTWARE (0 << 7) +#define IT8772F_FAN_CTL_PWM_MODE_AUTOMATIC (1 << 7) +#define IT8772F_ADC_TEMP_CHANNEL_ENABLE 0x51 +#define IT8772F_FAN_CTL2_PWM_START 0x6b +#define IT8772F_FAN_CTL2_AUTO_MODE 0x6c +#define IT8772F_FAN_CTL3_PWM_START 0x73 +#define IT8772F_FAN_CTL3_AUTO_MODE 0x74 +#define IT8772F_FAN_CTL_AUTO_SMOOTHING_DIS (0 << 7) +#define IT8772F_FAN_CTL_AUTO_SMOOTHING_EN (1 << 7) +#define IT8772F_EXTEMP_STATUS 0x88 +#define IT8772F_EXTEMP_ADDRESS 0x89 +#define IT8772F_EXTEMP_WRITE_LENGTH 0x8a +#define IT8772F_EXTEMP_READ_LENGTH 0x8b +#define IT8772F_EXTEMP_COMMAND 0x8c +#define IT8772F_EXTEMP_WRITE_DATA_2 0x8d +#define IT8772F_EXTEMP_CONTROL 0x8e +#define IT8772F_EXTEMP_CONTROL_AUTO_32HZ (0 << 6) +#define IT8772F_EXTEMP_CONTROL_AUTO_16HZ (1 << 6) +#define IT8772F_EXTEMP_CONTROL_AUTO_8HZ (2 << 6) +#define IT8772F_EXTEMP_CONTROL_AUTO_4HZ (3 << 6) +#define IT8772F_EXTEMP_CONTROL_AUTO_START (1 << 5) +#define IT8772F_EXTEMP_CONTROL_AUTO_ABORT (1 << 4) +#define IT8772F_EXTEMP_CONTROL_AUTO_TWO_DOMAIN (1 << 3) +#define IT8772F_EXTEMP_CONTROL_CONTENTION (1 << 2) +#define IT8772F_EXTEMP_CONTROL_SST_IDLE_HIGH (1 << 1) +#define IT8772F_EXTEMP_CONTROL_START (1 << 0) + +/* Standard PECI GetTemp */ +#define PECI_CLIENT_ADDRESS 0x30 +#define PECI_GETTEMP_COMMAND 0x01 +#define PECI_GETTEMP_WRITE_LENGTH 0x01 +#define PECI_GETTEMP_READ_LENGTH 0x02 + +/* GPIO interface */ +#define IT8772F_GPIO_LED_BLINK1_PINMAP 0xf8 +#define IT8772F_GPIO_LED_BLINK1_CONTROL 0xf9 + +#define GPIO_REG_SELECT(x) (0x25 + (x)) +#define GPIO_REG_POLARITY(x) (0xb0 + (x)) +#define GPIO_REG_PULLUP(x) (0xb8 + (x)) +#define GPIO_REG_ENABLE(x) (0xc0 + (x)) +#define GPIO_REG_OUTPUT(x) (0xc8 + (x)) + +#ifndef __ROMCC__ +u8 it8772f_sio_read(u8 index); +void it8772f_sio_write(u8 index, u8 value); +void it8772f_enable_serial(device_t dev, u16 iobase); +void it8772f_kill_watchdog(void); +void it8772f_24mhz_clkin(void); +void it8772f_enable_3vsbsw(void); +void it8772f_ac_resume_southbridge(void); +void it8772f_gpio_setup(int set, u8 func_select, u8 polarity, u8 pullup, + u8 output, u8 enable); +#endif + +#endif diff --git a/src/superio/ite/it8772f/superio.c b/src/superio/ite/it8772f/superio.c new file mode 100644 index 0000000..1361ef2 --- /dev/null +++ b/src/superio/ite/it8772f/superio.c @@ -0,0 +1,250 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include <device/pnp.h> +#include <uart8250.h> +#include <pc80/keyboard.h> +#include <arch/io.h> +#include <stdlib.h> +#include "chip.h" +#include "it8772f.h" + +static void pnp_enter_ext_func_mode(device_t dev) +{ + u16 port = dev->path.pnp.port; + + outb(0x87, port); + outb(0x01, port); + outb(0x55, port); + outb((port == 0x4e) ? 0xaa : 0x55, port); +} + +static void pnp_exit_ext_func_mode(device_t dev) +{ + pnp_write_config(dev, 0x02, 0x02); +} + +static inline u8 it8772f_envc_read(struct resource *res, u8 addr) +{ + outb(addr, res->base + 5); + return inb(res->base + 6); +} + +static inline void it8772f_envc_write(struct resource *res, u8 addr, u8 value) +{ + outb(addr, res->base + 5); + outb(value, res->base + 6); +} + +/* + * Setup External Temperature to read via PECI into TMPINx register + */ +static void it8772f_enable_peci(struct resource *res, int tmpin) +{ + if (tmpin < 1 || tmpin > 3) + return; + + /* Enable PECI interface */ + it8772f_envc_write(res, IT8772F_INTERFACE_SELECT, + IT8772F_INTERFACE_SEL_PECI | + IT8772F_INTERFACE_SPEED_TOLERANCE); + + /* Setup External Temperature using PECI GetTemp */ + it8772f_envc_write(res, IT8772F_EXTEMP_ADDRESS, + PECI_CLIENT_ADDRESS); + it8772f_envc_write(res, IT8772F_EXTEMP_COMMAND, + PECI_GETTEMP_COMMAND); + it8772f_envc_write(res, IT8772F_EXTEMP_WRITE_LENGTH, + PECI_GETTEMP_WRITE_LENGTH); + it8772f_envc_write(res, IT8772F_EXTEMP_READ_LENGTH, + PECI_GETTEMP_READ_LENGTH); + it8772f_envc_write(res, IT8772F_EXTEMP_CONTROL, + IT8772F_EXTEMP_CONTROL_AUTO_4HZ | + IT8772F_EXTEMP_CONTROL_AUTO_START); + + /* External Temperature reported in TMPINx register */ + it8772f_envc_write(res, IT8772F_ADC_TEMP_CHANNEL_ENABLE, + (tmpin & 3) << 6); +} + +/* + * Setup a FAN PWM interface for software control + */ +static void it8772f_enable_fan(struct resource *res, int fan) +{ + u8 reg; + + if (fan < 1 || fan > 3) + return; + + /* Enable 6MHz (23.43kHz PWM) active high output */ + reg = it8772f_envc_read(res, IT8772F_FAN_CTL_MODE); + reg |= IT8772F_FAN_CTL_ON(fan) | + IT8772F_FAN_PWM_CLOCK_6MHZ | + IT8772F_FAN_CTL_POLARITY_HIGH; + it8772f_envc_write(res, IT8772F_FAN_CTL_MODE, reg); + + /* Enable output in smart mode */ + reg = it8772f_envc_read(res, IT8772F_FAN_MAIN_CTL); + reg |= IT8772F_FAN_MAIN_CTL_TAC_SMART(fan); + reg |= IT8772F_FAN_MAIN_CTL_TAC_EN(fan); + it8772f_envc_write(res, IT8772F_FAN_MAIN_CTL, reg); + + switch (fan) { + case 2: + /* Enable software operation */ + it8772f_envc_write(res, IT8772F_FAN_CTL2_PWM_MODE, + IT8772F_FAN_CTL_PWM_MODE_SOFTWARE); + /* Disable Smoothing */ + it8772f_envc_write(res, IT8772F_FAN_CTL2_AUTO_MODE, + IT8772F_FAN_CTL_AUTO_SMOOTHING_DIS); + /* Set a default medium fan speed */ + it8772f_envc_write(res, IT8772F_FAN_CTL2_PWM_START, 0x80); + break; + case 3: + /* Enable software operation */ + it8772f_envc_write(res, IT8772F_FAN_CTL3_PWM_MODE, + IT8772F_FAN_CTL_PWM_MODE_SOFTWARE); + /* Disable Smoothing */ + it8772f_envc_write(res, IT8772F_FAN_CTL3_AUTO_MODE, + IT8772F_FAN_CTL_AUTO_SMOOTHING_DIS); + /* Set a default medium fan speed */ + it8772f_envc_write(res, IT8772F_FAN_CTL3_PWM_START, 0x80); + break; + } +} + +static void it8772f_init(device_t dev) +{ + struct superio_ite_it8772f_config *conf = dev->chip_info; + struct resource *res; + + if (!dev->enabled) + return; + + switch (dev->path.pnp.device) { + case IT8772F_EC: + res = find_resource(dev, PNP_IDX_IO0); + if (!res) + break; + + /* Enable PECI if configured */ + it8772f_enable_peci(res, conf->peci_tmpin); + + /* Enable FANx if configured */ + if (conf->fan1_enable) + it8772f_enable_fan(res, 1); + if (conf->fan2_enable) + it8772f_enable_fan(res, 2); + if (conf->fan3_enable) + it8772f_enable_fan(res, 3); + break; + case IT8772F_GPIO: + /* Set GPIO output levels */ + res = find_resource(dev, PNP_IDX_IO1); + if (res) { + if (conf->gpio_set1) + outb(conf->gpio_set1, res->base + 0); + if (conf->gpio_set2) + outb(conf->gpio_set2, res->base + 1); + if (conf->gpio_set3) + outb(conf->gpio_set3, res->base + 2); + if (conf->gpio_set4) + outb(conf->gpio_set4, res->base + 3); + if (conf->gpio_set5) + outb(conf->gpio_set5, res->base + 4); + if (conf->gpio_set6) + outb(conf->gpio_set6, res->base + 5); + } + break; + case IT8772F_KBCK: + if (!conf->skip_keyboard) { + set_kbc_ps2_mode(); + pc_keyboard_init(&conf->keyboard); + } + break; + case IT8772F_KBCM: + break; + case IT8772F_IR: + break; + } +} + +static void it8772f_pnp_set_resources(device_t dev) +{ + pnp_enter_ext_func_mode(dev); + pnp_set_resources(dev); + pnp_exit_ext_func_mode(dev); +} + +static void it8772f_pnp_enable_resources(device_t dev) +{ + pnp_enter_ext_func_mode(dev); + pnp_enable_resources(dev); + pnp_exit_ext_func_mode(dev); +} + +static void it8772f_pnp_enable(device_t dev) +{ + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, !!dev->enabled); + pnp_exit_ext_func_mode(dev); +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = it8772f_pnp_set_resources, + .enable_resources = it8772f_pnp_enable_resources, + .enable = it8772f_pnp_enable, + .init = it8772f_init, +}; + +static struct pnp_info pnp_dev_info[] = { + /* Floppy Disk Controller */ + { &ops, IT8772F_FDC, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, + /* Serial Port 1 */ + { &ops, IT8772F_SP1, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, + /* Environmental Controller */ + { &ops, IT8772F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, + {0x0ff8, 0}, {0x0ffc, 4}, }, + /* KBC Keyboard */ + { &ops, IT8772F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, + {0x0fff, 0}, {0x0fff, 4}, }, + /* KBC Mouse */ + { &ops, IT8772F_KBCM, PNP_IRQ0, }, + /* 27 GPIOs */ + { &ops, IT8772F_GPIO, PNP_IO0 | PNP_IO1, + {0x0fff, 0}, {0x0ff8, 0}, }, + /* Infrared */ + { &ops, IT8772F_IR, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &pnp_ops, + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_ite_it8772f_ops = { + CHIP_NAME("ITE IT8772F Super I/O") + .enable_dev = enable_dev, +};

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New patch to review for coreboot: ea119cc Add a helper function to determine the number of enabled CPUs
by Stefan Reinauer 31 Mar '12

31 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/821 -gerrit commit ea119ccdfd79f8373abf1b0b2717718e5d97d05d Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Mar 30 13:52:58 2012 -0700 Add a helper function to determine the number of enabled CPUs Change-Id: Ia72926002571e0f250849fa5db048bd8b2e92400 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- src/devices/device_util.c | 18 ++++++++++++++++++ src/include/device/device.h | 1 + 2 files changed, 19 insertions(+), 0 deletions(-) diff --git a/src/devices/device_util.c b/src/devices/device_util.c index 526490a..5225938 100644 --- a/src/devices/device_util.c +++ b/src/devices/device_util.c @@ -850,3 +850,21 @@ u32 find_pci_tolm(struct bus *bus) return tolm; } + +/* Count of enabled CPUs */ +int dev_count_cpu(void) +{ + device_t cpu; + int count = 0; + + for (cpu = all_devices; cpu; cpu = cpu->next) { + if ((cpu->path.type != DEVICE_PATH_APIC) || + (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) + continue; + if (!cpu->enabled) + continue; + count++; + } + + return count; +} diff --git a/src/include/device/device.h b/src/include/device/device.h index c097f57..0aea1d6 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -133,6 +133,7 @@ device_t dev_find_class (unsigned int class, device_t from); device_t dev_find_slot (unsigned int bus, unsigned int devfn); device_t dev_find_slot_on_smbus (unsigned int bus, unsigned int addr); device_t dev_find_lapic(unsigned apic_id); +int dev_count_cpu(void); /* Debug functions */ void print_resource_tree(struct device * root, int debug_level,

1 0

New patch to review for coreboot: 4fd1c6e Align: Make sure 1 is treated as unsigned long instead of int
by Stefan Reinauer 31 Mar '12

31 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/820 -gerrit commit 4fd1c6e96c8aeb1ce49aaae053f72726e4c410e8 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Mar 30 13:00:46 2012 -0700 Align: Make sure 1 is treated as unsigned long instead of int Change-Id: Id79daaaa35c4d412c8c1f621a3638d129681d331 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/include/stdlib.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/include/stdlib.h b/src/include/stdlib.h index 45420d7..5465c14 100644 --- a/src/include/stdlib.h +++ b/src/include/stdlib.h @@ -5,7 +5,7 @@ #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) -#define ALIGN(x,a) __ALIGN_MASK(x,(typeof(x))(a)-1) +#define ALIGN(x,a) __ALIGN_MASK(x,(typeof(x))(a)-1UL) #define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) #define MIN(a,b) ((a) < (b) ? (a) : (b))

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coreboot March 2012