coreboot March 2012

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Patch merged into coreboot/master: 5fc1b63 Intel cpus: get MAXPHYADDR at runtime for new CAR
by gerrit＠coreboot.org 31 Mar '12

31 Mar '12

the following patch was just integrated into master: commit 5fc1b63e0baa583b2012569ee8574fbf1dc5943b Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 28 02:06:45 2012 +0200 Intel cpus: get MAXPHYADDR at runtime for new CAR Use CPUID to get MAXPHYADDR and set MTRR masks correctly. Also only BSP CPU clears MTRRs and initializes its Local APIC. Change-Id: I89ee765a17ec7c041284ed402f21d9a969d699bd Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Sat Mar 31 12:03:35 2012, giving +2 See http://review.coreboot.org/686 for details. -gerrit

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Patch merged into coreboot/master: 217afa9 Intel cpus: add hyper-threading CPU support to new CAR
by gerrit＠coreboot.org 31 Mar '12

31 Mar '12

the following patch was just integrated into master: commit 217afa9f388738bbb43e80cd631115973b438ce1 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 28 02:02:27 2012 +0200 Intel cpus: add hyper-threading CPU support to new CAR This improvement of CAR code starts the sibling CPU processors and clears their cache disable bits (CR0.CD) in case a hyper-threading CPU is detected. Change-Id: Ieabb86a7c47afb3e178cc75bb89dee3efe0c3d18 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/604 for details. -gerrit

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Patch merged into coreboot/master: 6b350da Intel cpus: improve CPU compatibility of new CAR
by gerrit＠coreboot.org 31 Mar '12

31 Mar '12

the following patch was just integrated into master: commit 6b350da4fd2a1f504340fdeed75c2b916220fab1 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Feb 16 23:12:04 2012 +0200 Intel cpus: improve CPU compatibility of new CAR Most or many Xeons have no MSR 0x11e. I have previously tested that a HT-enabled P4 (model f25) can execute this but will not have cache-as-ram enabled. Should work for non-HT P4. Change-Id: I28cbfa68858df45a69aa0d5b050cd829d070ad66 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/644 for details. -gerrit

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Patch merged into coreboot/master: ed37431 Add support for RAM-less multi-processor init
by gerrit＠coreboot.org 31 Mar '12

31 Mar '12

the following patch was just integrated into master: commit ed3743123e4f832be6761a9b550cab5cc8a3f934 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 14 10:39:17 2012 +0200 Add support for RAM-less multi-processor init For a hyper-threading processor, enabling cache requires that both the BSP and AP CPU clear CR0.CD (Cache Disable) bit. For a Cache-As-Ram implementation, partial multi-processor initialisation precedes raminit and AP CPUs' 16bit entry must be run from ROM. The AP CPU can only start execute real-mode code at a 4kB aligned address below 1MB. The protected mode entry code for AP is identical with the BSP code, which is already located at the top of bootblock. This patch takes the simplest approach and aligns the bootblock 16 bit entry at highest possible 4kB boundary below 1MB. The symbol ap_sipi_vector is tested to match CONFIG_AP_SIPI_VECTOR used by the CAR code in romstage. Adress is not expected to ever change, but if it does, link will fail. Change-Id: I82e4edbf208c9ba863f51a64e50cd92871c528ef Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/454 for details. -gerrit

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Patch merged into coreboot/master: 33fd183 Intel cpus: apply some good programming practices in new CAR
by gerrit＠coreboot.org 31 Mar '12

31 Mar '12

the following patch was just integrated into master: commit 33fd183f1da7a734647fc876d607785990fc6d90 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 28 01:45:44 2012 +0200 Intel cpus: apply some good programming practices in new CAR Delete dead CAR code and whitespace fixes. Replace cryptic 32bit hex values with existing LAPIC definitions. Do not assume state of direction flag before "rep" instruction. Do not load immediate values on temporary registers when not needed. Parameter pushed on stack was not popped (or flushed) after returning from call. This is a sort-of memory leak if multiple call's are implemented the same way. Change-Id: Ibb93e889b3a0af87b89345c462e331881e78686a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/643 for details. -gerrit

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Patch merged into coreboot/master: 265da9b Intel cpus: cache actual size of the Flash ROM device
by gerrit＠coreboot.org 31 Mar '12

31 Mar '12

the following patch was just integrated into master: commit 265da9b2659d2e18bb59e6a99792492fac71bdc8 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 28 00:24:15 2012 +0200 Intel cpus: cache actual size of the Flash ROM device Cache was enabled for the last 4 MB below 4 GB when ramstage is loaded. This does not cover the case of a 8 MB Flash and could overlap with some system device placed at high memory. Use the actual device size for the cache region. Mainboard may override this with Kconfig CACHE_ROM_SIZE if necessary. Change-Id: I622223b1e2af0b3c1831f3570b74eacfde7189dc Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Sat Mar 31 11:54:01 2012, giving +2 See http://review.coreboot.org/641 for details. -gerrit

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Patch merged into coreboot/master: 7380dcf Intel cpus: copy model_6ex CAR code
by gerrit＠coreboot.org 31 Mar '12

31 Mar '12

the following patch was just integrated into master: commit 7380dcfbd652b16fbeafb484454f3dcbcabf80cc Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 28 00:15:30 2012 +0200 Intel cpus: copy model_6ex CAR code Copy model_6ex CAR as car/cache_as_ram_ht.inc to be extended with hyper-threading CPU support. Change-Id: I09619363e714b1ebf813932b0b22123c1d89010e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Sat Mar 31 11:50:35 2012, giving +2 See http://review.coreboot.org/606 for details. -gerrit

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Patch merged into coreboot/master: c81993b Makefile: rename romstage linking filenames
by gerrit＠coreboot.org 31 Mar '12

31 Mar '12

the following patch was just integrated into master: commit c81993b926372a1bcddc3c6c1666e789868fdd5a Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Mar 26 19:03:44 2012 +0300 Makefile: rename romstage linking filenames $(obj)/location.txt -> $(obj)/romstage/base_xip.txt $(obj)/romstage/link1st.ld -> $(obj)/romstage/link_null.ld $(obj)/romstage/link2nd.ld -> $(obj)/romstage/link_xip.ld Change-Id: I15cf29b13a846729f19ecefb21819c4e66681155 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Sat Mar 31 11:36:18 2012, giving +2 See http://review.coreboot.org/812 for details. -gerrit

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Patch merged into coreboot/master: bf34b57 Makefile: split romstage linking to separate rules
by gerrit＠coreboot.org 31 Mar '12

31 Mar '12

the following patch was just integrated into master: commit bf34b57ec47f525055157f4e5ec0f77c151ea2e4 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Mar 31 10:21:29 2012 +0300 Makefile: split romstage linking to separate rules After change it is more clear how romstage is linked twice and with what scripts. Also with the change, it is easier to add some object of static size that need to be re-compiled for the 2nd link. One such object could be md5sum of executable. Change-Id: Ib34d1876071a51345c5c7319a0ed937868817fd1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Sat Mar 31 11:33:17 2012, giving +2 See http://review.coreboot.org/803 for details. -gerrit

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Patch merged into coreboot/master: 2772620 Fix coreboot makefiles not to produce half baked output.
by gerrit＠coreboot.org 31 Mar '12

31 Mar '12

the following patch was just integrated into master: commit 2772620ad098e8dd1487667fbafd5947dbe5da08 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Mar 31 09:48:11 2012 +0300 Fix coreboot makefiles not to produce half baked output. There were cases where output file was generated and modified within a recipe. If make was interrupted, it could exit with an output file that appears as up-to-date, but was generated with incomplete recipe. The output file should be created only when successful, in an atomic operation. There could be other places in the make system which require a similar fix, this needs to be investigated further. Change-Id: I25c8ee23577a460eace196fd28c23cc67aa72a9a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Sat Mar 31 11:29:46 2012, giving +2 See http://review.coreboot.org/830 for details. -gerrit

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coreboot March 2012