coreboot March 2012

coreboot@coreboot.org

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718 discussions

Patch merged into coreboot/master: 2dc5544 Drop obsolete TINY_BOOTBLOCK
by gerrit＠coreboot.org 31 Mar '12

31 Mar '12

the following patch was just integrated into master: commit 2dc5544b32a83c63f0473bd4f5b48344289efeab Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Mar 31 11:05:52 2012 +0300 Drop obsolete TINY_BOOTBLOCK Change-Id: I0cbb5f7fce91fe65fe8daad00fc43e68337783b0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Sat Mar 31 11:28:07 2012, giving +2 See http://review.coreboot.org/832 for details. -gerrit

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New patch to review for coreboot: 2dc5544 Drop obsolete TINY_BOOTBLOCK
by Kyösti Mälkki 31 Mar '12

31 Mar '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/832 -gerrit commit 2dc5544b32a83c63f0473bd4f5b48344289efeab Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Mar 31 11:05:52 2012 +0300 Drop obsolete TINY_BOOTBLOCK Change-Id: I0cbb5f7fce91fe65fe8daad00fc43e68337783b0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/amd/dinar/Kconfig | 1 - src/mainboard/supermicro/h8qgi/Kconfig | 1 - 2 files changed, 0 insertions(+), 2 deletions(-) diff --git a/src/mainboard/amd/dinar/Kconfig b/src/mainboard/amd/dinar/Kconfig index d354a49..c81ccfa 100644 --- a/src/mainboard/amd/dinar/Kconfig +++ b/src/mainboard/amd/dinar/Kconfig @@ -43,7 +43,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES #TODO select HAVE_ACPI_RESUME select ENABLE_APIC_EXT_ID - select TINY_BOOTBLOCK select GFXUMA config MAINBOARD_DIR diff --git a/src/mainboard/supermicro/h8qgi/Kconfig b/src/mainboard/supermicro/h8qgi/Kconfig index 58f5692..4ab9a6b 100644 --- a/src/mainboard/supermicro/h8qgi/Kconfig +++ b/src/mainboard/supermicro/h8qgi/Kconfig @@ -41,7 +41,6 @@ config BOARD_SPECIFIC_OPTIONS select SERIAL_CPU_INIT select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_2048 - select TINY_BOOTBLOCK #select MMCONF_SUPPORT_DEFAULT #TODO enable it to resolve Multicore IO conflict config MAINBOARD_DIR

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New patch to review for coreboot: d9dd44c Keep cscope.out when distclean.
by Zheng Bao 31 Mar '12

31 Mar '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/831 -gerrit commit d9dd44c7d484839d8c9398e06eeca6505de7cb19 Author: zbao <zheng.bao(a)amd.com> Date: Fri Mar 23 10:26:28 2012 +0800 Keep cscope.out when distclean. It doesnt make sense to delete cscope.out when make distclean. Distclean is done all the time, and cscope database is also needed all the time. If we need to delete all the untracked files, we can use git-clean. Change-Id: Ic248ccd602ddc88d0b98d5d7f6cbbf530cd82e87 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- Makefile | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/Makefile b/Makefile index c5ee1f2..2723efb 100644 --- a/Makefile +++ b/Makefile @@ -276,7 +276,7 @@ clean: clean-for-update clean-target clean-cscope: rm -f cscope.out -distclean: clean-cscope +distclean: rm -rf $(obj) rm -f .config .config.old ..config.tmp .kconfig.d .tmpconfig* .ccwrap .xcompile

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Patch set updated for coreboot: bf34b57 Makefile: split romstage linking to separate rules
by Kyösti Mälkki 31 Mar '12

31 Mar '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/803 -gerrit commit bf34b57ec47f525055157f4e5ec0f77c151ea2e4 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Mar 31 10:21:29 2012 +0300 Makefile: split romstage linking to separate rules After change it is more clear how romstage is linked twice and with what scripts. Also with the change, it is easier to add some object of static size that need to be re-compiled for the 2nd link. One such object could be md5sum of executable. Change-Id: Ib34d1876071a51345c5c7319a0ed937868817fd1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/Makefile.inc | 41 ++++++++++++++++++++++++++++------------- 1 files changed, 28 insertions(+), 13 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 5917ce5..f131af9 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -274,9 +274,8 @@ $(obj)/coreboot.pre: $(obj)/coreboot.romstage $(obj)/coreboot.pre1 $(CBFSTOOL) @printf " CBFS $(subst $(obj)/,,$(@))\n" cp $(obj)/coreboot.pre1 $@.tmp $(CBFSTOOL) $@.tmp add-stage $(obj)/romstage.elf \ - $(CONFIG_CBFS_PREFIX)/romstage x 0x$(shell cat $(obj)/location.txt) + $(CONFIG_CBFS_PREFIX)/romstage x $(shell cat $(obj)/location.txt) mv $@.tmp $@ -#FIXME: location.txt might require an offset of header size ####################################################################### # Build the bootblock @@ -344,26 +343,42 @@ $(obj)/bootblock.elf: $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.o $(obj)/bootbl ####################################################################### # Build the romstage -$(obj)/coreboot.romstage: $(obj)/coreboot.pre1 $$(romstage-objs) $(obj)/romstage/ldscript.ld + +$(obj)/romstage.bin: $$(romstage-objs) $(obj)/romstage/link1st.ld @printf " LINK $(subst $(obj)/,,$(@))\n" - printf "ROMSTAGE_BASE = 0x0;\n" > $(obj)/location.ld - $(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/ldscript.ld $(romstage-objs) - $(OBJCOPY) -O binary $(obj)/romstage.elf $(obj)/romstage.bin - printf "ROMSTAGE_BASE = 0x" > $(obj)/location.ld - $(CBFSTOOL) $(obj)/coreboot.pre1 locate $(obj)/romstage.bin $(CONFIG_CBFS_PREFIX)/romstage $(CONFIG_XIP_ROM_SIZE) > $(obj)/location.txt || { echo "The romstage is larger than XIP size. Please expand the CONFIG_XIP_ROM_SIZE" ; exit 1; } - cat $(obj)/location.txt >> $(obj)/location.ld - printf ';\n' >> $(obj)/location.ld - $(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/ldscript.ld $(romstage-objs) + $(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/link1st.ld $(romstage-objs) + $(OBJCOPY) -O binary $(obj)/romstage.elf $@ + +$(obj)/coreboot.romstage: $$(romstage-objs) $(obj)/romstage/link2nd.ld + @printf " LINK $(subst $(obj)/,,$(@))\n" + $(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/link2nd.ld $(romstage-objs) $(NM) -n $(obj)/romstage.elf | sort > $(obj)/romstage.map $(OBJCOPY) --only-keep-debug $(obj)/romstage.elf $(obj)/romstage.debug $(OBJCOPY) --strip-debug $(obj)/romstage.elf $(OBJCOPY) --add-gnu-debuglink=$(obj)/romstage.debug $(obj)/romstage.elf $(OBJCOPY) -O binary $(obj)/romstage.elf $@ -$(obj)/romstage/ldscript.ld: $$(ldscripts) $(obj)/ldoptions +$(obj)/romstage/link1st.ld: $$(ldscripts) $(obj)/ldoptions @printf " GEN $(subst $(obj)/,,$(@))\n" mkdir -p $(obj)/romstage - printf '$(foreach ldscript,ldoptions location.ld $(ldscripts),INCLUDE "$(ldscript:$(obj)/%=%)"\n)' > $@ + rm -f $@ + printf "ROMSTAGE_BASE = 0x0;\n" > $@.tmp + printf '$(foreach ldscript,ldoptions $(ldscripts),INCLUDE "$(ldscript:$(obj)/%=%)"\n)' >> $@.tmp + mv $@.tmp $@ + +$(obj)/romstage/link2nd.ld: $(obj)/romstage/link1st.ld $(obj)/location.txt + @printf " GEN $(subst $(obj)/,,$(@))\n" + rm -f $@ + sed -e 's/^/ROMSTAGE_BASE = /g' -e 's/$$/;/g' $(obj)/location.txt > $@.tmp + sed -e '/ROMSTAGE_BASE/d' $(obj)/romstage/link1st.ld >> $@.tmp + mv $@.tmp $@ + +$(obj)/location.txt: $(obj)/coreboot.pre1 $(obj)/romstage.bin + rm -f $@ + $(CBFSTOOL) $(obj)/coreboot.pre1 locate $(obj)/romstage.bin $(CONFIG_CBFS_PREFIX)/romstage $(CONFIG_XIP_ROM_SIZE) > $@.tmp \ + || { echo "The romstage is larger than XIP size. Please expand the CONFIG_XIP_ROM_SIZE" ; exit 1; } + sed -i -e 's/^/0x/g' $@.tmp + mv $@.tmp $@ $(obj)/romstage/crt0.S: $$(crt0s) @printf " GEN $(subst $(obj)/,,$(@))\n"

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New patch to review for coreboot: 2772620 Fix coreboot makefiles not to produce half baked output.
by Kyösti Mälkki 31 Mar '12

31 Mar '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/830 -gerrit commit 2772620ad098e8dd1487667fbafd5947dbe5da08 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Mar 31 09:48:11 2012 +0300 Fix coreboot makefiles not to produce half baked output. There were cases where output file was generated and modified within a recipe. If make was interrupted, it could exit with an output file that appears as up-to-date, but was generated with incomplete recipe. The output file should be created only when successful, in an atomic operation. There could be other places in the make system which require a similar fix, this needs to be investigated further. Change-Id: I25c8ee23577a460eace196fd28c23cc67aa72a9a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/Makefile.inc | 34 ++++++++++++++++++---------------- 1 files changed, 18 insertions(+), 16 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 0a97ee5..5917ce5 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -146,11 +146,12 @@ $(objutil)/options/build_opt_tbl: $(top)/util/options/build_opt_tbl.c $(top)/src $(obj)/coreboot_ram: $(obj)/coreboot_ram.o $(src)/arch/x86/coreboot_ram.ld #ldoptions @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/x86/coreboot_ram.ld $(obj)/coreboot_ram.o - $(NM) -n $(obj)/coreboot_ram | sort > $(obj)/coreboot_ram.map - $(OBJCOPY) --only-keep-debug $@ $(obj)/coreboot_ram.debug - $(OBJCOPY) --strip-debug $@ - $(OBJCOPY) --add-gnu-debuglink=$(obj)/coreboot_ram.debug $@ + $(CC) -nostdlib -nostartfiles -static -o $@.tmp -L$(obj) -T $(src)/arch/x86/coreboot_ram.ld $(obj)/coreboot_ram.o + $(NM) -n $@.tmp | sort > $@.map + $(OBJCOPY) --only-keep-debug $@.tmp $@.debug + $(OBJCOPY) --strip-debug $@.tmp + $(OBJCOPY) --add-gnu-debuglink=$@.debug $@.tmp + mv $@.tmp $@ $(obj)/coreboot_ram.o: $(obj)/arch/x86/lib/c_start.ramstage.o $$(driver-objs) $(obj)/coreboot.a $(LIBGCC_FILE_NAME) @printf " CC $(subst $(obj)/,,$(@))\n" @@ -168,12 +169,12 @@ ifeq ($(CONFIG_AP_CODE_IN_CAR),y) $(obj)/coreboot_ap: $(obj)/mainboard/$(MAINBOARDDIR)/ap_romstage.o @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/x86/init/ldscript_apc.lb $^ - $(OBJCOPY) --only-keep-debug $@ $(obj)/coreboot_ap.debug - $(OBJCOPY) --strip-debug $@ - $(OBJCOPY) --add-gnu-debuglink=$(obj)/coreboot_ap.debug $@ - $(NM) -n $(obj)/coreboot_ap | sort > $(obj)/coreboot_ap.map - + $(CC) -nostdlib -nostartfiles -static -o $@.tmp -L$(obj) -T $(src)/arch/x86/init/ldscript_apc.lb $^ + $(OBJCOPY) --only-keep-debug $@.tmp $@.debug + $(OBJCOPY) --strip-debug $@.tmp + $(OBJCOPY) --add-gnu-debuglink=$@.debug $@.tmp + $(NM) -n $@.tmp | sort > $@.map + mv $@.tmp $@ endif @@ -334,11 +335,12 @@ $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc: $(src)/arch/x86/init/$(subst ",, $(obj)/bootblock.elf: $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.o $(obj)/bootblock/ldscript.ld @printf " LINK $(subst $(obj)/,,$(@))\n" - $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(obj)/bootblock/ldscript.ld $< - $(NM) -n $(obj)/bootblock.elf | sort > $(obj)/bootblock.map - $(OBJCOPY) --only-keep-debug $@ $(obj)/bootblock.debug - $(OBJCOPY) --strip-debug $@ - $(OBJCOPY) --add-gnu-debuglink=$(obj)/bootblock.debug $@ + $(CC) -nostdlib -nostartfiles -static -o $@.tmp -L$(obj) -T $(obj)/bootblock/ldscript.ld $< + $(NM) -n $@.tmp | sort > $(obj)/bootblock.map + $(OBJCOPY) --only-keep-debug $@.tmp $(obj)/bootblock.debug + $(OBJCOPY) --strip-debug $@.tmp + $(OBJCOPY) --add-gnu-debuglink=$(obj)/bootblock.debug $@.tmp + mv $@.tmp $@ ####################################################################### # Build the romstage

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Patch set updated for coreboot: e65e169 Add initial support for SMSC SIO1007 SuperI/O chip
by Stefan Reinauer 31 Mar '12

31 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/824 -gerrit commit e65e169edfb9eac77ba73d329a909407a9776105 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Mar 30 15:10:07 2012 -0700 Add initial support for SMSC SIO1007 SuperI/O chip early_serial and some ACPI needed for compilation Change-Id: I5dd970676488697156e0630392884f31149ac85b Signed-off-by: Gabe Black <gabeblack(a)google.com> --- src/superio/smsc/Kconfig | 2 + src/superio/smsc/Makefile.inc | 1 + src/superio/smsc/sio1007/acpi/superio.asl | 299 +++++++++++++++++++++++++++++ src/superio/smsc/sio1007/early_serial.c | 64 ++++++ 4 files changed, 366 insertions(+), 0 deletions(-) diff --git a/src/superio/smsc/Kconfig b/src/superio/smsc/Kconfig index d4f07ec..224376b 100644 --- a/src/superio/smsc/Kconfig +++ b/src/superio/smsc/Kconfig @@ -36,6 +36,8 @@ config SUPERIO_SMSC_LPC47N227 bool config SUPERIO_SMSC_SIO10N268 bool +config SUPERIO_SMSC_SIO1007 + bool config SUPERIO_SMSC_KBC1100 bool config SUPERIO_SMSC_SMSCSUPERIO diff --git a/src/superio/smsc/Makefile.inc b/src/superio/smsc/Makefile.inc index d07afea..bb4bf1d 100644 --- a/src/superio/smsc/Makefile.inc +++ b/src/superio/smsc/Makefile.inc @@ -27,6 +27,7 @@ subdirs-y += lpc47m15x subdirs-y += lpc47n217 subdirs-y += lpc47n227 subdirs-y += sio10n268 +subdirs-y += sio1007 subdirs-y += kbc1100 subdirs-y += smscsuperio subdirs-y += sio1036 diff --git a/src/superio/smsc/sio1007/acpi/superio.asl b/src/superio/smsc/sio1007/acpi/superio.asl new file mode 100644 index 0000000..5bb45fa --- /dev/null +++ b/src/superio/smsc/sio1007/acpi/superio.asl @@ -0,0 +1,299 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Scope is \_SB.PCI0.LPCB + +Device (SIO) { + Name (_ADR, 0x2E) + OperationRegion (SIOA, SystemIO, 0x2E, 0x02) + Field (SIOA, ByteAcc, NoLock, Preserve) + { + SI2E, 8, + SI2F, 8, + } + + IndexField (SI2E, SI2F, ByteAcc, NoLock, Preserve) + { + Offset (0x02), + SCNT, 8, /* Configure Control */ + Offset (0x07), + SLDN, 8, /* Logical Device Number */ + Offset (0x30), + SACT, 8, /* Activate */ + Offset (0x60), + IO0H, 8, /* Base Address 0 MSB */ + IO0L, 8, /* Base Address 0 LSB */ + Offset (0x62), + IO1H, 8, /* Base Address 1 MSB */ + IO1L, 8, /* Base Address 1 LSB */ + Offset (0x70), + IQ00, 8, /* Interrupt Select */ + } + + Name (SFDC, 0) /* Floppy Disk Controller */ + Name (SSP1, 1) /* Serial Port 1 */ + Name (SENV, 4) /* Environment Controller */ + Name (SKBC, 5) /* Keyboard */ + Name (SKBM, 6) /* Mouse */ + Name (SGPI, 7) /* GPIO */ + Name (SINF, 10) /* Consumer IR */ + + Method (ENTR, 0, NotSerialized) + { + Store (0x87, SI2E) + Store (0x01, SI2E) + Store (0x55, SI2E) + Store (0x55, SI2E) + } + + Method (EXIT, 0, NotSerialized) + { + Store (0x02, SCNT) + } + + /* Parse activate register for an LDN */ + Method (ISEN, 1, NotSerialized) + { + ENTR () + Store (Arg0, SLDN) + Store (SACT, Local0) + EXIT () + + /* Check if it exists */ + If (LEqual (Local0, 0xFF)) + { + Return (0x00) + } + + /* Check if activated */ + If (LEqual (Local0, One)) + { + Return (0x0F) + } + Else + { + Return (0x0D) + } + } + + /* Enable an LDN via the activate register */ + Method (SENA, 1, NotSerialized) + { + ENTR () + Store (Arg0, SLDN) + Store (One, SACT) + EXIT () + } + + /* Disable an LDN via the activate register */ + Method (SDIS, 1, NotSerialized) + { + ENTR () + Store (Arg0, SLDN) + Store (Zero, SACT) + EXIT () + } + +#ifdef SIO_ENABLE_ENVC + Device (ENVC) { + Name (_HID, EISAID ("PNP0C02")) + Name (_UID, 10) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (SENV)) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, SIO_ENVC_IO0, SIO_ENVC_IO0, 0x08, 0x08) + IO (Decode16, SIO_ENVC_IO1, SIO_ENVC_IO1, 0x04, 0x04) + }) + + Name (_PRS, ResourceTemplate () + { + IO (Decode16, SIO_ENVC_IO0, SIO_ENVC_IO0, 0x08, 0x08) + IO (Decode16, SIO_ENVC_IO1, SIO_ENVC_IO1, 0x04, 0x04) + }) + + OperationRegion (ECAP, SystemIO, SIO_ENVC_IO0, 0x07) + Field (ECAP, ByteAcc, NoLock, Preserve) + { + Offset (0x05), + ECAI, 8, // Address Index Register + ECAD, 8, // Address Data Register + } + + // Registers for thermal zone implementations + IndexField (ECAI, ECAD, ByteAcc, NoLock, Preserve) + { + Offset (0x29), + TIN1, 8, // TMPIN1 Reading + TIN2, 8, // TMPIN2 Reading + TIN3, 8, // TMPIN3 Reading + Offset (0x6b), + F2PS, 8, // FAN2 PWM Setting + Offset (0x73), + F3PS, 8, // FAN3 PWM Setting + } + } +#endif + +#ifdef SIO_ENABLE_GPIO + Device (GPIO) { + Name (_HID, EISAID ("PNP0C02")) + Name (_UID, 11) + + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, SIO_GPIO_IO0, SIO_GPIO_IO0, 0x01, 0x01) + IO (Decode16, SIO_GPIO_IO1, SIO_GPIO_IO1, 0x08, 0x08) + }) + + Name (_PRS, ResourceTemplate () + { + IO (Decode16, SIO_GPIO_IO0, SIO_GPIO_IO0, 0x01, 0x01) + IO (Decode16, SIO_GPIO_IO1, SIO_GPIO_IO1, 0x08, 0x08) + }) + } +#endif + +#ifdef SIO_ENABLE_COM1 + Device (COM1) { + Name (_HID, EISAID ("PNP0501")) + Name (_UID, 1) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (SSP1)) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08) + IRQNoFlags () {4} + }) + + Name (_PRS, ResourceTemplate () + { + IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08) + IRQNoFlags () {4} + }) + } +#endif + +#ifdef SIO_ENABLE_PS2K + Device (PS2K) // Keyboard + { + Name (_HID, EISAID("PNP0303")) + Name (_CID, EISAID("PNP030B")) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (SKBC)) + } + + Name (_CRS, ResourceTemplate() + { + IO (Decode16, 0x60, 0x60, 0x01, 0x01) + IO (Decode16, 0x64, 0x64, 0x01, 0x01) + IRQNoFlags () {1} + }) + + Name (_PRS, ResourceTemplate() + { + IO (Decode16, 0x60, 0x60, 0x01, 0x01) + IO (Decode16, 0x64, 0x64, 0x01, 0x01) + IRQNoFlags () {1} + }) + } +#endif + +#ifdef SIO_ENABLE_PS2M + Device (PS2M) // Mouse + { + Name (_HID, EISAID("PNP0F13")) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (SKBM)) + } + + Name (_CRS, ResourceTemplate() + { + IRQNoFlags () {12} + }) + + Name (_PRS, ResourceTemplate() + { + IRQNoFlags () {12} + }) + } +#endif + +#ifdef SIO_ENABLE_FDC0 + Device (FDC0) // Floppy controller + { + Name (_HID, EISAID ("PNP0700")) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (SFDC)) + } + + Name (_CRS, ResourceTemplate() + { + IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06) + IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01) + IRQNoFlags () {6} + DMA (Compatibility, NotBusMaster, Transfer8) {2} + }) + + Name (_PRS, ResourceTemplate() + { + IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06) + IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01) + IRQNoFlags () {6} + DMA (Compatibility, NotBusMaster, Transfer8) {2} + }) + } +#endif + +#ifdef SIO_ENABLE_INFR + Device (INFR) // Infrared controller + { + Name (_HID, EISAID ("PNP0510")) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (SINF)) + } + + Name (_CRS, ResourceTemplate() + { + IO (Decode16, SIO_INFR_IO0, SIO_INFR_IO0, 0x08, 0x08) + IRQNoFlags () { SIO_INFR_IRQ } + }) + + Name (_PRS, ResourceTemplate() + { + IO (Decode16, SIO_INFR_IO0, SIO_INFR_IO0, 0x08, 0x08) + IRQNoFlags () { SIO_INFR_IRQ } + }) + } +#endif +} diff --git a/src/superio/smsc/sio1007/early_serial.c b/src/superio/smsc/sio1007/early_serial.c new file mode 100644 index 0000000..859e351 --- /dev/null +++ b/src/superio/smsc/sio1007/early_serial.c @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * The chip could be bootstrap mapped to one of four LPC addresses: + * 0x2e, 0x4e, 0x162e, and 0x164e. + */ +const u16 sio1007_lpc_ports[] = {0x2e, 0x4e, 0x162e, 0x164e}; + +static void sio1007_setreg(u16 lpc_port, u8 reg, u8 value, u8 mask) +{ + u8 reg_value; + + outb(reg, lpc_port); + reg_value = inb(lpc_port + 1); + reg_value &= ~mask; + reg_value |= (value & mask); + outb(reg_value, lpc_port + 1); +} + +static int sio1007_enable_uart_at(u16 port) +{ + /* Enable config mode. */ + outb(0x55, port); + if (inb(port) != 0x55) + return 0; /* There is no LPC device at this address. */ + + /* Registers 12 and 13 hold config address, look for a match. */ + outb(0x12, port); + if (inb(port + 1) != (port & 0xff)) + return 0; + + outb(0x13, port); + if (inb(port + 1) != (port >> 8)) + return 0; + + /* This must be the sio1007, enable the UART. */ + /* turn on power */ + sio1007_setreg(port, 0x2, 1 << 3, 1 << 3); + /* enable high speed */ + sio1007_setreg(port, 0xc, 1 << 6, 1 << 6); + /* set the base address */ + sio1007_setreg(port, 0x24, CONFIG_TTYS0_BASE >> 2, 0xff); + + /* Disable config mode. */ + outb(0xaa, port); + return 1; +}

1 0

Patch set updated for coreboot: 563002c Add support for SMSC MEC1308/1310 SuperI/O EC
by Stefan Reinauer 31 Mar '12

31 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/825 -gerrit commit 563002c625a176f678309c0be453a13b41f7f5f8 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Mar 30 15:12:22 2012 -0700 Add support for SMSC MEC1308/1310 SuperI/O EC Change-Id: If7921a66bab35f72c8455d5f0befc32a514ab417 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/superio/smsc/Kconfig | 2 + src/superio/smsc/Makefile.inc | 1 + src/superio/smsc/mec1308/Makefile.inc | 20 ++ src/superio/smsc/mec1308/acpi/superio.asl | 261 +++++++++++++++++++++++++ src/superio/smsc/mec1308/chip.h | 34 ++++ src/superio/smsc/mec1308/mec1308.h | 27 +++ src/superio/smsc/mec1308/mec1308_early_init.c | 29 +++ src/superio/smsc/mec1308/superio.c | 121 ++++++++++++ 8 files changed, 495 insertions(+), 0 deletions(-) diff --git a/src/superio/smsc/Kconfig b/src/superio/smsc/Kconfig index 224376b..8d66fc5 100644 --- a/src/superio/smsc/Kconfig +++ b/src/superio/smsc/Kconfig @@ -40,6 +40,8 @@ config SUPERIO_SMSC_SIO1007 bool config SUPERIO_SMSC_KBC1100 bool +config SUPERIO_SMSC_MEC1308 + bool config SUPERIO_SMSC_SMSCSUPERIO bool config SUPERIO_SMSC_SIO1036 diff --git a/src/superio/smsc/Makefile.inc b/src/superio/smsc/Makefile.inc index bb4bf1d..8ebdf05 100644 --- a/src/superio/smsc/Makefile.inc +++ b/src/superio/smsc/Makefile.inc @@ -29,6 +29,7 @@ subdirs-y += lpc47n227 subdirs-y += sio10n268 subdirs-y += sio1007 subdirs-y += kbc1100 +subdirs-y += mec1308 subdirs-y += smscsuperio subdirs-y += sio1036 subdirs-y += sch4037 diff --git a/src/superio/smsc/mec1308/Makefile.inc b/src/superio/smsc/mec1308/Makefile.inc new file mode 100644 index 0000000..b2b7baa --- /dev/null +++ b/src/superio/smsc/mec1308/Makefile.inc @@ -0,0 +1,20 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Google Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +ramstage-$(CONFIG_SUPERIO_SMSC_MEC1308) += superio.c diff --git a/src/superio/smsc/mec1308/acpi/superio.asl b/src/superio/smsc/mec1308/acpi/superio.asl new file mode 100644 index 0000000..96f2ef8 --- /dev/null +++ b/src/superio/smsc/mec1308/acpi/superio.asl @@ -0,0 +1,261 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Scope is \_SB.PCI0.LPCB + +Device (SIO) { + OperationRegion (SIOA, SystemIO, 0x2E, 0x02) + Field (SIOA, ByteAcc, NoLock, Preserve) + { + SI2E, 8, + SI2F, 8, + } + + IndexField (SI2E, SI2F, ByteAcc, NoLock, Preserve) + { + Offset (0x07), + SLDN, 8, /* Logical Device Number */ + Offset (0x30), + SACT, 8, /* Activate */ + Offset (0x60), + IO0H, 8, /* Base Address 0 MSB */ + IO0L, 8, /* Base Address 0 LSB */ + Offset (0x62), + IO1H, 8, /* Base Address 1 MSB */ + IO1L, 8, /* Base Address 1 LSB */ + Offset (0x70), + IQ00, 8, /* Interrupt Select */ + } + + Name (LPM1, 1) /* ACPI PM1 */ + Name (LEC1, 2) /* EC 1 */ + Name (LEC2, 3) /* EC 2 */ + Name (LSP1, 4) /* Serial Port */ + Name (LKBC, 7) /* Keyboard */ + Name (LEC0, 8) /* EC 0 */ + Name (LMBX, 9) /* Mailbox */ + + Method (ENTR, 0, NotSerialized) + { + Store (0x55, SI2E) + } + + Method (EXIT, 0, NotSerialized) + { + Store (0xaa, SI2E) + } + + /* Parse activate register for an LDN */ + Method (ISEN, 1, NotSerialized) + { + ENTR () + Store (Arg0, SLDN) + Store (SACT, Local0) + EXIT () + + /* Check if it exists */ + If (LEqual (Local0, 0xFF)) + { + Return (0x00) + } + + /* Check if activated */ + If (LEqual (Local0, One)) + { + Return (0x0F) + } + Else + { + Return (0x0D) + } + } + + /* Enable an LDN via the activate register */ + Method (SENA, 1, NotSerialized) + { + ENTR () + Store (Arg0, SLDN) + Store (One, SACT) + EXIT () + } + + /* Disable an LDN via the activate register */ + Method (SDIS, 1, NotSerialized) + { + ENTR () + Store (Arg0, SLDN) + Store (Zero, SACT) + EXIT () + } + +#ifdef SIO_ENABLE_SPM1 + Device (SPM1) { + Name (_HID, EISAID ("PNP0C02")) + Name (_UID, 1) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (LPM1)) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, SIO_SPM1_IO0, SIO_SPM1_IO0, 0x08, 0x08) + }) + + Name (_PRS, ResourceTemplate () + { + IO (Decode16, SIO_SPM1_IO0, SIO_SPM1_IO0, 0x08, 0x08) + }) + } +#endif + +#ifdef SIO_ENABLE_SEC1 + Device (SEC1) { + Name (_HID, EISAID ("PNP0C09")) + Name (_UID, 2) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (LEC1)) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, SIO_SEC1_IO0, SIO_SEC1_IO0, 0x04, 0x04) + }) + + Name (_PRS, ResourceTemplate () + { + IO (Decode16, SIO_SEC1_IO0, SIO_SEC1_IO0, 0x04, 0x04) + }) + } +#endif + +#ifdef SIO_ENABLE_SEC2 + Device (SEC2) { + Name (_HID, EISAID ("PNP0C09")) + Name (_UID, 3) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (LEC2)) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, SIO_SEC2_IO0, SIO_SEC2_IO0, 0x04, 0x04) + }) + + Name (_PRS, ResourceTemplate () + { + IO (Decode16, SIO_SEC2_IO0, SIO_SEC2_IO0, 0x04, 0x04) + }) + } +#endif + +#ifdef SIO_ENABLE_SSP1 + Device (SSP1) { + Name (_HID, EISAID ("PNP0501")) + Name (_UID, 4) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (LSP1)) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, SIO_SSP1_IO0, SIO_SSP1_IO0, 0x08, 0x08) + IRQNoFlags () {SIO_SSP1_IRQ} + }) + + Name (_PRS, ResourceTemplate () + { + IO (Decode16, SIO_SSP1_IO0, SIO_SSP1_IO0, 0x08, 0x08) + IRQNoFlags () {SIO_SSP1_IRQ} + }) + } +#endif + +#ifdef SIO_ENABLE_SKBC + Device (SKBC) // Keyboard + { + Name (_HID, EISAID("PNP0303")) + Name (_CID, EISAID("PNP030B")) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (LKBC)) + } + + Name (_CRS, ResourceTemplate() + { + IO (Decode16, 0x60, 0x60, 0x01, 0x01) + IO (Decode16, 0x64, 0x64, 0x01, 0x01) + IRQNoFlags () {1} + }) + + Name (_PRS, ResourceTemplate() + { + IO (Decode16, 0x60, 0x60, 0x01, 0x01) + IO (Decode16, 0x64, 0x64, 0x01, 0x01) + IRQNoFlags () {1} + }) + } +#endif + +#ifdef SIO_ENABLE_SEC0 + Device (SEC0) { + Name (_HID, EISAID ("PNP0C09")) + Name (_UID, 8) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (LEC0)) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, SIO_SEC0_IO0, SIO_SEC0_IO0, 0x04, 0x04) + }) + + Name (_PRS, ResourceTemplate () + { + IO (Decode16, SIO_SEC0_IO0, SIO_SEC0_IO0, 0x04, 0x04) + }) + } +#endif + +#ifdef SIO_ENABLE_SMBX + Device (SMBX) // Mailbox + { + Name (_HID, EISAID("PNP0C02")) + Name (_UID, 9) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (LMBX)) + } + + Name (_CRS, ResourceTemplate() + { + IO (Decode16, SIO_SMBX_IO0, SIO_SMBX_IO0, 0x34, 0x34) + }) + + Name (_PRS, ResourceTemplate() + { + IO (Decode16, SIO_SMBX_IO0, SIO_SMBX_IO0, 0x34, 0x34) + }) + } +#endif +} diff --git a/src/superio/smsc/mec1308/chip.h b/src/superio/smsc/mec1308/chip.h new file mode 100644 index 0000000..04e829d --- /dev/null +++ b/src/superio/smsc/mec1308/chip.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_SMSC_MEC1308_CHIP_H +#define SUPERIO_SMSC_MEC1308_CHIP_H + +#include <pc80/keyboard.h> +#include <uart8250.h> + +struct chip_operations; +extern struct chip_operations superio_smsc_mec1308_ops; + +struct superio_smsc_mec1308_config { + + struct pc_keyboard keyboard; +}; + +#endif diff --git a/src/superio/smsc/mec1308/mec1308.h b/src/superio/smsc/mec1308/mec1308.h new file mode 100644 index 0000000..2b61234 --- /dev/null +++ b/src/superio/smsc/mec1308/mec1308.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define MEC1308_PM1 1 +#define MEC1308_EC1 2 +#define MEC1308_EC2 3 +#define MEC1308_UART 4 +#define MEC1308_KBC 7 +#define MEC1308_EC0 8 +#define MEC1308_MBX 9 + diff --git a/src/superio/smsc/mec1308/mec1308_early_init.c b/src/superio/smsc/mec1308/mec1308_early_init.c new file mode 100644 index 0000000..60d43a7 --- /dev/null +++ b/src/superio/smsc/mec1308/mec1308_early_init.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Pre-RAM driver for the SMSC MEC1308 EC chip */ + +#include <arch/romcc_io.h> +#include "mec1308.h" + +static inline void mec1308_early_init(unsigned port) +{ + +} + diff --git a/src/superio/smsc/mec1308/superio.c b/src/superio/smsc/mec1308/superio.c new file mode 100644 index 0000000..dfa155f --- /dev/null +++ b/src/superio/smsc/mec1308/superio.c @@ -0,0 +1,121 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* RAM driver for the SMSC KBC1100 Super I/O chip */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pnp.h> +#include <console/console.h> +#include <device/smbus.h> +#include <string.h> +#include <bitops.h> +#include <pc80/keyboard.h> +#include <stdlib.h> +#include "chip.h" +#include "mec1308.h" +#if CONFIG_HAVE_ACPI_RESUME +#include <arch/acpi.h> +#endif + +static void pnp_enter_conf_state(device_t dev) +{ + outb(0x55, dev->path.pnp.port); +} + +static void pnp_exit_conf_state(device_t dev) +{ + outb(0xaa, dev->path.pnp.port); +} + +static void mec1308_pnp_set_resources(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_set_resources(dev); + pnp_exit_conf_state(dev); +} + +static void mec1308_pnp_enable_resources(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_enable_resources(dev); + pnp_exit_conf_state(dev); +} + +static void mec1308_pnp_enable(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + + if(dev->enabled) { + pnp_set_enable(dev, 1); + } + else { + pnp_set_enable(dev, 0); + } + pnp_exit_conf_state(dev); +} + +static void mec1308_init(device_t dev) +{ + struct superio_smsc_mec1308_config *conf = dev->chip_info; + + if (!dev->enabled) + return; + + switch(dev->path.pnp.device) { + case MEC1308_KBC: +#if CONFIG_HAVE_ACPI_RESUME + if (acpi_slp_type == 3) + return; +#endif + pc_keyboard_init(&conf->keyboard); + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = mec1308_pnp_set_resources, + .enable_resources = mec1308_pnp_enable_resources, + .enable = mec1308_pnp_enable, + .init = mec1308_init, +}; + +static struct pnp_info pnp_dev_info[] = { + { &ops, MEC1308_PM1, PNP_IO0, { 0x7ff, 0 } }, + { &ops, MEC1308_EC1, PNP_IO0, { 0x7ff, 0 } }, + { &ops, MEC1308_EC2, PNP_IO0, { 0x7ff, 0 } }, + { &ops, MEC1308_UART, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, + { &ops, MEC1308_KBC, PNP_IRQ0, { 0, 0 } /* IO Fixed at 0x60/0x64 */ }, + { &ops, MEC1308_EC0, PNP_IO0, { 0x7ff, 0 } }, + { &ops, MEC1308_MBX, PNP_IO0, { 0x7ff, 0 } }, +}; + +static void enable_dev(device_t dev) +{ + pnp_enable_devices(dev, &pnp_ops, + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_smsc_mec1308_ops = { + CHIP_NAME("SMSC MEC1308 EC SuperIO Interface") + .enable_dev = enable_dev +}; +

1 0

Patch set updated for coreboot: f62e2d8 Add support for ITE IT8772F SuperI/O chip
by Stefan Reinauer 31 Mar '12

31 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/822 -gerrit commit f62e2d8ad35b6f7e1b6c56c04361fece45f9650b Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Mar 30 15:04:07 2012 -0700 Add support for ITE IT8772F SuperI/O chip Change-Id: I8e80c22eb0f3cb68f2457be6b2e7894df60ed632 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/superio/ite/Kconfig | 2 + src/superio/ite/Makefile.inc | 1 + src/superio/ite/it8772f/Makefile.inc | 21 ++ src/superio/ite/it8772f/acpi/superio.asl | 299 ++++++++++++++++++++++++++++++ src/superio/ite/it8772f/chip.h | 57 ++++++ src/superio/ite/it8772f/early_serial.c | 131 +++++++++++++ src/superio/ite/it8772f/it8772f.h | 120 ++++++++++++ src/superio/ite/it8772f/superio.c | 250 +++++++++++++++++++++++++ 8 files changed, 881 insertions(+), 0 deletions(-) diff --git a/src/superio/ite/Kconfig b/src/superio/ite/Kconfig index d045bf4..5d92a96 100644 --- a/src/superio/ite/Kconfig +++ b/src/superio/ite/Kconfig @@ -38,3 +38,5 @@ config SUPERIO_ITE_IT8718F bool config SUPERIO_ITE_IT8721F bool +config SUPERIO_ITE_IT8772F + bool diff --git a/src/superio/ite/Makefile.inc b/src/superio/ite/Makefile.inc index 1e734fe..fa44ff8 100644 --- a/src/superio/ite/Makefile.inc +++ b/src/superio/ite/Makefile.inc @@ -25,3 +25,4 @@ subdirs-y += it8712f subdirs-y += it8716f subdirs-y += it8718f subdirs-y += it8721f +subdirs-y += it8772f diff --git a/src/superio/ite/it8772f/Makefile.inc b/src/superio/ite/it8772f/Makefile.inc new file mode 100644 index 0000000..d001c61 --- /dev/null +++ b/src/superio/ite/it8772f/Makefile.inc @@ -0,0 +1,21 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +ramstage-$(CONFIG_SUPERIO_ITE_IT8772F) += superio.c diff --git a/src/superio/ite/it8772f/acpi/superio.asl b/src/superio/ite/it8772f/acpi/superio.asl new file mode 100644 index 0000000..5bb45fa --- /dev/null +++ b/src/superio/ite/it8772f/acpi/superio.asl @@ -0,0 +1,299 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Scope is \_SB.PCI0.LPCB + +Device (SIO) { + Name (_ADR, 0x2E) + OperationRegion (SIOA, SystemIO, 0x2E, 0x02) + Field (SIOA, ByteAcc, NoLock, Preserve) + { + SI2E, 8, + SI2F, 8, + } + + IndexField (SI2E, SI2F, ByteAcc, NoLock, Preserve) + { + Offset (0x02), + SCNT, 8, /* Configure Control */ + Offset (0x07), + SLDN, 8, /* Logical Device Number */ + Offset (0x30), + SACT, 8, /* Activate */ + Offset (0x60), + IO0H, 8, /* Base Address 0 MSB */ + IO0L, 8, /* Base Address 0 LSB */ + Offset (0x62), + IO1H, 8, /* Base Address 1 MSB */ + IO1L, 8, /* Base Address 1 LSB */ + Offset (0x70), + IQ00, 8, /* Interrupt Select */ + } + + Name (SFDC, 0) /* Floppy Disk Controller */ + Name (SSP1, 1) /* Serial Port 1 */ + Name (SENV, 4) /* Environment Controller */ + Name (SKBC, 5) /* Keyboard */ + Name (SKBM, 6) /* Mouse */ + Name (SGPI, 7) /* GPIO */ + Name (SINF, 10) /* Consumer IR */ + + Method (ENTR, 0, NotSerialized) + { + Store (0x87, SI2E) + Store (0x01, SI2E) + Store (0x55, SI2E) + Store (0x55, SI2E) + } + + Method (EXIT, 0, NotSerialized) + { + Store (0x02, SCNT) + } + + /* Parse activate register for an LDN */ + Method (ISEN, 1, NotSerialized) + { + ENTR () + Store (Arg0, SLDN) + Store (SACT, Local0) + EXIT () + + /* Check if it exists */ + If (LEqual (Local0, 0xFF)) + { + Return (0x00) + } + + /* Check if activated */ + If (LEqual (Local0, One)) + { + Return (0x0F) + } + Else + { + Return (0x0D) + } + } + + /* Enable an LDN via the activate register */ + Method (SENA, 1, NotSerialized) + { + ENTR () + Store (Arg0, SLDN) + Store (One, SACT) + EXIT () + } + + /* Disable an LDN via the activate register */ + Method (SDIS, 1, NotSerialized) + { + ENTR () + Store (Arg0, SLDN) + Store (Zero, SACT) + EXIT () + } + +#ifdef SIO_ENABLE_ENVC + Device (ENVC) { + Name (_HID, EISAID ("PNP0C02")) + Name (_UID, 10) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (SENV)) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, SIO_ENVC_IO0, SIO_ENVC_IO0, 0x08, 0x08) + IO (Decode16, SIO_ENVC_IO1, SIO_ENVC_IO1, 0x04, 0x04) + }) + + Name (_PRS, ResourceTemplate () + { + IO (Decode16, SIO_ENVC_IO0, SIO_ENVC_IO0, 0x08, 0x08) + IO (Decode16, SIO_ENVC_IO1, SIO_ENVC_IO1, 0x04, 0x04) + }) + + OperationRegion (ECAP, SystemIO, SIO_ENVC_IO0, 0x07) + Field (ECAP, ByteAcc, NoLock, Preserve) + { + Offset (0x05), + ECAI, 8, // Address Index Register + ECAD, 8, // Address Data Register + } + + // Registers for thermal zone implementations + IndexField (ECAI, ECAD, ByteAcc, NoLock, Preserve) + { + Offset (0x29), + TIN1, 8, // TMPIN1 Reading + TIN2, 8, // TMPIN2 Reading + TIN3, 8, // TMPIN3 Reading + Offset (0x6b), + F2PS, 8, // FAN2 PWM Setting + Offset (0x73), + F3PS, 8, // FAN3 PWM Setting + } + } +#endif + +#ifdef SIO_ENABLE_GPIO + Device (GPIO) { + Name (_HID, EISAID ("PNP0C02")) + Name (_UID, 11) + + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, SIO_GPIO_IO0, SIO_GPIO_IO0, 0x01, 0x01) + IO (Decode16, SIO_GPIO_IO1, SIO_GPIO_IO1, 0x08, 0x08) + }) + + Name (_PRS, ResourceTemplate () + { + IO (Decode16, SIO_GPIO_IO0, SIO_GPIO_IO0, 0x01, 0x01) + IO (Decode16, SIO_GPIO_IO1, SIO_GPIO_IO1, 0x08, 0x08) + }) + } +#endif + +#ifdef SIO_ENABLE_COM1 + Device (COM1) { + Name (_HID, EISAID ("PNP0501")) + Name (_UID, 1) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (SSP1)) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08) + IRQNoFlags () {4} + }) + + Name (_PRS, ResourceTemplate () + { + IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08) + IRQNoFlags () {4} + }) + } +#endif + +#ifdef SIO_ENABLE_PS2K + Device (PS2K) // Keyboard + { + Name (_HID, EISAID("PNP0303")) + Name (_CID, EISAID("PNP030B")) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (SKBC)) + } + + Name (_CRS, ResourceTemplate() + { + IO (Decode16, 0x60, 0x60, 0x01, 0x01) + IO (Decode16, 0x64, 0x64, 0x01, 0x01) + IRQNoFlags () {1} + }) + + Name (_PRS, ResourceTemplate() + { + IO (Decode16, 0x60, 0x60, 0x01, 0x01) + IO (Decode16, 0x64, 0x64, 0x01, 0x01) + IRQNoFlags () {1} + }) + } +#endif + +#ifdef SIO_ENABLE_PS2M + Device (PS2M) // Mouse + { + Name (_HID, EISAID("PNP0F13")) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (SKBM)) + } + + Name (_CRS, ResourceTemplate() + { + IRQNoFlags () {12} + }) + + Name (_PRS, ResourceTemplate() + { + IRQNoFlags () {12} + }) + } +#endif + +#ifdef SIO_ENABLE_FDC0 + Device (FDC0) // Floppy controller + { + Name (_HID, EISAID ("PNP0700")) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (SFDC)) + } + + Name (_CRS, ResourceTemplate() + { + IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06) + IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01) + IRQNoFlags () {6} + DMA (Compatibility, NotBusMaster, Transfer8) {2} + }) + + Name (_PRS, ResourceTemplate() + { + IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06) + IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01) + IRQNoFlags () {6} + DMA (Compatibility, NotBusMaster, Transfer8) {2} + }) + } +#endif + +#ifdef SIO_ENABLE_INFR + Device (INFR) // Infrared controller + { + Name (_HID, EISAID ("PNP0510")) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (SINF)) + } + + Name (_CRS, ResourceTemplate() + { + IO (Decode16, SIO_INFR_IO0, SIO_INFR_IO0, 0x08, 0x08) + IRQNoFlags () { SIO_INFR_IRQ } + }) + + Name (_PRS, ResourceTemplate() + { + IO (Decode16, SIO_INFR_IO0, SIO_INFR_IO0, 0x08, 0x08) + IRQNoFlags () { SIO_INFR_IRQ } + }) + } +#endif +} diff --git a/src/superio/ite/it8772f/chip.h b/src/superio/ite/it8772f/chip.h new file mode 100644 index 0000000..e91f6fa --- /dev/null +++ b/src/superio/ite/it8772f/chip.h @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_ITE_IT8772F_CHIP_H +#define SUPERIO_ITE_IT8772F_CHIP_H + +#include <device/device.h> +#include <pc80/keyboard.h> +#include <uart8250.h> + +extern struct chip_operations superio_ite_it8772f_ops; + +struct superio_ite_it8772f_config { + struct pc_keyboard keyboard; + + /* GPIO SimpleIO register values via devicetree.cb */ + u8 gpio_set1; + u8 gpio_set2; + u8 gpio_set3; + u8 gpio_set4; + u8 gpio_set5; + u8 gpio_set6; + + u8 skip_keyboard; + + /* + * Enable external temperature sensor to use PECI GetTemp() + * command and store in register TMPIN 1, 2, or 3. + */ + u8 peci_tmpin; + + /* + * Enable a FAN for sofware control. + */ + u8 fan1_enable; + u8 fan2_enable; + u8 fan3_enable; +}; + +#endif diff --git a/src/superio/ite/it8772f/early_serial.c b/src/superio/ite/it8772f/early_serial.c new file mode 100644 index 0000000..0721060 --- /dev/null +++ b/src/superio/ite/it8772f/early_serial.c @@ -0,0 +1,131 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/romcc_io.h> +#include <device/pnp_def.h> +#include "it8772f.h" + +/* The base address is 0x2e or 0x4e, depending on config bytes. */ +#define SIO_BASE IT8772F_BASE +#define SIO_INDEX SIO_BASE +#define SIO_DATA (SIO_BASE + 1) + +/* Global configuration registers. */ +#define IT8772F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ +#define IT8772F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ +#define IT8772F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ +#define IT8772F_CONFIG_REG_MFC 0x2a /* Multi-function control */ +#define IT8772F_CONFIG_REG_WATCHDOG 0x72 /* Watchdog control. */ + +u8 it8772f_sio_read(u8 index) +{ + outb(index, SIO_BASE); + return inb(SIO_DATA); +} + +void it8772f_sio_write(u8 index, u8 value) +{ + outb(index, SIO_BASE); + outb(value, SIO_DATA); +} + +static void it8772f_enter_conf(void) +{ + u16 port = SIO_BASE; + + outb(0x87, port); + outb(0x01, port); + outb(0x55, port); + outb((port == 0x4e) ? 0xaa : 0x55, port); +} + +static void it8772f_exit_conf(void) +{ + it8772f_sio_write(IT8772F_CONFIG_REG_CC, 0x02); +} + +/* Select 24MHz CLKIN (48MHz is the default). */ +void it8772f_24mhz_clkin(void) +{ + it8772f_enter_conf(); + it8772f_sio_write(IT8772F_CONFIG_REG_LDN, 0x00); + it8772f_sio_write(IT8772F_CONFIG_REG_CLOCKSEL, 0x1); + it8772f_exit_conf(); +} + +/* + * LDN 7, reg 0x2a - needed for S3, or memory power will be cut off. + * + * Enable 3VSBSW#. (For System Suspend-to-RAM) + * 0: 3VSBSW# will be always inactive. + * 1: 3VSBSW# enabled. It will be (NOT SUSB#) NAND SUSC#. + */ +void it8772f_enable_3vsbsw(void) +{ + it8772f_enter_conf(); + it8772f_sio_write(IT8772F_CONFIG_REG_LDN, IT8772F_GPIO); + it8772f_sio_write(IT8772F_CONFIG_REG_MFC, 0x80); + it8772f_exit_conf(); +} + +void it8772f_kill_watchdog(void) +{ + it8772f_enter_conf(); + it8772f_sio_write(IT8772F_CONFIG_REG_LDN, IT8772F_GPIO); + it8772f_sio_write(IT8772F_CONFIG_REG_WATCHDOG, 0x00); + it8772f_exit_conf(); +} + +/* Enable the serial port(s). */ +void it8772f_enable_serial(device_t dev, u16 iobase) +{ + it8772f_enter_conf(); + it8772f_sio_write(IT8772F_CONFIG_REG_LDN, dev & 0xff); + it8772f_sio_write(PNP_IDX_IO0, (iobase >> 8) & 0xff); + it8772f_sio_write(PNP_IDX_IO0+1, iobase & 0xff); + it8772f_sio_write(PNP_IDX_EN, 1); + it8772f_exit_conf(); +} + +/* Set AC resume to be up to the Southbridge */ +void it8772f_ac_resume_southbridge(void) +{ + it8772f_enter_conf(); + it8772f_sio_write(IT8772F_CONFIG_REG_LDN, IT8772F_EC); + it8772f_sio_write(0xf4, 0x60); + it8772f_exit_conf(); +} + +/* Configure a set of GPIOs */ +void it8772f_gpio_setup(int set, u8 select, u8 polarity, u8 pullup, + u8 output, u8 enable) +{ + set--; /* Set 1 is offset 0 */ + it8772f_enter_conf(); + it8772f_sio_write(IT8772F_CONFIG_REG_LDN, IT8772F_GPIO); + if (set < 5) { + it8772f_sio_write(GPIO_REG_SELECT(set), select); + it8772f_sio_write(GPIO_REG_ENABLE(set), enable); + it8772f_sio_write(GPIO_REG_POLARITY(set), polarity); + } + it8772f_sio_write(GPIO_REG_OUTPUT(set), output); + it8772f_sio_write(GPIO_REG_PULLUP(set), pullup); + it8772f_exit_conf(); +} diff --git a/src/superio/ite/it8772f/it8772f.h b/src/superio/ite/it8772f/it8772f.h new file mode 100644 index 0000000..1ec82e1 --- /dev/null +++ b/src/superio/ite/it8772f/it8772f.h @@ -0,0 +1,120 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_ITE_IT8772F_IT8772F_H +#define SUPERIO_ITE_IT8772F_IT8772F_H + +#define IT8772F_BASE 0x2e + +#define IT8772F_FDC 0x00 /* Floppy disk controller */ +#define IT8772F_SP1 0x01 /* Com1 */ +#define IT8772F_EC 0x04 /* Environment controller */ +#define IT8772F_KBCK 0x05 /* Keyboard */ +#define IT8772F_KBCM 0x06 /* Mouse */ +#define IT8772F_GPIO 0x07 /* GPIO */ +#define IT8772F_IR 0x0a /* Consumer IR */ + +/* Environmental Controller interface */ +#define IT8772F_INTERFACE_SELECT 0x0a +#define IT8772F_INTERFACE_PSEUDO_EOC (1 << 7) +#define IT8772F_INTERFACE_SMB_ENABLE (1 << 6) +#define IT8772F_INTERFACE_SEL_DISABLE (0 << 4) +#define IT8772F_INTERFACE_SEL_SST_SLAVE (1 << 4) +#define IT8772F_INTERFACE_SEL_PECI (2 << 4) +#define IT8772F_INTERFACE_SEL_SST_HOST (3 << 4) +#define IT8772F_INTERFACE_CLOCK_32MHZ (0 << 3) +#define IT8772F_INTERFACE_CLOCK_24MHZ (1 << 3) +#define IT8772F_INTERFACE_SPEED_TOLERANCE (1 << 2) +#define IT8772F_INTERFACE_PECI_AWFCS (1 << 0) +#define IT8772F_FAN_TAC2_READ 0x0e +#define IT8772F_FAN_TAC3_READ 0x0f +#define IT8772F_FAN_MAIN_CTL 0x13 +#define IT8772F_FAN_MAIN_CTL_TAC_SMART(x) (1 << ((x)-1)) +#define IT8772F_FAN_MAIN_CTL_TAC_EN(x) (1 << ((x)+3)) +#define IT8772F_FAN_CTL_MODE 0x14 +#define IT8772F_FAN_CTL_ON(x) (1 << ((x)-1)) +#define IT8772F_FAN_PWM_MIN_DUTY (1 << 3) +#define IT8772F_FAN_PWM_CLOCK_48MHZ (0 << 4) +#define IT8772F_FAN_PWM_CLOCK_24MHZ (1 << 4) +#define IT8772F_FAN_PWM_CLOCK_8MHZ (3 << 4) +#define IT8772F_FAN_PWM_CLOCK_6MHZ (4 << 4) +#define IT8772F_FAN_PWM_CLOCK_3MHZ (5 << 4) +#define IT8772F_FAN_PWM_CLOCK_1_5MHZ (6 << 4) +#define IT8772F_FAN_PWM_CLOCK_51KHZ (7 << 4) +#define IT8772F_FAN_CTL_POLARITY_LOW (0 << 7) +#define IT8772F_FAN_CTL_POLARITY_HIGH (1 << 7) +#define IT8772F_FAN_CTL2_PWM_MODE 0x16 +#define IT8772F_FAN_CTL3_PWM_MODE 0x17 +#define IT8772F_FAN_CTL_PWM_MODE_SOFTWARE (0 << 7) +#define IT8772F_FAN_CTL_PWM_MODE_AUTOMATIC (1 << 7) +#define IT8772F_ADC_TEMP_CHANNEL_ENABLE 0x51 +#define IT8772F_FAN_CTL2_PWM_START 0x6b +#define IT8772F_FAN_CTL2_AUTO_MODE 0x6c +#define IT8772F_FAN_CTL3_PWM_START 0x73 +#define IT8772F_FAN_CTL3_AUTO_MODE 0x74 +#define IT8772F_FAN_CTL_AUTO_SMOOTHING_DIS (0 << 7) +#define IT8772F_FAN_CTL_AUTO_SMOOTHING_EN (1 << 7) +#define IT8772F_EXTEMP_STATUS 0x88 +#define IT8772F_EXTEMP_ADDRESS 0x89 +#define IT8772F_EXTEMP_WRITE_LENGTH 0x8a +#define IT8772F_EXTEMP_READ_LENGTH 0x8b +#define IT8772F_EXTEMP_COMMAND 0x8c +#define IT8772F_EXTEMP_WRITE_DATA_2 0x8d +#define IT8772F_EXTEMP_CONTROL 0x8e +#define IT8772F_EXTEMP_CONTROL_AUTO_32HZ (0 << 6) +#define IT8772F_EXTEMP_CONTROL_AUTO_16HZ (1 << 6) +#define IT8772F_EXTEMP_CONTROL_AUTO_8HZ (2 << 6) +#define IT8772F_EXTEMP_CONTROL_AUTO_4HZ (3 << 6) +#define IT8772F_EXTEMP_CONTROL_AUTO_START (1 << 5) +#define IT8772F_EXTEMP_CONTROL_AUTO_ABORT (1 << 4) +#define IT8772F_EXTEMP_CONTROL_AUTO_TWO_DOMAIN (1 << 3) +#define IT8772F_EXTEMP_CONTROL_CONTENTION (1 << 2) +#define IT8772F_EXTEMP_CONTROL_SST_IDLE_HIGH (1 << 1) +#define IT8772F_EXTEMP_CONTROL_START (1 << 0) + +/* Standard PECI GetTemp */ +#define PECI_CLIENT_ADDRESS 0x30 +#define PECI_GETTEMP_COMMAND 0x01 +#define PECI_GETTEMP_WRITE_LENGTH 0x01 +#define PECI_GETTEMP_READ_LENGTH 0x02 + +/* GPIO interface */ +#define IT8772F_GPIO_LED_BLINK1_PINMAP 0xf8 +#define IT8772F_GPIO_LED_BLINK1_CONTROL 0xf9 + +#define GPIO_REG_SELECT(x) (0x25 + (x)) +#define GPIO_REG_POLARITY(x) (0xb0 + (x)) +#define GPIO_REG_PULLUP(x) (0xb8 + (x)) +#define GPIO_REG_ENABLE(x) (0xc0 + (x)) +#define GPIO_REG_OUTPUT(x) (0xc8 + (x)) + +#ifndef __ROMCC__ +u8 it8772f_sio_read(u8 index); +void it8772f_sio_write(u8 index, u8 value); +void it8772f_enable_serial(device_t dev, u16 iobase); +void it8772f_kill_watchdog(void); +void it8772f_24mhz_clkin(void); +void it8772f_enable_3vsbsw(void); +void it8772f_ac_resume_southbridge(void); +void it8772f_gpio_setup(int set, u8 func_select, u8 polarity, u8 pullup, + u8 output, u8 enable); +#endif + +#endif diff --git a/src/superio/ite/it8772f/superio.c b/src/superio/ite/it8772f/superio.c new file mode 100644 index 0000000..1361ef2 --- /dev/null +++ b/src/superio/ite/it8772f/superio.c @@ -0,0 +1,250 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include <device/pnp.h> +#include <uart8250.h> +#include <pc80/keyboard.h> +#include <arch/io.h> +#include <stdlib.h> +#include "chip.h" +#include "it8772f.h" + +static void pnp_enter_ext_func_mode(device_t dev) +{ + u16 port = dev->path.pnp.port; + + outb(0x87, port); + outb(0x01, port); + outb(0x55, port); + outb((port == 0x4e) ? 0xaa : 0x55, port); +} + +static void pnp_exit_ext_func_mode(device_t dev) +{ + pnp_write_config(dev, 0x02, 0x02); +} + +static inline u8 it8772f_envc_read(struct resource *res, u8 addr) +{ + outb(addr, res->base + 5); + return inb(res->base + 6); +} + +static inline void it8772f_envc_write(struct resource *res, u8 addr, u8 value) +{ + outb(addr, res->base + 5); + outb(value, res->base + 6); +} + +/* + * Setup External Temperature to read via PECI into TMPINx register + */ +static void it8772f_enable_peci(struct resource *res, int tmpin) +{ + if (tmpin < 1 || tmpin > 3) + return; + + /* Enable PECI interface */ + it8772f_envc_write(res, IT8772F_INTERFACE_SELECT, + IT8772F_INTERFACE_SEL_PECI | + IT8772F_INTERFACE_SPEED_TOLERANCE); + + /* Setup External Temperature using PECI GetTemp */ + it8772f_envc_write(res, IT8772F_EXTEMP_ADDRESS, + PECI_CLIENT_ADDRESS); + it8772f_envc_write(res, IT8772F_EXTEMP_COMMAND, + PECI_GETTEMP_COMMAND); + it8772f_envc_write(res, IT8772F_EXTEMP_WRITE_LENGTH, + PECI_GETTEMP_WRITE_LENGTH); + it8772f_envc_write(res, IT8772F_EXTEMP_READ_LENGTH, + PECI_GETTEMP_READ_LENGTH); + it8772f_envc_write(res, IT8772F_EXTEMP_CONTROL, + IT8772F_EXTEMP_CONTROL_AUTO_4HZ | + IT8772F_EXTEMP_CONTROL_AUTO_START); + + /* External Temperature reported in TMPINx register */ + it8772f_envc_write(res, IT8772F_ADC_TEMP_CHANNEL_ENABLE, + (tmpin & 3) << 6); +} + +/* + * Setup a FAN PWM interface for software control + */ +static void it8772f_enable_fan(struct resource *res, int fan) +{ + u8 reg; + + if (fan < 1 || fan > 3) + return; + + /* Enable 6MHz (23.43kHz PWM) active high output */ + reg = it8772f_envc_read(res, IT8772F_FAN_CTL_MODE); + reg |= IT8772F_FAN_CTL_ON(fan) | + IT8772F_FAN_PWM_CLOCK_6MHZ | + IT8772F_FAN_CTL_POLARITY_HIGH; + it8772f_envc_write(res, IT8772F_FAN_CTL_MODE, reg); + + /* Enable output in smart mode */ + reg = it8772f_envc_read(res, IT8772F_FAN_MAIN_CTL); + reg |= IT8772F_FAN_MAIN_CTL_TAC_SMART(fan); + reg |= IT8772F_FAN_MAIN_CTL_TAC_EN(fan); + it8772f_envc_write(res, IT8772F_FAN_MAIN_CTL, reg); + + switch (fan) { + case 2: + /* Enable software operation */ + it8772f_envc_write(res, IT8772F_FAN_CTL2_PWM_MODE, + IT8772F_FAN_CTL_PWM_MODE_SOFTWARE); + /* Disable Smoothing */ + it8772f_envc_write(res, IT8772F_FAN_CTL2_AUTO_MODE, + IT8772F_FAN_CTL_AUTO_SMOOTHING_DIS); + /* Set a default medium fan speed */ + it8772f_envc_write(res, IT8772F_FAN_CTL2_PWM_START, 0x80); + break; + case 3: + /* Enable software operation */ + it8772f_envc_write(res, IT8772F_FAN_CTL3_PWM_MODE, + IT8772F_FAN_CTL_PWM_MODE_SOFTWARE); + /* Disable Smoothing */ + it8772f_envc_write(res, IT8772F_FAN_CTL3_AUTO_MODE, + IT8772F_FAN_CTL_AUTO_SMOOTHING_DIS); + /* Set a default medium fan speed */ + it8772f_envc_write(res, IT8772F_FAN_CTL3_PWM_START, 0x80); + break; + } +} + +static void it8772f_init(device_t dev) +{ + struct superio_ite_it8772f_config *conf = dev->chip_info; + struct resource *res; + + if (!dev->enabled) + return; + + switch (dev->path.pnp.device) { + case IT8772F_EC: + res = find_resource(dev, PNP_IDX_IO0); + if (!res) + break; + + /* Enable PECI if configured */ + it8772f_enable_peci(res, conf->peci_tmpin); + + /* Enable FANx if configured */ + if (conf->fan1_enable) + it8772f_enable_fan(res, 1); + if (conf->fan2_enable) + it8772f_enable_fan(res, 2); + if (conf->fan3_enable) + it8772f_enable_fan(res, 3); + break; + case IT8772F_GPIO: + /* Set GPIO output levels */ + res = find_resource(dev, PNP_IDX_IO1); + if (res) { + if (conf->gpio_set1) + outb(conf->gpio_set1, res->base + 0); + if (conf->gpio_set2) + outb(conf->gpio_set2, res->base + 1); + if (conf->gpio_set3) + outb(conf->gpio_set3, res->base + 2); + if (conf->gpio_set4) + outb(conf->gpio_set4, res->base + 3); + if (conf->gpio_set5) + outb(conf->gpio_set5, res->base + 4); + if (conf->gpio_set6) + outb(conf->gpio_set6, res->base + 5); + } + break; + case IT8772F_KBCK: + if (!conf->skip_keyboard) { + set_kbc_ps2_mode(); + pc_keyboard_init(&conf->keyboard); + } + break; + case IT8772F_KBCM: + break; + case IT8772F_IR: + break; + } +} + +static void it8772f_pnp_set_resources(device_t dev) +{ + pnp_enter_ext_func_mode(dev); + pnp_set_resources(dev); + pnp_exit_ext_func_mode(dev); +} + +static void it8772f_pnp_enable_resources(device_t dev) +{ + pnp_enter_ext_func_mode(dev); + pnp_enable_resources(dev); + pnp_exit_ext_func_mode(dev); +} + +static void it8772f_pnp_enable(device_t dev) +{ + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, !!dev->enabled); + pnp_exit_ext_func_mode(dev); +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = it8772f_pnp_set_resources, + .enable_resources = it8772f_pnp_enable_resources, + .enable = it8772f_pnp_enable, + .init = it8772f_init, +}; + +static struct pnp_info pnp_dev_info[] = { + /* Floppy Disk Controller */ + { &ops, IT8772F_FDC, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, + /* Serial Port 1 */ + { &ops, IT8772F_SP1, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, + /* Environmental Controller */ + { &ops, IT8772F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, + {0x0ff8, 0}, {0x0ffc, 4}, }, + /* KBC Keyboard */ + { &ops, IT8772F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, + {0x0fff, 0}, {0x0fff, 4}, }, + /* KBC Mouse */ + { &ops, IT8772F_KBCM, PNP_IRQ0, }, + /* 27 GPIOs */ + { &ops, IT8772F_GPIO, PNP_IO0 | PNP_IO1, + {0x0fff, 0}, {0x0ff8, 0}, }, + /* Infrared */ + { &ops, IT8772F_IR, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &pnp_ops, + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_ite_it8772f_ops = { + CHIP_NAME("ITE IT8772F Super I/O") + .enable_dev = enable_dev, +};

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Patch set updated for coreboot: 5806c38 Add support for SMSC LPC47N207 SuperI/O chip
by Stefan Reinauer 31 Mar '12

31 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/823 -gerrit commit 5806c38c93ad5dcc860e3637d80908766a19c154 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Mar 30 15:06:04 2012 -0700 Add support for SMSC LPC47N207 SuperI/O chip This includes only early serial support for now. Change-Id: I9a2a439e1d17a989428033fdb4a4b813553dab6d Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/superio/smsc/lpc47n207/early_serial.c | 122 +++++++++++++++++++++++++++++ src/superio/smsc/lpc47n207/lpc47n207.h | 25 ++++++ 2 files changed, 147 insertions(+), 0 deletions(-) diff --git a/src/superio/smsc/lpc47n207/early_serial.c b/src/superio/smsc/lpc47n207/early_serial.c new file mode 100644 index 0000000..41e1b10 --- /dev/null +++ b/src/superio/smsc/lpc47n207/early_serial.c @@ -0,0 +1,122 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * This code tries to discover the SMSC LPC47N207 superio chip which can be + * connected over an LPC dongle. The chip could be bootstrap mapped to one of + * four LPC addresses: 0x2e, 0x4e, 0x162e, and 0x164e. + * + * Initializing the UART requires accesses to a few control registers. This + * structure includes the register offset and the value to write (along with + * the mask). + */ +typedef struct { + u8 conf_reg; + u8 value; + u8 mask; +} uart_conf; + +/* All regs/values to write to initialize the LPC47N207 UART */ +static const uart_conf uart_conf_data [] = { + {2, (1 << 3), (1 << 3)}, /* cr02, enable Primary UART power */ + {0xc, (1 << 6), (1 << 6)}, /* cr0c, enable Primary UART high speed */ + {0x24, (CONFIG_TTYS0_BASE >> 3) << 1, 0xff}, /* cr24, base addr */ +}; + +void try_enabling_LPC47N207_uart(void) +{ + device_t dev = PCH_LPC_DEV; + u16 saved_basic_config; + u16 saved_extended_config; + u8 reg_value; + const uart_conf* conf_item; + u16 lpc_ports[] = {0x2e, 0x4e, 0x162e, 0x164e}; + u16 lpc_port; + int i, j; + + /* preserve the LPC controller conffguration */ + saved_basic_config = pci_read_config16(dev, LPC_EN); + saved_extended_config = pci_read_config32(dev, LPC_GEN1_DEC); + + /* enable COMA mapping and all possible LPC addresses of 47N207 */ + pci_write_config16(dev, LPC_EN, + saved_basic_config | + CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN); + + /* map full 256 bytes at 0x1600 to the LPC bus */ + pci_write_config32(dev, LPC_GEN1_DEC, 0xfc1601); + + /* Set COM1/COM2 decode range */ + pci_write_config16(dev, LPC_IO_DEC, 0x0010); + +#define CONFIG_ENABLE 0x55 +#define CONFIG_DISABLE 0xaa + + for (j = 0; j < ARRAY_SIZE(lpc_ports); j++) { + lpc_port = lpc_ports[j]; + + /* enable CONFIG mode */ + outb(CONFIG_ENABLE, lpc_port); + reg_value=inb(lpc_port); + if (reg_value != CONFIG_ENABLE) { + continue; /* There is no LPC device at this address */ + } + + do { + /* + * Registers 12 and 13 hold config address, look for a + * match. + */ + outb(0x12, lpc_port); + reg_value=inb(lpc_port + 1); + if (reg_value != (lpc_port & 0xff)) + break; + + outb(0x13, lpc_port); + reg_value=inb(lpc_port + 1); + if (reg_value != (lpc_port >> 8)) + break; + + /* This must be the SMSC LPC 47N207, enable the UART. */ + for (i = 0; i < ARRAY_SIZE(uart_conf_data); i++) { + u8 reg, value, mask; + + conf_item = uart_conf_data + i; + + reg = conf_item->conf_reg; + value = conf_item->value; + mask = conf_item->mask; + + outb(reg, lpc_port); + reg_value = inb(lpc_port + 1); + reg_value &= ~mask; + reg_value |= (value & mask); + outb(reg_value, lpc_port + 1); + } + /* Keep COMA UART enable bit on */ + saved_basic_config |= COMA_LPC_EN; + } while (0); + outb(CONFIG_DISABLE, lpc_port); + } + + /* Restore PCH config state. */ + pci_write_config16(dev, LPC_EN, saved_basic_config); + pci_write_config32(dev, LPC_GEN1_DEC, saved_extended_config); + +} diff --git a/src/superio/smsc/lpc47n207/lpc47n207.h b/src/superio/smsc/lpc47n207/lpc47n207.h new file mode 100644 index 0000000..69689a4 --- /dev/null +++ b/src/superio/smsc/lpc47n207/lpc47n207.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_SMSC_LPC47N207_LPC47N207_H +#define SUPERIO_SMSC_LPC47N207_LPC47N207_H + +extern void try_enabling_LPC47N207_uart(void); + +#endif

1 0

Patch set updated for coreboot: 69d9d86 Align: Make sure 1 is treated as unsigned long instead of int
by Stefan Reinauer 31 Mar '12

31 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/820 -gerrit commit 69d9d86b4a64ddc01d3bd3956b5984afeb7e2f7a Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Mar 30 13:00:46 2012 -0700 Align: Make sure 1 is treated as unsigned long instead of int ... and drop duplicate definition in via/epia-n code. Change-Id: Id79daaaa35c4d412c8c1f621a3638d129681d331 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/include/stdlib.h | 2 +- src/mainboard/via/epia-n/acpi_tables.c | 4 ---- 2 files changed, 1 insertions(+), 5 deletions(-) diff --git a/src/include/stdlib.h b/src/include/stdlib.h index 45420d7..5465c14 100644 --- a/src/include/stdlib.h +++ b/src/include/stdlib.h @@ -5,7 +5,7 @@ #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) -#define ALIGN(x,a) __ALIGN_MASK(x,(typeof(x))(a)-1) +#define ALIGN(x,a) __ALIGN_MASK(x,(typeof(x))(a)-1UL) #define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) #define MIN(a,b) ((a) < (b) ? (a) : (b)) diff --git a/src/mainboard/via/epia-n/acpi_tables.c b/src/mainboard/via/epia-n/acpi_tables.c index 589e14c..b4966bb 100644 --- a/src/mainboard/via/epia-n/acpi_tables.c +++ b/src/mainboard/via/epia-n/acpi_tables.c @@ -118,10 +118,6 @@ unsigned long acpi_fill_srat(unsigned long current) return current; } -#define ALIGN(x,a) __ALIGN_MASK(x,(typeof(x))(a)-1) -#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) -#define ALIGN_CURRENT current = ((current + 0x0f) & -0x10) - unsigned long write_acpi_tables(unsigned long start) { unsigned long current;

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coreboot March 2012