coreboot March 2012

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Patch merged into coreboot/master: ae57bd0 Fix issues with x86 memcpy
by gerrit＠coreboot.org 31 Mar '12

31 Mar '12

the following patch was just integrated into master: commit ae57bd02ee4fd5636db10dd180f5d5c622d7e4ed Author: Mathias Krause <minipli(a)googlemail.com> Date: Sat Mar 31 17:23:53 2012 +0200 Fix issues with x86 memcpy The x86 memcpy() implementation did not mention its implicit output registers ESI, EDI and ECX which might make this code miscompile when the compiler uses the value of EDI for the return value *after* the 'rep movsb' has completed. That would break the API of memcpy as this would return 'dst+len' instead of 'dst'. Fix this possible bug by removing the wrong comment and listing all output registers as such (using dummy stack variables that get optimized away). Also the leading 'cld' is superflous as the ABI mandates the direction flag to be cleared all the time when we're in C (see <http://gcc.gnu.org/gcc-4.3/changes.html>) and we have no ASM call sites that might require it to be cleared explicitly (SMM might come to mind, but it clears the DF itself before passing control to the C part of the SMI handler). Last but not least fix the prototype to match the one from <string.h>. Change-Id: I106422d41180c4ed876078cabb26b45e49f3fa93 Signed-off-by: Mathias Krause <minipli(a)googlemail.com> Build-Tested: build bot (Jenkins) at Sat Mar 31 18:09:56 2012, giving +1 Reviewed-By: Peter Stuge <peter(a)stuge.se> at Sat Mar 31 20:26:20 2012, giving +2 See http://review.coreboot.org/836 for details. -gerrit

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Patch merged into coreboot/master: 6fa3096 Whitespace fixes
by gerrit＠coreboot.org 31 Mar '12

31 Mar '12

the following patch was just integrated into master: commit 6fa3096d7e308c9a5e1abeb5a66b662d1220366c Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Mar 31 13:08:12 2012 +0200 Whitespace fixes Change-Id: I441326ecbda72ec7e99fc99bf40a81aa7e94ee26 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Build-Tested: build bot (Jenkins) at Sat Mar 31 13:54:52 2012, giving +1 Reviewed-By: Mathias Krause <minipli(a)googlemail.com> at Sat Mar 31 18:05:43 2012, giving +2 See http://review.coreboot.org/834 for details. -gerrit

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Patch set updated for coreboot: ae57bd0 Fix issues with x86 memcpy
by Mathias Krause 31 Mar '12

31 Mar '12

Mathias Krause (minipli(a)googlemail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/836 -gerrit commit ae57bd02ee4fd5636db10dd180f5d5c622d7e4ed Author: Mathias Krause <minipli(a)googlemail.com> Date: Sat Mar 31 17:23:53 2012 +0200 Fix issues with x86 memcpy The x86 memcpy() implementation did not mention its implicit output registers ESI, EDI and ECX which might make this code miscompile when the compiler uses the value of EDI for the return value *after* the 'rep movsb' has completed. That would break the API of memcpy as this would return 'dst+len' instead of 'dst'. Fix this possible bug by removing the wrong comment and listing all output registers as such (using dummy stack variables that get optimized away). Also the leading 'cld' is superflous as the ABI mandates the direction flag to be cleared all the time when we're in C (see <http://gcc.gnu.org/gcc-4.3/changes.html>) and we have no ASM call sites that might require it to be cleared explicitly (SMM might come to mind, but it clears the DF itself before passing control to the C part of the SMI handler). Last but not least fix the prototype to match the one from <string.h>. Change-Id: I106422d41180c4ed876078cabb26b45e49f3fa93 Signed-off-by: Mathias Krause <minipli(a)googlemail.com> --- src/arch/x86/lib/memcpy.c | 20 +++++++++++--------- 1 files changed, 11 insertions(+), 9 deletions(-) diff --git a/src/arch/x86/lib/memcpy.c b/src/arch/x86/lib/memcpy.c index de21092..f8607cf 100644 --- a/src/arch/x86/lib/memcpy.c +++ b/src/arch/x86/lib/memcpy.c @@ -1,13 +1,15 @@ #include <string.h> -void *memcpy(void *__restrict __dest, - __const void *__restrict __src, size_t __n) +void *memcpy(void *dest, const void *src, size_t n) { - asm("cld\n" - "rep\n" - "movsb" - : /* no input (?) */ - :"S"(__src), "D"(__dest), "c"(__n) - ); - return __dest; + unsigned long d0, d1, d2; + + asm volatile( + "rep movsb" + : "=S"(d0), "=D"(d1), "=c"(d2) + : "0"(src), "1"(dest), "2"(n) + : "memory" + ); + + return dest; }

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New patch to review for coreboot: 6d4e711 Fix issues with x86 memcpy
by Mathias Krause 31 Mar '12

31 Mar '12

Mathias Krause (minipli(a)googlemail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/836 -gerrit commit 6d4e71183f1238bc7e655122a5f733adc02e5088 Author: Mathias Krause <minipli(a)googlemail.com> Date: Sat Mar 31 17:23:53 2012 +0200 Fix issues with x86 memcpy The x86 memcpy() implementation did not mention its implicit output registers ESI, EDI and ECX which might make this code miscompile when the compiler uses the value of EDI for the return value *after* the 'rep movsb' has completed. That would break the API of memcpy as this would return 'dst+len' instead of 'dst'. Fix this possible bug by removing the wrong comment and listing all output registers as such (using dummy stack variables that get optimized away). Also fix the prototype to match the one from <string.h>. Change-Id: I106422d41180c4ed876078cabb26b45e49f3fa93 Signed-off-by: Mathias Krause <minipli(a)googlemail.com> --- src/arch/x86/lib/memcpy.c | 20 +++++++++++--------- 1 files changed, 11 insertions(+), 9 deletions(-) diff --git a/src/arch/x86/lib/memcpy.c b/src/arch/x86/lib/memcpy.c index de21092..f8607cf 100644 --- a/src/arch/x86/lib/memcpy.c +++ b/src/arch/x86/lib/memcpy.c @@ -1,13 +1,15 @@ #include <string.h> -void *memcpy(void *__restrict __dest, - __const void *__restrict __src, size_t __n) +void *memcpy(void *dest, const void *src, size_t n) { - asm("cld\n" - "rep\n" - "movsb" - : /* no input (?) */ - :"S"(__src), "D"(__dest), "c"(__n) - ); - return __dest; + unsigned long d0, d1, d2; + + asm volatile( + "rep movsb" + : "=S"(d0), "=D"(d1), "=c"(d2) + : "0"(src), "1"(dest), "2"(n) + : "memory" + ); + + return dest; }

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New patch to review for coreboot: 6fa3096 Whitespace fixes
by Patrick Georgi 31 Mar '12

31 Mar '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/834 -gerrit commit 6fa3096d7e308c9a5e1abeb5a66b662d1220366c Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Mar 31 13:08:12 2012 +0200 Whitespace fixes Change-Id: I441326ecbda72ec7e99fc99bf40a81aa7e94ee26 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/cpu/Kconfig | 2 +- src/cpu/intel/car/cache_as_ram_ht.inc | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index 0bdef34..ec10a97 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -36,7 +36,7 @@ config AP_SIPI_VECTOR default 0xfffff000 help This must equal address of ap_sipi_vector from bootblock build. - + config MMX bool help diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index 0d1b2a6..32efc41 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -128,7 +128,7 @@ bsp_init: jnz 1b post_code(0x24) - + /* For a hyper-threading processor, cache must not be disabled * on an AP on the same physical package with the BSP. */

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New patch to review for coreboot: dabe845 Replace cache control magic numbers with symbols
by Patrick Georgi 31 Mar '12

31 Mar '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/833 -gerrit commit dabe8452d2f6481597243b8c425645b2d3ce971a Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Mar 31 12:52:21 2012 +0200 Replace cache control magic numbers with symbols Instead of opaque numbers like (1<<29), use symbols like MTRRdefNoWriteThrough. Change-Id: Id845e087fb472cfaf5f71beaf37fbf0d407880b5 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/cpu/amd/car/cache_as_ram.inc | 2 +- src/cpu/amd/car/disable_cache_as_ram.c | 2 +- src/cpu/intel/car/cache_as_ram.inc | 6 +++--- src/cpu/intel/car/cache_as_ram_ht.inc | 16 ++++++++-------- src/cpu/intel/model_106cx/cache_as_ram.inc | 14 +++++++------- src/cpu/intel/model_6ex/cache_as_ram.inc | 14 +++++++------- src/cpu/intel/model_6fx/cache_as_ram.inc | 14 +++++++------- src/cpu/via/car/cache_as_ram.inc | 8 ++++---- src/include/cpu/x86/mtrr.h | 2 ++ 9 files changed, 40 insertions(+), 38 deletions(-) diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 4625da1..b0ad62b 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -320,7 +320,7 @@ wbcache_post_fam10_setup: /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(MTRRdefCacheDisable | MTRRdefNoWriteThrough)), %eax movl %eax, %cr0 jmp_if_k8(fam10_end_part1) diff --git a/src/cpu/amd/car/disable_cache_as_ram.c b/src/cpu/amd/car/disable_cache_as_ram.c index 0f91154..38edf63 100644 --- a/src/cpu/amd/car/disable_cache_as_ram.c +++ b/src/cpu/amd/car/disable_cache_as_ram.c @@ -26,7 +26,7 @@ static inline __attribute__((always_inline)) void disable_cache_as_ram(void) msr_t msr; /* disable cache */ - write_cr0(read_cr0() | (1 << 30)); + write_cr0(read_cr0() | MTRRdefCacheDisable); msr.lo = 0; msr.hi = 0; diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc index 7742a68..60536b7 100644 --- a/src/cpu/intel/car/cache_as_ram.inc +++ b/src/cpu/intel/car/cache_as_ram.inc @@ -254,7 +254,7 @@ clear_fixed_var_mtrr_out: /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(MTRRdefCacheDisable | MTRRdefNoWriteThrough)), %eax movl %eax, %cr0 /* Read the range with lodsl. */ @@ -328,7 +328,7 @@ lout: /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $MTRRdefCacheDisable, %eax movl %eax, %cr0 /* Clear sth. */ @@ -353,7 +353,7 @@ lout: /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(MTRRdefCacheDisable | MTRRdefNoWriteThrough)), %eax movl %eax, %cr0 /* Clear boot_complete flag. */ diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index 2485e20..0d1b2a6 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -188,7 +188,7 @@ ap_init: /* Do not disable cache (so BSP can enable it). */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(MTRRdefCacheDisable | MTRRdefNoWriteThrough)), %eax movl %eax, %cr0 post_code(0x28) @@ -271,7 +271,7 @@ no_msr_11e: /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(MTRRdefCacheDisable | MTRRdefNoWriteThrough)), %eax invd movl %eax, %cr0 @@ -284,7 +284,7 @@ no_msr_11e: /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $MTRRdefCacheDisable, %eax movl %eax, %cr0 post_code(0x2d) @@ -310,7 +310,7 @@ no_msr_11e: /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(MTRRdefCacheDisable | MTRRdefNoWriteThrough)), %eax movl %eax, %cr0 post_code(0x2e) @@ -338,7 +338,7 @@ no_msr_11e: /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $MTRRdefCacheDisable, %eax movl %eax, %cr0 post_code(0x34) @@ -357,14 +357,14 @@ no_msr_11e: /* Enable cache. */ movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax + andl $~(MTRRdefCacheDisable | MTRRdefNoWriteThrough), %eax movl %eax, %cr0 post_code(0x37) /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $MTRRdefCacheDisable, %eax movl %eax, %cr0 post_code(0x38) @@ -393,7 +393,7 @@ no_msr_11e: /* And enable cache again after setting MTRRs. */ movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax + andl $~(MTRRdefCacheDisable | MTRRdefNoWriteThrough), %eax movl %eax, %cr0 post_code(0x3a) diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc index caf5d03..ca717ec 100644 --- a/src/cpu/intel/model_106cx/cache_as_ram.inc +++ b/src/cpu/intel/model_106cx/cache_as_ram.inc @@ -84,7 +84,7 @@ clear_mtrrs: /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(MTRRdefCacheDisable | MTRRdefNoWriteThrough)), %eax invd movl %eax, %cr0 @@ -98,7 +98,7 @@ clear_mtrrs: /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $MTRRdefCacheDisable, %eax movl %eax, %cr0 #if CONFIG_XIP_ROM_SIZE @@ -122,7 +122,7 @@ clear_mtrrs: /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(MTRRdefCacheDisable | MTRRdefNoWriteThrough)), %eax movl %eax, %cr0 /* Set up the stack pointer. */ @@ -150,7 +150,7 @@ clear_mtrrs: /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $MTRRdefCacheDisable, %eax movl %eax, %cr0 post_code(0x31) @@ -181,14 +181,14 @@ clear_mtrrs: /* Enable cache. */ movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax + andl $~(MTRRdefCacheDisable | MTRRdefNoWriteThrough), %eax movl %eax, %cr0 post_code(0x36) /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $MTRRdefCacheDisable, %eax movl %eax, %cr0 post_code(0x38) @@ -207,7 +207,7 @@ clear_mtrrs: /* And enable cache again after setting MTRRs. */ movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax + andl $~(MTRRdefCacheDisable | MTRRdefNoWriteThrough), %eax movl %eax, %cr0 post_code(0x3a) diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index 08f5b11..702ced5 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -84,7 +84,7 @@ clear_mtrrs: /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(MTRRdefCacheDisable | MTRRdefNoWriteThrough)), %eax invd movl %eax, %cr0 @@ -98,7 +98,7 @@ clear_mtrrs: /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $MTRRdefCacheDisable, %eax movl %eax, %cr0 #if CONFIG_XIP_ROM_SIZE @@ -122,7 +122,7 @@ clear_mtrrs: /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(MTRRdefCacheDisable | MTRRdefNoWriteThrough)), %eax movl %eax, %cr0 /* Set up the stack pointer. */ @@ -150,7 +150,7 @@ clear_mtrrs: /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $MTRRdefCacheDisable, %eax movl %eax, %cr0 post_code(0x31) @@ -181,14 +181,14 @@ clear_mtrrs: /* Enable cache. */ movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax + andl $~(MTRRdefCacheDisable | MTRRdefNoWriteThrough), %eax movl %eax, %cr0 post_code(0x36) /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $MTRRdefCacheDisable, %eax movl %eax, %cr0 post_code(0x38) @@ -217,7 +217,7 @@ clear_mtrrs: /* And enable cache again after setting MTRRs. */ movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax + andl $~(MTRRdefCacheDisable | MTRRdefNoWriteThrough), %eax movl %eax, %cr0 post_code(0x3a) diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc index 25d8de2..e11c523 100644 --- a/src/cpu/intel/model_6fx/cache_as_ram.inc +++ b/src/cpu/intel/model_6fx/cache_as_ram.inc @@ -91,7 +91,7 @@ clear_mtrrs: /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(MTRRdefCacheDisable | MTRRdefNoWriteThrough)), %eax invd movl %eax, %cr0 @@ -105,7 +105,7 @@ clear_mtrrs: /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $MTRRdefCacheDisable, %eax movl %eax, %cr0 #if CONFIG_XIP_ROM_SIZE @@ -129,7 +129,7 @@ clear_mtrrs: /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(MTRRdefCacheDisable | MTRRdefNoWriteThrough)), %eax movl %eax, %cr0 /* Set up the stack pointer. */ @@ -157,7 +157,7 @@ clear_mtrrs: /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $MTRRdefCacheDisable, %eax movl %eax, %cr0 post_code(0x31) @@ -188,14 +188,14 @@ clear_mtrrs: /* Enable cache. */ movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax + andl $~(MTRRdefCacheDisable | MTRRdefNoWriteThrough), %eax movl %eax, %cr0 post_code(0x36) /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $MTRRdefCacheDisable, %eax movl %eax, %cr0 post_code(0x38) @@ -214,7 +214,7 @@ clear_mtrrs: /* And enable cache again after setting MTRRs. */ movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax + andl $~(MTRRdefCacheDisable | MTRRdefNoWriteThrough), %eax movl %eax, %cr0 post_code(0x3a) diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc index 90e6d2b..26b55e6 100644 --- a/src/cpu/via/car/cache_as_ram.inc +++ b/src/cpu/via/car/cache_as_ram.inc @@ -39,7 +39,7 @@ CacheAsRam: /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $MTRRdefCacheDisable, %eax movl %eax, %cr0 invd @@ -139,7 +139,7 @@ clear_fixed_var_mtrr_out: /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(MTRRdefCacheDisable | MTRRdefNoWriteThrough)), %eax movl %eax, %cr0 /* Read the range with lodsl. */ @@ -219,7 +219,7 @@ testok: /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $MTRRdefCacheDisable, %eax movl %eax, %cr0 /* Set the default memory type and enable variable MTRRs. */ @@ -259,7 +259,7 @@ testok: /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(MTRRdefCacheDisable | MTRRdefNoWriteThrough)), %eax movl %eax, %cr0 invd diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 8b5cc28..1299a9e 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -14,6 +14,8 @@ #define MTRRcap_MSR 0x0fe #define MTRRdefType_MSR 0x2ff +#define MTRRdefCacheDisable (1 << 30) +#define MTRRdefNoWriteThrough (1 << 29) #define MTRRdefTypeEn (1 << 11) #define MTRRdefTypeFixEn (1 << 10)

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Patch merged into coreboot/master: 76db020 Update xcompile to search for x86_64 toolchain.
by gerrit＠coreboot.org 31 Mar '12

31 Mar '12

the following patch was just integrated into master: commit 76db020f22bbe48c3cc78fd4ec5f8b77c66ceed6 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Wed Feb 22 11:46:17 2012 -0700 Update xcompile to search for x86_64 toolchain. This adds detection of x86_64 gcc toolchain (which buildgcc can build if provided the option). Change-Id: I8b12f3e705157741279c7347f4847fb50ccc2b0e Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/673 for details. -gerrit

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Patch merged into coreboot/master: 7b1da0f Make libpayload parse the coreboot tables before setting up the consoles
by gerrit＠coreboot.org 31 Mar '12

31 Mar '12

the following patch was just integrated into master: commit 7b1da0fb2b5dbc8cc7269811ac36bf52f3635b15 Author: Gabe Black <gabeblack(a)google.com> Date: Mon Mar 5 15:49:32 2012 -0800 Make libpayload parse the coreboot tables before setting up the consoles At least one of the console drivers, coreboot fb, uses information in the sysinfo structure to set itself up. If that structure hasn't been populated, the driver decides that there is no framebuffer and disables itself. Reversing the order these are set up fixes that problem. Change-Id: Idd8b5518980dfdd82fd4359dd0133ab7736fc428 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Sat Mar 31 12:10:00 2012, giving +2 See http://review.coreboot.org/816 for details. -gerrit

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Patch merged into coreboot/master: 0afabb9 Enable -Werror for romcc
by gerrit＠coreboot.org 31 Mar '12

31 Mar '12

the following patch was just integrated into master: commit 0afabb90a9f893e37097e0c393efe2d3f1f4cd94 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Mar 30 12:11:04 2012 -0700 Enable -Werror for romcc ... and remove some dead code. Change-Id: Id959bdf57af09db2a1f5742555c2dcabca38ac9a Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Sat Mar 31 12:07:09 2012, giving +2 See http://review.coreboot.org/818 for details. -gerrit

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Patch merged into coreboot/master: d9dd44c Keep cscope.out when distclean.
by gerrit＠coreboot.org 31 Mar '12

31 Mar '12

the following patch was just integrated into master: commit d9dd44c7d484839d8c9398e06eeca6505de7cb19 Author: zbao <zheng.bao(a)amd.com> Date: Fri Mar 23 10:26:28 2012 +0800 Keep cscope.out when distclean. It doesnt make sense to delete cscope.out when make distclean. Distclean is done all the time, and cscope database is also needed all the time. If we need to delete all the untracked files, we can use git-clean. Change-Id: Ic248ccd602ddc88d0b98d5d7f6cbbf530cd82e87 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Sat Mar 31 12:06:07 2012, giving +2 See http://review.coreboot.org/831 for details. -gerrit

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coreboot March 2012