coreboot October 2012

coreboot@coreboot.org

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312 discussions

New patch to review for coreboot: 72e17d2 Fix ExecuteFinalHltInstruction function in f15h family code
by Aladyshev Konstantin 08 Oct '12

08 Oct '12

Aladyshev Konstantin (kostr(a)list.ru) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1569 -gerrit commit 72e17d2d302bf07df3c18a7814de0419de9bb48d Author: Kostr <aladyshev(a)nicevt.ru> Date: Mon Oct 8 22:04:53 2012 +0400 Fix ExecuteFinalHltInstruction function in f15h family code Current ExecuteFinalHltInstruction function doesn't work well. (at least in configuration Supermicro board with Orochi AMD Opteron processors (model OS6234WKTCGGU)) System reboots when trying to halt core 2,4,6,8 or 10 (OS6234WKTCGGU is 12 core processor) Based on this information, i think that code doesn't really work with f15 compute unit (CU) system. Replacing ExecuteFinalHltInstruction function with analogous function from f15tn family code fix this problem. Both functions written from the same cahalt.asm file, but f15tn version seems more completed Change-Id: I3942abcdf21f1b86a44c01cc477714e44a40b9cf Signed-off-by: Kostr <aladyshev(a)nicevt.ru> --- src/vendorcode/amd/agesa/f15/Makefile.inc | 1 + src/vendorcode/amd/agesa/f15/Proc/CPU/cahalt.c | 146 --------------- src/vendorcode/amd/agesa/f15/Proc/CPU/cahaltasm.S | 209 ++++++++++++++++++++++ src/vendorcode/amd/agesa/f15/gcccar.inc | 15 ++ 4 files changed, 225 insertions(+), 146 deletions(-) diff --git a/src/vendorcode/amd/agesa/f15/Makefile.inc b/src/vendorcode/amd/agesa/f15/Makefile.inc index 1f3ba51..0762b08 100644 --- a/src/vendorcode/amd/agesa/f15/Makefile.inc +++ b/src/vendorcode/amd/agesa/f15/Makefile.inc @@ -88,6 +88,7 @@ agesa_lib_src += ./Proc/Common/CommonReturns.c agesa_lib_src += ./Proc/Common/CreateStruct.c agesa_lib_src += ./Proc/Common/S3RestoreState.c agesa_lib_src += ./Proc/Common/S3SaveState.c +agesa_lib_src += ./Proc/CPU/cahaltasm.S agesa_lib_src += ./Proc/CPU/cahalt.c agesa_lib_src += ./Proc/CPU/cpuApicUtilities.c agesa_lib_src += ./Proc/CPU/cpuBist.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cahalt.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/cahalt.c index e204a49..68ca272 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cahalt.c +++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/cahalt.c @@ -102,152 +102,6 @@ ExecuteWbinvdInstruction ( */ -//---------------------------------------------------------------------------- - -STATIC -VOID -PrimaryCoreFunctions (AP_MTRR_SETTINGS *ApMtrrSettingsList) - { - UINT64 data; - UINT32 msrno; - // Configure the MTRRs on the AP so - // when it runs remote code it will execute - // out of RAM instead of ROM. - // Disable MTRRs and turn on modification enable bit - - data = __readmsr (0xC0010010); // MTRR_SYS_CFG - data &= ~(1 << 18); // MtrrFixDramEn - data &= ~(1 << 20); // MtrrVarDramEn - data |= (1 << 19); // MtrrFixDramModEn - data |= (1 << 17); // SysUcLockEn - - - __writemsr (0xC0010010, data); - - // Set 7FFFh-00000h and 9FFFFh-80000h as WB DRAM - __writemsr (0x250, 0x1E1E1E1E1E1E1E1E); // AMD_MTRR_FIX64k_00000 - __writemsr (0x258, 0x1E1E1E1E1E1E1E1E); // AMD_MTRR_FIX16k_80000 - - // Set BFFFFh-A0000h, DFFFFh-C0000h as Uncacheable Memory-mapped IO - __writemsr (0x259, 0); // AMD_AP_MTRR_FIX16k_A0000 - __writemsr (0x268, 0); // AMD_MTRR_FIX4k_C0000 - __writemsr (0x269, 0); // AMD_MTRR_FIX4k_C8000 - __writemsr (0x26A, 0); // AMD_MTRR_FIX4k_D0000 - __writemsr (0x26B, 0); // AMD_MTRR_FIX4k_D8000 - - // Set FFFFFh-E0000h as Uncacheable Memory - for (msrno = 0x26C; msrno <= 0x26F; msrno++) - __writemsr (msrno, 0x1818181818181818); - - // If IBV provided settings for Fixed-Sized MTRRs, - // overwrite the default settings. - if ((uintptr_t) ApMtrrSettingsList != 0 && (uintptr_t) ApMtrrSettingsList != 0xFFFFFFFF) - { - int index; - for (index = 0; ApMtrrSettingsList [index].MsrAddr != CPU_LIST_TERMINAL; index++) - __writemsr (ApMtrrSettingsList [index].MsrAddr, ApMtrrSettingsList [index].MsrData); - } - - // restore variable MTTR6 and MTTR7 to default states - for (msrno = 0x20F; msrno <= 0x20C; msrno--) // decrement so that the pair is disable before the base is cleared - __writemsr (msrno, 0); - - // Enable fixed-range and variable-range MTRRs - // Set Fixed-Range Enable (FE) and MTRR Enable (E) bits - __writemsr (0x2FF, __readmsr (0x2FF) | 0xC00); - - // Enable Top-of-Memory setting - // Enable use of RdMem/WrMem bits attributes - data = __readmsr (0xC0010010); // MTRR_SYS_CFG - data |= (1 << 18); // MtrrFixDramEn - data |= (1 << 20); // MtrrVarDramEn - data &= ~(1 << 19); // MtrrFixDramModEn - __writemsr (0xC0010010, data); - } - -//---------------------------------------------------------------------------- - -VOID -ExecuteFinalHltInstruction ( - IN UINT32 SharedCore, - IN AP_MTRR_SETTINGS *ApMtrrSettingsList, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - int abcdRegs [4]; - UINT32 cr0val; - UINT64 data; - - cr0val = __readcr0 (); - if (SharedCore & 2) - { - // set CombineCr0Cd and enable cache in CR0 - __writemsr (MSR_CU_CFG3, __readmsr (MSR_CU_CFG3) | 1ULL << 49); - __writecr0 (cr0val & ~0x60000000); - } - else - __writecr0 (cr0val | 0x60000000); - - if (SharedCore & 1) PrimaryCoreFunctions (ApMtrrSettingsList); - - // Make sure not to touch any Shared MSR from this point on - - // Restore settings that were temporarily overridden for the cache as ram phase - data = __readmsr (0xC0011022); // MSR_DC_CFG - data &= ~(1 << 4); // DC_DIS_SPEC_TLB_RLD - data &= ~(1 << 8); // DIS_CLR_WBTOL2_SMC_HIT - data &= ~(1 << 13); // DIS_HW_PF - __writemsr (0xC0011022, data); - - data = __readmsr (0xC0011021); // MSR_IC_CFG - C001_1021 - data &= ~(1 << 9); // IC_DIS_SPEC_TLB_RLD - __writemsr (0xC0011021, data); - - // AMD_DISABLE_STACK_FAMILY_HOOK - __cpuid (abcdRegs, 1); - if ((abcdRegs [0] >> 20) == 1) //-----family 10h (Hydra) only----- - { - data = __readmsr (0xC0011022); - data &= ~(1 << 4); - data &= ~(1 << 8); - data &= ~(1 << 13); - __writemsr (0xC0011022, data); - - data = __readmsr (0xC0011021); - data &= ~(1 << 14); - data &= ~(1 << 9); - __writemsr (0xC0011021, data); - - data = __readmsr (0xC001102A); - data &= ~(1 << 15); - data &= ~(1ull << 35); - __writemsr (0xC001102A, data); - } - else if ((abcdRegs [0] >> 20) == 6) //-----family 15h (Orochi) only----- - { - data = __readmsr (0xC0011020); - data &= ~(1 << 28); - __writemsr (0xC0011020, data); - - data = __readmsr (0xC0011021); - data &= ~(1 << 9); - __writemsr (0xC0011021, data); - - data = __readmsr (0xC0011022); - data &= ~(1 << 4); - data &= ~(1l << 13); - __writemsr (0xC0011022, data); - } - - for (;;) - { - _disable (); - __halt (); - } - } - -//---------------------------------------------------------------------------- - /// Structure needed to load the IDTR using the lidt instruction VOID diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cahaltasm.S b/src/vendorcode/amd/agesa/f15/Proc/CPU/cahaltasm.S new file mode 100644 index 0000000..4ab535a --- /dev/null +++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/cahaltasm.S @@ -0,0 +1,209 @@ +/* + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +.include "src/vendorcode/amd/agesa/f15tn/gcccar.inc" + +.code32 +.align 4 +.globl ExecuteFinalHltInstruction + .type ExecuteFinalHltInstruction, @function +/* ExecuteFinalHltInstruction ( + IN UINT32 HaltFlags, + IN AP_MTRR_SETTINGS *ApMtrrSettingsList, + IN AMD_CONFIG_PARAMS *StdHeader + ) +*/ + +/* This function disables CAR. We don't care about the stack on this CPU */ +ExecuteFinalHltInstruction: + movl 4(%esp), %esi /* HaltFlags*/ + movl 8(%esp), %edi /* ApMtrrSettingList */ +//1: jmp 1b //good +/* Do these special steps in case if the core is part of a compute unit + * Note: The following bits are family specific flags, that gets set during build time, + * and indicates things like "family cache control methodology", etc. + * esi bit0 = 0 -> not a Primary core + * esi bit0 = 1 -> Primary core + * esi bit1 = 0 -> Cache disable + * esi bit1 = 1 -> Cache enable + */ + + bt $1, %esi /* .if (esi & 2h) */ + jz 0f + /* Set CombineCr0Cd bit */ + movl $CU_CFG3, %ecx + rdmsr + bts $(COMBINE_CR0_CD - 32), %edx + wrmsr + /* Clear the CR0.CD bit */ + movl %cr0, %eax /* Make sure cache is enabled for all APs */ + btr $CR0_CD, %eax + btr $CR0_NW, %eax + mov %eax, %cr0 /* Write back to CR0 */ + jmp 1f /* .else */ +0: + movl %cr0, %eax /* Make sure cache is disabled for all APs */ + bts $CR0_CD, %eax /* Disable cache */ + bts $CR0_NW, %eax + movl %eax, %cr0 /* Write back to CR0 */ +1: /* .endif */ + +// jmp 1b + bt $0, %esi /* .if (esi & 1h) */ + jz 2f + /* This core is a primary core and needs to do all the MTRRs, including shared MTRRs. */ + movl %edi, %esi /* Get ApMtrrSettingList */ + + /* Configure the MTRRs on the AP so + * when it runs remote code it will execute + * out of RAM instead of ROM. + */ + + /* Disable MTRRs and turn on modification enable bit */ + movl $MTRR_SYS_CFG, %ecx + rdmsr + /* TODO: why comment this? */ + //btr $MTRR_VAR_DRAM_EN, %eax /* Disable */ + bts $MTRR_FIX_DRAM_MOD_EN, %eax /* Enable */ + btr $MTRR_FIX_DRAM_EN, %eax /* Disable */ + //bts $SYS_UC_LOCK_EN, %eax + wrmsr + + /* Setup default values for Fixed-Sized MTRRs */ + /* Set 7FFFh-00000h as WB */ + movl $AMD_AP_MTRR_FIX64k_00000, %ecx + movl $0x1E1E1E1E, %eax + movl %eax, %edx + wrmsr + + /* Set 9FFFFh-80000h also as WB */ + movl $AMD_AP_MTRR_FIX16k_80000, %ecx + wrmsr + + /* Set BFFFFh-A0000h as Uncacheable Memory-mapped IO */ + movl $AMD_AP_MTRR_FIX16k_A0000, %ecx + xorl %eax, %eax + xorl %edx, %edx + wrmsr + + /* Set DFFFFh-C0000h as Uncacheable Memory-mapped IO */ + xorl %eax, %eax + xorl %edx, %edx + movl $AMD_AP_MTRR_FIX4k_C0000, %ecx + +CDLoop: + wrmsr + inc %ecx + cmp $AMD_AP_MTRR_FIX4k_D8000, %ecx + jbe CDLoop + + /* Set FFFFFh-E0000h as Uncacheable Memory */ + movl $0x18181818, %eax + movl %eax, %edx + + mov $AMD_AP_MTRR_FIX4k_E0000, %ecx + +EFLoop: + wrmsr + inc %ecx + cmp $AMD_AP_MTRR_FIX4k_F8000, %ecx + jbe EFLoop + + /* If IBV provided settings for Fixed-Sized MTRRs, + * overwrite the default settings. */ + cmp $0, %esi /*.if ((esi != 0) && (esi != 0FFFFFFFFh)) */ + jz 4f + cmp $0xFFFFFFFF, %esi + jz 4f + 5: + mov (%esi), %ecx /* (AP_MTRR_SETTINGS ptr [esi]).MsrAddr */ + /* While we are not at the end of the list */ + cmp $CPU_LIST_TERMINAL, %ecx /* .while (ecx != CPU_LIST_TERMINAL)*/ + je 4f + /* TODO - coreboot isn't checking for valid data. + * Ensure that the MSR address is valid for Fixed-Sized MTRRs */ + /*.if ( ((ecx >= AMD_AP_MTRR_FIX4k_C0000) && (ecx <= AMD_AP_MTRR_FIX4k_F8000)) || \ + (ecx == AMD_AP_MTRR_FIX64k_00000) || (ecx == AMD_AP_MTRR_FIX16k_80000 ) || \ + (ecx == AMD_AP_MTRR_FIX16k_A0000)) + */ + mov 4(%esi), %eax /* MsrData */ + mov 8(%esi), %edx /* MsrData */ + wrmsr + /* .endif */ + add $12, %esi /* sizeof (AP_MTRR_SETTINGS) */ + jmp 5b /* .endw */ + 4: /* .endif */ + + /* Enable fixed-range and variable-range MTRRs */ + mov $AMD_MTRR_DEFTYPE, %ecx + rdmsr + bts $MTRR_DEF_TYPE_EN, %eax /* MtrrDefTypeEn */ + bts $MTRR_DEF_TYPE_FIX_EN, %eax /* MtrrDefTypeFixEn */ + wrmsr + + /* Enable Top-of-Memory setting */ + /* Enable use of RdMem/WrMem bits attributes */ + mov $MTRR_SYS_CFG, %ecx + rdmsr + /* TODO: */ + //bts $MTRR_VAR_DRAM_EN, %eax /* Enable */ + btr $MTRR_FIX_DRAM_MOD_EN, %eax /* Disable */ + bts $MTRR_FIX_DRAM_EN, %eax /* Enable */ + wrmsr + + bts $FLAG_IS_PRIMARY, %esi + jmp 3f /* .else ; end if primary core */ + 2: + xor %esi, %esi + 3: /* .endif*/ + +//8: jmp 8b //bad + /* Make sure not to touch any Shared MSR from this point on */ + + AMD_DISABLE_STACK_FAMILY_HOOK + + /* restore variable MTTR6 and MTTR7 to default states */ + bt $FLAG_IS_PRIMARY, %esi /* .if (esi & 1h) */ + jz 6f + movl $AMD_MTRR_VARIABLE_MASK7, %ecx /* clear MTRRPhysBase6 MTRRPhysMask6 */ + xor %eax, %eax /* and MTRRPhysBase7 MTRRPhysMask7 */ + xor %edx, %edx + cmp $AMD_MTRR_VARIABLE_BASE6, %ecx /* .while (cl < 010h) */ + jl 6f + wrmsr + dec %ecx + 6: /* .endw */ + + xor %eax, %eax + +7: + cli + hlt + jmp 7b /* ExecuteHltInstruction */ + + .size ExecuteFinalHltInstruction, .-ExecuteFinalHltInstruction diff --git a/src/vendorcode/amd/agesa/f15/gcccar.inc b/src/vendorcode/amd/agesa/f15/gcccar.inc index 07e3285..423d404 100644 --- a/src/vendorcode/amd/agesa/f15/gcccar.inc +++ b/src/vendorcode/amd/agesa/f15/gcccar.inc @@ -49,6 +49,7 @@ APIC_BASE_ADDRESS = 0x0000001B AMD_MTRR_VARIABLE_BASE0 = 0x0200 AMD_MTRR_VARIABLE_BASE6 = 0x020C +AMD_MTRR_VARIABLE_MASK7 = 0x020F AMD_MTRR_FIX64k_00000 = 0x0250 AMD_MTRR_FIX16k_80000 = 0x0258 AMD_MTRR_FIX16k_A0000 = 0x0259 @@ -61,6 +62,20 @@ AMD_MTRR_FIX4k_E8000 = 0x026D AMD_MTRR_FIX4k_F0000 = 0x026E AMD_MTRR_FIX4k_F8000 = 0x026F +/* Reproduced from AGESA.h */ +AMD_AP_MTRR_FIX64k_00000 = 0x00000250 +AMD_AP_MTRR_FIX16k_80000 = 0x00000258 +AMD_AP_MTRR_FIX16k_A0000 = 0x00000259 +AMD_AP_MTRR_FIX4k_C0000 = 0x00000268 +AMD_AP_MTRR_FIX4k_C8000 = 0x00000269 +AMD_AP_MTRR_FIX4k_D0000 = 0x0000026A +AMD_AP_MTRR_FIX4k_D8000 = 0x0000026B +AMD_AP_MTRR_FIX4k_E0000 = 0x0000026C +AMD_AP_MTRR_FIX4k_E8000 = 0x0000026D +AMD_AP_MTRR_FIX4k_F0000 = 0x0000026E +AMD_AP_MTRR_FIX4k_F8000 = 0x0000026F +CPU_LIST_TERMINAL = 0xFFFFFFFF + AMD_MTRR_DEFTYPE = 0x02FF WB_DRAM_TYPE = 0x1E /* MemType - memory type */ MTRR_DEF_TYPE_EN = 11 /* MtrrDefTypeEn - variable and fixed MTRRs default enabled */

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Re: [coreboot] USB Problems geode lx800
by Christian Gmeiner 08 Oct '12

08 Oct '12

2012/10/8 Christian Gmeiner <christian.gmeiner(a)gmail.com>: > 2012/10/8 Christian Gmeiner <christian.gmeiner(a)gmail.com>: >> HI all >> >> I am running into some usb problems with coreboot & seabios: >> >> >> init usb >> pmm_malloc zone=0x1f7afe7f handle=ffffffff size=72 align=10 >> ret=0x1f7a8860 (detail=0x1f7a88b0) >> EHCI init on dev 00:0f.5 (regs=0xfe038010) >> pmm_malloc zone=0x1f7afe83 handle=ffffffff size=4096 align=1000 >> ret=0x1f7bf000 (detail=0x1f7a8830) >> pmm_malloc zone=0x1f7afe83 handle=ffffffff size=68 align=80 >> ret=0x1f7bef80 (detail=0x1f7a8800) >> pmm_malloc zone=0x1f7afe83 handle=ffffffff size=68 align=80 >> ret=0x1f7bef00 (detail=0x1f7a87d0) >> pmm_malloc zone=0x1f7afe7f handle=ffffffff size=28 align=10 >> ret=0x1f7a8780 (detail=0x1f7a87a0) >> pmm_free 0x1f7a8780 (detail=0x1f7a87a0) >> pmm_malloc zone=0x1f7afe7f handle=ffffffff size=28 align=10 >> ret=0x1f7a8780 (detail=0x1f7a87a0) >> set_address 0x1f7a8860 >> ehci_alloc_async_pipe 0x1f7a8860 0 >> pmm_malloc zone=0x1f7afe7f handle=ffffffff size=92 align=80 >> ret=0x1f7a8680 (detail=0x1f7a8750) >> ehci_control 0x1f7a86d0 (dir=0 cmd=8 data=0) >> pmm_malloc zone=0x1f7afe7f handle=ffffffff size=192 align=40 >> ret=0x1f7a85c0 (detail=0x1f7a8720) >> pmm_free 0x1f7a85c0 (detail=0x1f7a8720) >> ehci_alloc_async_pipe 0x1f7a8860 0 >> config_usb: 0x1f7a86d0 >> ehci_control 0x1f7a86d0 (dir=128 cmd=8 data=8) >> pmm_malloc zone=0x1f7afe7f handle=ffffffff size=192 align=40 >> ret=0x1f7a85c0 (detail=0x1f7a8720) >> pmm_free 0x1f7a85c0 (detail=0x1f7a8720) >> device rev=0200 cls=00 sub=00 proto=00 size=40 >> ehci_alloc_async_pipe 0x1f7a8860 0 >> ehci_control 0x1f7a86d0 (dir=128 cmd=8 data=9) >> pmm_malloc zone=0x1f7afe7f handle=ffffffff size=192 align=40 >> ret=0x1f7a85c0 (detail=0x1f7a8720) >> pmm_free 0x1f7a85c0 (detail=0x1f7a8720) >> pmm_malloc zone=0x1f7afe7f handle=ffffffff size=32 align=10 >> ret=0x1f7a8700 (detail=0x1f7a8720) >> ehci_control 0x1f7a86d0 (dir=128 cmd=8 data=32) >> pmm_malloc zone=0x1f7afe7f handle=ffffffff size=192 align=40 >> ret=0x1f7a8580 (detail=0x1f7a8650) >> pmm_free 0x1f7a8580 (detail=0x1f7a8650) >> ehci_control 0x1f7a86d0 (dir=0 cmd=8 data=0) >> pmm_malloc zone=0x1f7afe7f handle=ffffffff size=192 align=40 >> ret=0x1f7a8580 (detail=0x1f7a8650) >> pmm_free 0x1f7a8580 (detail=0x1f7a8650) >> ehci_alloc_async_pipe 0x1f7a8860 2 >> pmm_malloc zone=0x1f7afe77 handle=ffffffff size=92 align=80 >> ret=0x000ef700 (detail=0x1f7a8650) >> ehci_alloc_async_pipe 0x1f7a8860 2 >> pmm_malloc zone=0x1f7afe77 handle=ffffffff size=92 align=80 >> ret=0x000ef680 (detail=0x1f7a8620) >> ehci_control 0x1f7a86d0 (dir=128 cmd=8 data=1) >> pmm_malloc zone=0x1f7afe7f handle=ffffffff size=192 align=40 >> ret=0x1f7a8500 (detail=0x1f7a85f0) >> pmm_free 0x1f7a8500 (detail=0x1f7a85f0) >> pmm_malloc zone=0x1f7afe7b handle=ffffffff size=48 align=10 >> ret=0x000fdb30 (detail=0x1f7a85f0) >> Searching bootorder for: /pci@i0cf8/usb@f,5/storage@2/*@0/*@0,0 >> Searching bootorder for: /pci@i0cf8/usb@f,5/usb-*@2 >> ehci_send_bulk qh=0x000ef680 dir=0 data=0x00006d55 size=31 >> ehci_send_bulk qh=0x000ef700 dir=128 data=0x00006e3c size=36 >> ehci_send_bulk qh=0x000ef700 dir=128 data=0x00006d8f size=13 >> WARNING - Timeout at ehci_wait_td:542! >> ehci pipe=0x000ef700 cur=00000000 tok=00000000 next=6b80 td=0x00006b80 >> status=d0d80 >> USB transmission failed >> Unable to configure USB MSC drive. >> pmm_free 0x000fdb30 (detail=0x1f7a85f0) >> Unable to configure USB MSC device. >> pmm_free 0x1f7a8700 (detail=0x1f7a8720) >> pmm_free 0x1f7a8780 (detail=0x1f7a87a0) >> pmm_malloc zone=0x1f7afe7f handle=ffffffff size=28 align=10 >> ret=0x1f7a8780 (detail=0x1f7a87a0) >> pmm_free 0x1f7a8780 (detail=0x1f7a87a0) >> pmm_malloc zone=0x1f7afe7f handle=ffffffff size=28 align=10 >> ret=0x1f7a8780 (detail=0x1f7a87a0) >> pmm_free 0x1f7a8780 (detail=0x1f7a87a0) >> ehci_free_pipes 0x1f7a8860 >> pmm_free 0x1f7a8680 (detail=0x1f7a8750) >> pmm_free 0x000ef680 (detail=0x1f7a8620) >> pmm_free 0x000ef700 (detail=0x1f7a8650) >> pmm_free 0x1f7bf000 (detail=0x1f7a8830) >> pmm_free 0x1f7bef80 (detail=0x1f7a8800) >> pmm_free 0x1f7bef00 (detail=0x1f7a87d0) >> pmm_free 0x1f7a8860 (detail=0x1f7a88b0) >> init serial >> Found 2 serial ports >> init hard drives >> >> Mabye somebody has some hints how to start debugging this and what I >> should look for. >> > added some debug to seabios: > http://dpaste.com/811158/ > > and tired my luck with FILO (using libpayload from coreboot): > http://dpaste.com/811165/ > I can boot with FILO from usb successfully into Linux --- Christian Gmeiner, MSc

1 0

Re: [coreboot] USB Problems geode lx800
by Christian Gmeiner 08 Oct '12

08 Oct '12

2012/10/8 Christian Gmeiner <christian.gmeiner(a)gmail.com>: > HI all > > I am running into some usb problems with coreboot & seabios: > > > init usb > pmm_malloc zone=0x1f7afe7f handle=ffffffff size=72 align=10 > ret=0x1f7a8860 (detail=0x1f7a88b0) > EHCI init on dev 00:0f.5 (regs=0xfe038010) > pmm_malloc zone=0x1f7afe83 handle=ffffffff size=4096 align=1000 > ret=0x1f7bf000 (detail=0x1f7a8830) > pmm_malloc zone=0x1f7afe83 handle=ffffffff size=68 align=80 > ret=0x1f7bef80 (detail=0x1f7a8800) > pmm_malloc zone=0x1f7afe83 handle=ffffffff size=68 align=80 > ret=0x1f7bef00 (detail=0x1f7a87d0) > pmm_malloc zone=0x1f7afe7f handle=ffffffff size=28 align=10 > ret=0x1f7a8780 (detail=0x1f7a87a0) > pmm_free 0x1f7a8780 (detail=0x1f7a87a0) > pmm_malloc zone=0x1f7afe7f handle=ffffffff size=28 align=10 > ret=0x1f7a8780 (detail=0x1f7a87a0) > set_address 0x1f7a8860 > ehci_alloc_async_pipe 0x1f7a8860 0 > pmm_malloc zone=0x1f7afe7f handle=ffffffff size=92 align=80 > ret=0x1f7a8680 (detail=0x1f7a8750) > ehci_control 0x1f7a86d0 (dir=0 cmd=8 data=0) > pmm_malloc zone=0x1f7afe7f handle=ffffffff size=192 align=40 > ret=0x1f7a85c0 (detail=0x1f7a8720) > pmm_free 0x1f7a85c0 (detail=0x1f7a8720) > ehci_alloc_async_pipe 0x1f7a8860 0 > config_usb: 0x1f7a86d0 > ehci_control 0x1f7a86d0 (dir=128 cmd=8 data=8) > pmm_malloc zone=0x1f7afe7f handle=ffffffff size=192 align=40 > ret=0x1f7a85c0 (detail=0x1f7a8720) > pmm_free 0x1f7a85c0 (detail=0x1f7a8720) > device rev=0200 cls=00 sub=00 proto=00 size=40 > ehci_alloc_async_pipe 0x1f7a8860 0 > ehci_control 0x1f7a86d0 (dir=128 cmd=8 data=9) > pmm_malloc zone=0x1f7afe7f handle=ffffffff size=192 align=40 > ret=0x1f7a85c0 (detail=0x1f7a8720) > pmm_free 0x1f7a85c0 (detail=0x1f7a8720) > pmm_malloc zone=0x1f7afe7f handle=ffffffff size=32 align=10 > ret=0x1f7a8700 (detail=0x1f7a8720) > ehci_control 0x1f7a86d0 (dir=128 cmd=8 data=32) > pmm_malloc zone=0x1f7afe7f handle=ffffffff size=192 align=40 > ret=0x1f7a8580 (detail=0x1f7a8650) > pmm_free 0x1f7a8580 (detail=0x1f7a8650) > ehci_control 0x1f7a86d0 (dir=0 cmd=8 data=0) > pmm_malloc zone=0x1f7afe7f handle=ffffffff size=192 align=40 > ret=0x1f7a8580 (detail=0x1f7a8650) > pmm_free 0x1f7a8580 (detail=0x1f7a8650) > ehci_alloc_async_pipe 0x1f7a8860 2 > pmm_malloc zone=0x1f7afe77 handle=ffffffff size=92 align=80 > ret=0x000ef700 (detail=0x1f7a8650) > ehci_alloc_async_pipe 0x1f7a8860 2 > pmm_malloc zone=0x1f7afe77 handle=ffffffff size=92 align=80 > ret=0x000ef680 (detail=0x1f7a8620) > ehci_control 0x1f7a86d0 (dir=128 cmd=8 data=1) > pmm_malloc zone=0x1f7afe7f handle=ffffffff size=192 align=40 > ret=0x1f7a8500 (detail=0x1f7a85f0) > pmm_free 0x1f7a8500 (detail=0x1f7a85f0) > pmm_malloc zone=0x1f7afe7b handle=ffffffff size=48 align=10 > ret=0x000fdb30 (detail=0x1f7a85f0) > Searching bootorder for: /pci@i0cf8/usb@f,5/storage@2/*@0/*@0,0 > Searching bootorder for: /pci@i0cf8/usb@f,5/usb-*@2 > ehci_send_bulk qh=0x000ef680 dir=0 data=0x00006d55 size=31 > ehci_send_bulk qh=0x000ef700 dir=128 data=0x00006e3c size=36 > ehci_send_bulk qh=0x000ef700 dir=128 data=0x00006d8f size=13 > WARNING - Timeout at ehci_wait_td:542! > ehci pipe=0x000ef700 cur=00000000 tok=00000000 next=6b80 td=0x00006b80 > status=d0d80 > USB transmission failed > Unable to configure USB MSC drive. > pmm_free 0x000fdb30 (detail=0x1f7a85f0) > Unable to configure USB MSC device. > pmm_free 0x1f7a8700 (detail=0x1f7a8720) > pmm_free 0x1f7a8780 (detail=0x1f7a87a0) > pmm_malloc zone=0x1f7afe7f handle=ffffffff size=28 align=10 > ret=0x1f7a8780 (detail=0x1f7a87a0) > pmm_free 0x1f7a8780 (detail=0x1f7a87a0) > pmm_malloc zone=0x1f7afe7f handle=ffffffff size=28 align=10 > ret=0x1f7a8780 (detail=0x1f7a87a0) > pmm_free 0x1f7a8780 (detail=0x1f7a87a0) > ehci_free_pipes 0x1f7a8860 > pmm_free 0x1f7a8680 (detail=0x1f7a8750) > pmm_free 0x000ef680 (detail=0x1f7a8620) > pmm_free 0x000ef700 (detail=0x1f7a8650) > pmm_free 0x1f7bf000 (detail=0x1f7a8830) > pmm_free 0x1f7bef80 (detail=0x1f7a8800) > pmm_free 0x1f7bef00 (detail=0x1f7a87d0) > pmm_free 0x1f7a8860 (detail=0x1f7a88b0) > init serial > Found 2 serial ports > init hard drives > > Mabye somebody has some hints how to start debugging this and what I > should look for. > added some debug to seabios: http://dpaste.com/811158/ and tired my luck with FILO (using libpayload from coreboot): http://dpaste.com/811165/ --- Christian Gmeiner, MSc

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USB Problems geode lx800
by Christian Gmeiner 08 Oct '12

08 Oct '12

HI all I am running into some usb problems with coreboot & seabios: init usb pmm_malloc zone=0x1f7afe7f handle=ffffffff size=72 align=10 ret=0x1f7a8860 (detail=0x1f7a88b0) EHCI init on dev 00:0f.5 (regs=0xfe038010) pmm_malloc zone=0x1f7afe83 handle=ffffffff size=4096 align=1000 ret=0x1f7bf000 (detail=0x1f7a8830) pmm_malloc zone=0x1f7afe83 handle=ffffffff size=68 align=80 ret=0x1f7bef80 (detail=0x1f7a8800) pmm_malloc zone=0x1f7afe83 handle=ffffffff size=68 align=80 ret=0x1f7bef00 (detail=0x1f7a87d0) pmm_malloc zone=0x1f7afe7f handle=ffffffff size=28 align=10 ret=0x1f7a8780 (detail=0x1f7a87a0) pmm_free 0x1f7a8780 (detail=0x1f7a87a0) pmm_malloc zone=0x1f7afe7f handle=ffffffff size=28 align=10 ret=0x1f7a8780 (detail=0x1f7a87a0) set_address 0x1f7a8860 ehci_alloc_async_pipe 0x1f7a8860 0 pmm_malloc zone=0x1f7afe7f handle=ffffffff size=92 align=80 ret=0x1f7a8680 (detail=0x1f7a8750) ehci_control 0x1f7a86d0 (dir=0 cmd=8 data=0) pmm_malloc zone=0x1f7afe7f handle=ffffffff size=192 align=40 ret=0x1f7a85c0 (detail=0x1f7a8720) pmm_free 0x1f7a85c0 (detail=0x1f7a8720) ehci_alloc_async_pipe 0x1f7a8860 0 config_usb: 0x1f7a86d0 ehci_control 0x1f7a86d0 (dir=128 cmd=8 data=8) pmm_malloc zone=0x1f7afe7f handle=ffffffff size=192 align=40 ret=0x1f7a85c0 (detail=0x1f7a8720) pmm_free 0x1f7a85c0 (detail=0x1f7a8720) device rev=0200 cls=00 sub=00 proto=00 size=40 ehci_alloc_async_pipe 0x1f7a8860 0 ehci_control 0x1f7a86d0 (dir=128 cmd=8 data=9) pmm_malloc zone=0x1f7afe7f handle=ffffffff size=192 align=40 ret=0x1f7a85c0 (detail=0x1f7a8720) pmm_free 0x1f7a85c0 (detail=0x1f7a8720) pmm_malloc zone=0x1f7afe7f handle=ffffffff size=32 align=10 ret=0x1f7a8700 (detail=0x1f7a8720) ehci_control 0x1f7a86d0 (dir=128 cmd=8 data=32) pmm_malloc zone=0x1f7afe7f handle=ffffffff size=192 align=40 ret=0x1f7a8580 (detail=0x1f7a8650) pmm_free 0x1f7a8580 (detail=0x1f7a8650) ehci_control 0x1f7a86d0 (dir=0 cmd=8 data=0) pmm_malloc zone=0x1f7afe7f handle=ffffffff size=192 align=40 ret=0x1f7a8580 (detail=0x1f7a8650) pmm_free 0x1f7a8580 (detail=0x1f7a8650) ehci_alloc_async_pipe 0x1f7a8860 2 pmm_malloc zone=0x1f7afe77 handle=ffffffff size=92 align=80 ret=0x000ef700 (detail=0x1f7a8650) ehci_alloc_async_pipe 0x1f7a8860 2 pmm_malloc zone=0x1f7afe77 handle=ffffffff size=92 align=80 ret=0x000ef680 (detail=0x1f7a8620) ehci_control 0x1f7a86d0 (dir=128 cmd=8 data=1) pmm_malloc zone=0x1f7afe7f handle=ffffffff size=192 align=40 ret=0x1f7a8500 (detail=0x1f7a85f0) pmm_free 0x1f7a8500 (detail=0x1f7a85f0) pmm_malloc zone=0x1f7afe7b handle=ffffffff size=48 align=10 ret=0x000fdb30 (detail=0x1f7a85f0) Searching bootorder for: /pci@i0cf8/usb@f,5/storage@2/*@0/*@0,0 Searching bootorder for: /pci@i0cf8/usb@f,5/usb-*@2 ehci_send_bulk qh=0x000ef680 dir=0 data=0x00006d55 size=31 ehci_send_bulk qh=0x000ef700 dir=128 data=0x00006e3c size=36 ehci_send_bulk qh=0x000ef700 dir=128 data=0x00006d8f size=13 WARNING - Timeout at ehci_wait_td:542! ehci pipe=0x000ef700 cur=00000000 tok=00000000 next=6b80 td=0x00006b80 status=d0d80 USB transmission failed Unable to configure USB MSC drive. pmm_free 0x000fdb30 (detail=0x1f7a85f0) Unable to configure USB MSC device. pmm_free 0x1f7a8700 (detail=0x1f7a8720) pmm_free 0x1f7a8780 (detail=0x1f7a87a0) pmm_malloc zone=0x1f7afe7f handle=ffffffff size=28 align=10 ret=0x1f7a8780 (detail=0x1f7a87a0) pmm_free 0x1f7a8780 (detail=0x1f7a87a0) pmm_malloc zone=0x1f7afe7f handle=ffffffff size=28 align=10 ret=0x1f7a8780 (detail=0x1f7a87a0) pmm_free 0x1f7a8780 (detail=0x1f7a87a0) ehci_free_pipes 0x1f7a8860 pmm_free 0x1f7a8680 (detail=0x1f7a8750) pmm_free 0x000ef680 (detail=0x1f7a8620) pmm_free 0x000ef700 (detail=0x1f7a8650) pmm_free 0x1f7bf000 (detail=0x1f7a8830) pmm_free 0x1f7bef80 (detail=0x1f7a8800) pmm_free 0x1f7bef00 (detail=0x1f7a87d0) pmm_free 0x1f7a8860 (detail=0x1f7a88b0) init serial Found 2 serial ports init hard drives Mabye somebody has some hints how to start debugging this and what I should look for. --- Christian Gmeiner, MSc

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Patch merged into coreboot/master: fe4362c Increment revision of SeaBIOS to remove bashism
by gerrit＠coreboot.org 08 Oct '12

08 Oct '12

the following patch was just integrated into master: commit fe4362ced7a05f4984a81a6b2d0b8e362ba7377e Author: Stefan Tauner <stefan.tauner(a)gmx.at> Date: Mon Oct 8 03:00:08 2012 +0200 Increment revision of SeaBIOS to remove bashism This enables building with dash again(?) by using exactly one patch of SeaBIOS more/newer than previously, which has also the sole purpose of removing bashism and is a single line change. *sigh* Change-Id: Ib036894d8b9886f74d6eb0853f1fc0ce1aa39d54 Signed-off-by: Stefan Tauner <stefan.tauner(a)gmx.at> See http://review.coreboot.org/1568 for details. -gerrit

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Patch merged into coreboot/master: f68d1a4 Every chip must have chip_operations
by gerrit＠coreboot.org 08 Oct '12

08 Oct '12

the following patch was just integrated into master: commit f68d1a47411fe01213d7e1c14b77e4c8cfcb48a3 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Oct 7 15:08:32 2012 +0200 Every chip must have chip_operations Forcing this rule, chip_ops can be added in the static devicetree regardless of the existence of the chip.h files. Change-Id: Iec1c23484e85cab3f80a34f2b082088f38ac4de9 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Mon Oct 8 13:24:31 2012, giving +2 See http://review.coreboot.org/1472 for details. -gerrit

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New patch to review for coreboot: fe4362c Increment revision of SeaBIOS to remove bashism
by Stefan Tauner 08 Oct '12

08 Oct '12

Stefan Tauner (stefan.tauner(a)gmx.at) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1568 -gerrit commit fe4362ced7a05f4984a81a6b2d0b8e362ba7377e Author: Stefan Tauner <stefan.tauner(a)gmx.at> Date: Mon Oct 8 03:00:08 2012 +0200 Increment revision of SeaBIOS to remove bashism This enables building with dash again(?) by using exactly one patch of SeaBIOS more/newer than previously, which has also the sole purpose of removing bashism and is a single line change. *sigh* Change-Id: Ib036894d8b9886f74d6eb0853f1fc0ce1aa39d54 Signed-off-by: Stefan Tauner <stefan.tauner(a)gmx.at> --- payloads/external/SeaBIOS/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index e0f03b1..d856f37 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -1,7 +1,7 @@ TAG-$(CONFIG_SEABIOS_MASTER)=origin/master -TAG-$(CONFIG_SEABIOS_STABLE)=a0263083cb4cda172832fbc916dc1417ee930574 +TAG-$(CONFIG_SEABIOS_STABLE)=385a7d0dec28841a05531cba96c62138c3959fef unexport KCONFIG_AUTOCONFIG

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New patch to review for coreboot: 02d3cf7 Provide weak empty declarations of all chip_ops used on a board
by Patrick Georgi 07 Oct '12

07 Oct '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1567 -gerrit commit 02d3cf7d5c47827d80b08f06b3d35b259d66c664 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sun Oct 7 22:04:52 2012 +0200 Provide weak empty declarations of all chip_ops used on a board sconfig creates empty defaults for all chip_ops, which can be overridden by drivers simply by providing a concrete implementation. Change-Id: Ib37515f0b0747bdbf4da780d28690a1e719944b2 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/devices/Makefile.inc | 3 --- src/devices/dummy_chip_ops.c | 30 ------------------------------ util/sconfig/main.c | 2 +- 3 files changed, 1 insertion(+), 34 deletions(-) diff --git a/src/devices/Makefile.inc b/src/devices/Makefile.inc index 185ccc1..9d4b391 100644 --- a/src/devices/Makefile.inc +++ b/src/devices/Makefile.inc @@ -12,9 +12,6 @@ ramstage-y += pnp_device.c ramstage-y += pci_ops.c ramstage-y += smbus_ops.c -# Work-around for chip.h removal -ramstage-y += dummy_chip_ops.c - romstage-y+= device_romstage.c subdirs-y += oprom diff --git a/src/devices/dummy_chip_ops.c b/src/devices/dummy_chip_ops.c deleted file mode 100644 index a2fc999..0000000 --- a/src/devices/dummy_chip_ops.c +++ /dev/null @@ -1,30 +0,0 @@ -#include <device/device.h> - -/* Dummy chip_operations, so every chip has one for sure. - * Temporary work-around before total chip.h removal. - */ - -struct chip_operations cpu_via_c3_ops = {}; -struct chip_operations cpu_via_c7_ops = {}; -struct chip_operations cpu_amd_geode_lx_ops = {}; -struct chip_operations cpu_amd_geode_gx1_ops = {}; -struct chip_operations cpu_amd_geode_gx2_ops = {}; -struct chip_operations drivers_ati_ragexl_ops = {}; -struct chip_operations drivers_dec_21143_ops = {}; -struct chip_operations drivers_generic_generic_ops = {}; -struct chip_operations drivers_oxford_oxpcie_ops = {}; -struct chip_operations drivers_realtek_ops = {}; -struct chip_operations drivers_sil_3114_ops = {}; -struct chip_operations drivers_trident_blade3d_ops = {}; -struct chip_operations southbridge_amd_amd8131_ops = {}; -struct chip_operations southbridge_amd_amd8132_ops = {}; -struct chip_operations southbridge_amd_amd8151_ops = {}; -struct chip_operations southbridge_broadcom_bcm21000_ops = {}; -struct chip_operations southbridge_broadcom_bcm5780_ops = {}; -struct chip_operations southbridge_intel_i82870_ops = {}; -struct chip_operations southbridge_rdc_r8610_ops = {}; -struct chip_operations southbridge_via_k8t890_ops = {}; -struct chip_operations superio_serverengines_pilot_ops = {}; -struct chip_operations superio_smsc_lpc47n207_ops = {}; -struct chip_operations superio_smsc_sio1007_ops = {}; - diff --git a/util/sconfig/main.c b/util/sconfig/main.c index f066d7b..1b0968f 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -625,7 +625,7 @@ int main(int argc, char** argv) { h = h->next; char *name_underscore = strdup(h->name); translate_name(name_underscore, 0); - fprintf(autogen, "extern struct chip_operations %s_ops;\n", name_underscore); + fprintf(autogen, "__attribute__((weak)) struct chip_operations %s_ops = {};\n", name_underscore); free(name_underscore); } fprintf(autogen, "#endif\n");

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New patch to review for coreboot: 8193b99 Drop ramstage.a
by Patrick Georgi 07 Oct '12

07 Oct '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1566 -gerrit commit 8193b997acf2c7ddb04ef0d4095fc950afcd754d Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sun Oct 7 22:11:07 2012 +0200 Drop ramstage.a ramstage.a has two issues: 1. duplicate source filenames don't survive the ar(1) treatment properly (so files aren't considered) 2. ld doesn't resolve symbols if it isn't forced to, in particular no overrides of weak symbols Downside: The resulting binaries get slightly larger. Link time optimizations should fix that, as would tighter rules in the build system (to not compile unused code in the first place). Change-Id: Iaae771ec8f92b42069237acd3b79c14e5bf9c03d Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/arch/x86/Makefile.inc | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index c58f3be..ab823f1 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -159,19 +159,14 @@ else $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/x86/coreboot_ram.ld $< endif -$(objgenerated)/coreboot_ram.o: $(obj)/arch/x86/lib/c_start.ramstage.o $$(driver-objs) $(objgenerated)/ramstage.a $(LIBGCC_FILE_NAME) +$(objgenerated)/coreboot_ram.o: $(obj)/arch/x86/lib/c_start.ramstage.o $$(driver-objs) $$(ramstage-objs) $(LIBGCC_FILE_NAME) @printf " CC $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD) -m elf_i386 -r -o $@ $(obj)/arch/x86/lib/c_start.ramstage.o $(driver-objs) --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --start-group $(objgenerated)/ramstage.a $(LIBGCC_FILE_NAME) --end-group + $(LD) -m elf_i386 -r -o $@ $(obj)/arch/x86/lib/c_start.ramstage.o $(driver-objs) --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --start-group $(filter-out $(obj)/arch/x86/lib/c_start.ramstage.o,$(ramstage-objs)) $(LIBGCC_FILE_NAME) --end-group else - $(CC) -nostdlib -r -o $@ $(obj)/arch/x86/lib/c_start.ramstage.o $(driver-objs) -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(objgenerated)/ramstage.a $(LIBGCC_FILE_NAME) -Wl,--end-group + $(CC) -nostdlib -r -o $@ $(obj)/arch/x86/lib/c_start.ramstage.o $(driver-objs) -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(filter-out $(obj)/arch/x86/lib/c_start.ramstage.o,$(ramstage-objs)) $(LIBGCC_FILE_NAME) -Wl,--end-group endif -$(objgenerated)/ramstage.a: $$(ramstage-objs) - @printf " AR $(subst $(obj)/,,$(@))\n" - rm -f $@ - $(AR) cr $@ $^ - ################################################################################ # Ramstage for AP CPU (AMD K8, obsolete?)

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Patch merged into coreboot/master: f66a086 Take care of NULL chip_ops->name
by gerrit＠coreboot.org 07 Oct '12

07 Oct '12

the following patch was just integrated into master: commit f66a0861572e198bffa8a31af56871044ea81781 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Oct 7 14:57:15 2012 +0200 Take care of NULL chip_ops->name Change-Id: I62b1c497d23ec2241efb963e7834728085824016 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Sun Oct 7 21:48:47 2012, giving +2 See http://review.coreboot.org/1565 for details. -gerrit

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coreboot October 2012