coreboot October 2012

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Patch merged into coreboot/master: 77f6b55 bachmann/ot200: Fix wrong IRQ number for PIRQD
by gerrit＠coreboot.org 10 Oct '12

10 Oct '12

the following patch was just integrated into master: commit 77f6b55c71770a2565dbe5c7240eb8820ebc2c99 Author: Christian Gmeiner <christian.gmeiner(a)gmail.com> Date: Wed Oct 10 09:07:28 2012 +0200 bachmann/ot200: Fix wrong IRQ number for PIRQD The used FPGA on the device triggers PIRQD for the membrane keyboard. The used linux driver for the keyboard uses the fixed IRQ number of 7. In order not to touch the linux driver and be compatible with proprietary BIOS change the irq_table in coreboot. Change-Id: If5bc929eb48bb1eafd401941ebb7d34cf5862c35 Signed-off-by: Christian Gmeiner <christian.gmeiner(a)gmail.com> Build-Tested: build bot (Jenkins) at Wed Oct 10 09:26:49 2012, giving +1 Reviewed-By: Peter Stuge <peter(a)stuge.se> at Wed Oct 10 15:36:11 2012, giving +2 See http://review.coreboot.org/1571 for details. -gerrit

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Re: [coreboot] how to assign irq to a device
by WANG Siyuan 10 Oct '12

10 Oct '12

hi, ali thank you. this is an Ethernet controller plugged in PCI slot. maybe it is also called LAN card. this card is not plugged in USB slot, it is plugged in PCI slot. so I think the irq is not right. On Wed, Oct 10, 2012 at 7:34 PM, ali hagigat <hagigatali(a)gmail.com> wrote: > External PCI network adaptor? > If it is plugged in PCI slot so it is internal. Is it a LAN card > plugged into USB slot? > > On Wed, Oct 10, 2012 at 2:41 PM, WANG Siyuan <wangsiyuanbuaa(a)gmail.com> > wrote: > > hi, > > i am debugging a mainboard with an external pci network adapter. > > the adapter share irq with usb. it seems not correct, so i want to assign > > an irq for this adapter. > > how to do that? > > thank you. > > > > /proc/interrupt > > eth1 is an external pci network adapter. i want to assign irq 21 for it. > > > > CPU0 CPU1 CPU2 CPU3 CPU4 CPU5 > > CPU6 CPU7 > > 0: 59 0 0 0 0 0 > > 0 0 IO-APIC-edge timer > > 1: 0 0 1 0 1 1 > > 0 0 IO-APIC-edge i8042 > > 7: 1 0 0 0 0 0 > > 0 0 IO-APIC-edge > > 8: 0 0 0 0 0 0 > > 0 0 IO-APIC-edge rtc0 > > 9: 0 0 0 0 0 0 > > 0 0 IO-APIC-fasteoi acpi > > 12: 0 0 0 1 1 0 > > 1 1 IO-APIC-edge i8042 > > 14: 0 0 0 0 0 0 > > 0 0 IO-APIC-edge pata_atiixp > > 15: 0 0 0 0 0 0 > > 0 0 IO-APIC-edge pata_atiixp > > 16: 93 95 80 91 96 94 > > 98 97 IO-APIC-fasteoi ohci_hcd:usb3, ohci_hcd:usb4 > > 17: 1 0 1 0 0 0 > > 0 0 IO-APIC-fasteoi ehci_hcd:usb1 > > 18: 4 4 4 4 4 4 > > 2 4 IO-APIC-fasteoi ohci_hcd:usb5, ohci_hcd:usb6, > > ohci_hcd:usb7 > > 19: 1 1 0 0 0 0 > > 0 0 IO-APIC-fasteoi ehci_hcd:usb2, eth1 > > 22: 672 685 691 692 693 683 > > 687 681 IO-APIC-fasteoi ahci > > 296: 119 99 127 87 125 96 > > 121 105 PCI-MSI-edge eth0-rx-0 > > 297: 0 0 0 0 0 0 > > 0 0 PCI-MSI-edge eth0-tx-0 > > 298: 1 0 0 0 0 0 > > 0 0 PCI-MSI-edge eth0 > > 299: 123 125 105 138 93 135 > > 106 132 PCI-MSI-edge eth2-rx-0 > > 300: 2 4 4 0 1 2 > > 1 3 PCI-MSI-edge eth2-tx-0 > > 301: 0 0 1 0 0 0 > > 0 2 PCI-MSI-edge eth2 > > NMI: 0 0 0 0 0 0 > > 0 0 Non-maskable interrupts > > LOC: 4050 1673 3943 2348 2519 2963 > > 3093 1644 Local timer interrupts > > SPU: 0 0 0 0 0 0 > > 0 0 Spurious interrupts > > PMI: 0 0 0 0 0 0 > > 0 0 Performance monitoring interrupts > > IWI: 0 0 0 0 0 0 > > 0 0 IRQ work interrupts > > RTR: 0 0 0 0 0 0 > > 0 0 APIC ICR read retries > > RES: 5454 4177 5477 3690 5121 3822 > > 5342 3630 Rescheduling interrupts > > CAL: 44 58 52 57 46 56 > > 50 59 Function call interrupts > > TLB: 291 391 291 336 274 344 > > 237 395 TLB shootdowns > > TRM: 0 0 0 0 0 0 > > 0 0 Thermal event interrupts > > THR: 0 0 0 0 0 0 > > 0 0 Threshold APIC interrupts > > MCE: 0 0 0 0 0 0 > > 0 0 Machine check exceptions > > MCP: 6 6 6 6 6 6 > > 6 6 Machine check polls > > ERR: 1 > > MIS: 0 > > > > > > -- > > WANG Siyuan > > -- > > coreboot mailing list: coreboot(a)coreboot.org > > http://www.coreboot.org/mailman/listinfo/coreboot > -- WANG Siyuan

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Re: [coreboot] how to assign irq to a device
by ali hagigat 10 Oct '12

10 Oct '12

External PCI network adaptor? If it is plugged in PCI slot so it is internal. Is it a LAN card plugged into USB slot? On Wed, Oct 10, 2012 at 2:41 PM, WANG Siyuan <wangsiyuanbuaa(a)gmail.com> wrote: > hi, > i am debugging a mainboard with an external pci network adapter. > the adapter share irq with usb. it seems not correct, so i want to assign > an irq for this adapter. > how to do that? > thank you. > > /proc/interrupt > eth1 is an external pci network adapter. i want to assign irq 21 for it. > > CPU0 CPU1 CPU2 CPU3 CPU4 CPU5 > CPU6 CPU7 > 0: 59 0 0 0 0 0 > 0 0 IO-APIC-edge timer > 1: 0 0 1 0 1 1 > 0 0 IO-APIC-edge i8042 > 7: 1 0 0 0 0 0 > 0 0 IO-APIC-edge > 8: 0 0 0 0 0 0 > 0 0 IO-APIC-edge rtc0 > 9: 0 0 0 0 0 0 > 0 0 IO-APIC-fasteoi acpi > 12: 0 0 0 1 1 0 > 1 1 IO-APIC-edge i8042 > 14: 0 0 0 0 0 0 > 0 0 IO-APIC-edge pata_atiixp > 15: 0 0 0 0 0 0 > 0 0 IO-APIC-edge pata_atiixp > 16: 93 95 80 91 96 94 > 98 97 IO-APIC-fasteoi ohci_hcd:usb3, ohci_hcd:usb4 > 17: 1 0 1 0 0 0 > 0 0 IO-APIC-fasteoi ehci_hcd:usb1 > 18: 4 4 4 4 4 4 > 2 4 IO-APIC-fasteoi ohci_hcd:usb5, ohci_hcd:usb6, > ohci_hcd:usb7 > 19: 1 1 0 0 0 0 > 0 0 IO-APIC-fasteoi ehci_hcd:usb2, eth1 > 22: 672 685 691 692 693 683 > 687 681 IO-APIC-fasteoi ahci > 296: 119 99 127 87 125 96 > 121 105 PCI-MSI-edge eth0-rx-0 > 297: 0 0 0 0 0 0 > 0 0 PCI-MSI-edge eth0-tx-0 > 298: 1 0 0 0 0 0 > 0 0 PCI-MSI-edge eth0 > 299: 123 125 105 138 93 135 > 106 132 PCI-MSI-edge eth2-rx-0 > 300: 2 4 4 0 1 2 > 1 3 PCI-MSI-edge eth2-tx-0 > 301: 0 0 1 0 0 0 > 0 2 PCI-MSI-edge eth2 > NMI: 0 0 0 0 0 0 > 0 0 Non-maskable interrupts > LOC: 4050 1673 3943 2348 2519 2963 > 3093 1644 Local timer interrupts > SPU: 0 0 0 0 0 0 > 0 0 Spurious interrupts > PMI: 0 0 0 0 0 0 > 0 0 Performance monitoring interrupts > IWI: 0 0 0 0 0 0 > 0 0 IRQ work interrupts > RTR: 0 0 0 0 0 0 > 0 0 APIC ICR read retries > RES: 5454 4177 5477 3690 5121 3822 > 5342 3630 Rescheduling interrupts > CAL: 44 58 52 57 46 56 > 50 59 Function call interrupts > TLB: 291 391 291 336 274 344 > 237 395 TLB shootdowns > TRM: 0 0 0 0 0 0 > 0 0 Thermal event interrupts > THR: 0 0 0 0 0 0 > 0 0 Threshold APIC interrupts > MCE: 0 0 0 0 0 0 > 0 0 Machine check exceptions > MCP: 6 6 6 6 6 6 > 6 6 Machine check polls > ERR: 1 > MIS: 0 > > > -- > WANG Siyuan > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot

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how to assign irq to a device
by WANG Siyuan 10 Oct '12

10 Oct '12

hi, i am debugging a mainboard with an external pci network adapter. the adapter share irq with usb. it seems not correct, so i want to assign an irq for this adapter. how to do that? thank you. /proc/interrupt eth1 is an external pci network adapter. i want to assign irq 21 for it. CPU0 CPU1 CPU2 CPU3 CPU4 CPU5 CPU6 CPU7 0: 59 0 0 0 0 0 0 0 IO-APIC-edge timer 1: 0 0 1 0 1 1 0 0 IO-APIC-edge i8042 7: 1 0 0 0 0 0 0 0 IO-APIC-edge 8: 0 0 0 0 0 0 0 0 IO-APIC-edge rtc0 9: 0 0 0 0 0 0 0 0 IO-APIC-fasteoi acpi 12: 0 0 0 1 1 0 1 1 IO-APIC-edge i8042 14: 0 0 0 0 0 0 0 0 IO-APIC-edge pata_atiixp 15: 0 0 0 0 0 0 0 0 IO-APIC-edge pata_atiixp 16: 93 95 80 91 96 94 98 97 IO-APIC-fasteoi ohci_hcd:usb3, ohci_hcd:usb4 17: 1 0 1 0 0 0 0 0 IO-APIC-fasteoi ehci_hcd:usb1 18: 4 4 4 4 4 4 2 4 IO-APIC-fasteoi ohci_hcd:usb5, ohci_hcd:usb6, ohci_hcd:usb7 19: 1 1 0 0 0 0 0 0 IO-APIC-fasteoi ehci_hcd:usb2, eth1 22: 672 685 691 692 693 683 687 681 IO-APIC-fasteoi ahci 296: 119 99 127 87 125 96 121 105 PCI-MSI-edge eth0-rx-0 297: 0 0 0 0 0 0 0 0 PCI-MSI-edge eth0-tx-0 298: 1 0 0 0 0 0 0 0 PCI-MSI-edge eth0 299: 123 125 105 138 93 135 106 132 PCI-MSI-edge eth2-rx-0 300: 2 4 4 0 1 2 1 3 PCI-MSI-edge eth2-tx-0 301: 0 0 1 0 0 0 0 2 PCI-MSI-edge eth2 NMI: 0 0 0 0 0 0 0 0 Non-maskable interrupts LOC: 4050 1673 3943 2348 2519 2963 3093 1644 Local timer interrupts SPU: 0 0 0 0 0 0 0 0 Spurious interrupts PMI: 0 0 0 0 0 0 0 0 Performance monitoring interrupts IWI: 0 0 0 0 0 0 0 0 IRQ work interrupts RTR: 0 0 0 0 0 0 0 0 APIC ICR read retries RES: 5454 4177 5477 3690 5121 3822 5342 3630 Rescheduling interrupts CAL: 44 58 52 57 46 56 50 59 Function call interrupts TLB: 291 391 291 336 274 344 237 395 TLB shootdowns TRM: 0 0 0 0 0 0 0 0 Thermal event interrupts THR: 0 0 0 0 0 0 0 0 Threshold APIC interrupts MCE: 0 0 0 0 0 0 0 0 Machine check exceptions MCP: 6 6 6 6 6 6 6 6 Machine check polls ERR: 1 MIS: 0 -- WANG Siyuan

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New patch to review for coreboot: 77f6b55 bachmann/ot200: Fix wrong IRQ number for PIRQD
by Christian Gmeiner 10 Oct '12

10 Oct '12

Christian Gmeiner (christian.gmeiner(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1571 -gerrit commit 77f6b55c71770a2565dbe5c7240eb8820ebc2c99 Author: Christian Gmeiner <christian.gmeiner(a)gmail.com> Date: Wed Oct 10 09:07:28 2012 +0200 bachmann/ot200: Fix wrong IRQ number for PIRQD The used FPGA on the device triggers PIRQD for the membrane keyboard. The used linux driver for the keyboard uses the fixed IRQ number of 7. In order not to touch the linux driver and be compatible with proprietary BIOS change the irq_table in coreboot. Change-Id: If5bc929eb48bb1eafd401941ebb7d34cf5862c35 Signed-off-by: Christian Gmeiner <christian.gmeiner(a)gmail.com> --- src/mainboard/bachmann/ot200/irq_tables.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/bachmann/ot200/irq_tables.c b/src/mainboard/bachmann/ot200/irq_tables.c index 7c3e08f..5a5372a 100644 --- a/src/mainboard/bachmann/ot200/irq_tables.c +++ b/src/mainboard/bachmann/ot200/irq_tables.c @@ -23,8 +23,8 @@ /* Platform IRQs */ #define PIRQA 5 #define PIRQB 9 -#define PIRQC 7 -#define PIRQD 10 +#define PIRQC 10 +#define PIRQD 7 /* Map */ #define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */

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Patch merged into coreboot/master: 02d7292 iei/kino-780am2: Turn on PCIe bridge to 2nd ethernet controller.
by gerrit＠coreboot.org 10 Oct '12

10 Oct '12

the following patch was just integrated into master: commit 02d729275a0187cf44eb4ad927e00f52433bb82f Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Tue Oct 9 15:13:25 2012 -0600 iei/kino-780am2: Turn on PCIe bridge to 2nd ethernet controller. Change-Id: I35fa94bafcf7c835081b57acf031a2fb334d353d Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> Build-Tested: build bot (Jenkins) at Wed Oct 10 00:43:53 2012, giving +1 Reviewed-By: Peter Stuge <peter(a)stuge.se> at Wed Oct 10 01:59:06 2012, giving +2 See http://review.coreboot.org/1570 for details. -gerrit

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New patch to review for coreboot: 02d7292 iei/kino-780am2: Turn on PCIe bridge to 2nd ethernet controller.
by Dave Frodin 10 Oct '12

10 Oct '12

Dave Frodin (dave.frodin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1570 -gerrit commit 02d729275a0187cf44eb4ad927e00f52433bb82f Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Tue Oct 9 15:13:25 2012 -0600 iei/kino-780am2: Turn on PCIe bridge to 2nd ethernet controller. Change-Id: I35fa94bafcf7c835081b57acf031a2fb334d353d Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> --- src/mainboard/iei/kino-780am2-fam10/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/iei/kino-780am2-fam10/devicetree.cb b/src/mainboard/iei/kino-780am2-fam10/devicetree.cb index 3f0b361..06d2d32 100644 --- a/src/mainboard/iei/kino-780am2-fam10/devicetree.cb +++ b/src/mainboard/iei/kino-780am2-fam10/devicetree.cb @@ -14,7 +14,7 @@ chip northbridge/amd/amdfam10/root_complex device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 device pci 3.0 on end # PCIE P2P bridge 0x960b device pci 4.0 on end # PCIE P2P bridge 0x9604 - device pci 5.0 off end # PCIE P2P bridge 0x9605 + device pci 5.0 on end # PCIE P2P bridge 0x9605 device pci 6.0 off end # PCIE P2P bridge 0x9606 device pci 7.0 off end # PCIE P2P bridge 0x9607 device pci 8.0 off end # NB/SB Link P2P bridge

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Re: [coreboot] [SeaBIOS] USB Problems geode lx800
by Kevin O'Connor 09 Oct '12

09 Oct '12

On Mon, Oct 08, 2012 at 02:14:03PM +0200, Christian Gmeiner wrote: > HI all > > I am running into some usb problems with coreboot & seabios: > > > init usb > pmm_malloc zone=0x1f7afe7f handle=ffffffff size=72 align=10 > ret=0x1f7a8860 (detail=0x1f7a88b0) [...] > > Mabye somebody has some hints how to start debugging this and what I > should look for. Hi Christian, Can you set the debug level to 8 and post the whole log? Also, for timeout issues, having timestamps (via tools/readserial.py tool) sometimes helps. Did this regress, or has it never worked? What type of USB drive are you attempting to use? -Kevin

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Patch merged into coreboot/master: a65378e hpet: common ACPI generation
by gerrit＠coreboot.org 08 Oct '12

08 Oct '12

the following patch was just integrated into master: commit a65378e809b60e18eb8b1c2f54c30eff84b3f7f3 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Fri Oct 5 21:54:38 2012 +0200 hpet: common ACPI generation HPET's min ticks (minimum time between events to avoid losing interrupts) is chipset specific, so move it to Kconfig. Via also has a special base address, so move it as well. Apart from these (and the base address was already #defined), the table is very uniform. Change-Id: I848a2e2b0b16021c7ee5ba99097fa6a5886c3286 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/1562 for details. -gerrit

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Patch set updated for coreboot: 1485980 Fix ExecuteFinalHltInstruction function in f15h family code
by Aladyshev Konstantin 08 Oct '12

08 Oct '12

Aladyshev Konstantin (kostr(a)list.ru) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1569 -gerrit commit 148598054c34c601273b69a67d7db2d2b88da48c Author: Kostr <aladyshev(a)nicevt.ru> Date: Mon Oct 8 22:04:53 2012 +0400 Fix ExecuteFinalHltInstruction function in f15h family code Current ExecuteFinalHltInstruction function doesn't work well. (at least in configuration Supermicro board with Orochi AMD Opteron processors (model OS6234WKTCGGU)) System reboots when trying to halt core 2,4,6,8 or 10 (OS6234WKTCGGU is 12 core processor) Based on this information, i think that code doesn't really work with f15 compute unit (CU) system. Replacing ExecuteFinalHltInstruction function with analogous function from f15tn family code fix this problem. Both functions written from the same cahalt.asm file, but f15tn version seems more completed Change-Id: I3942abcdf21f1b86a44c01cc477714e44a40b9cf Signed-off-by: Kostr <aladyshev(a)nicevt.ru> --- src/vendorcode/amd/agesa/f15/Makefile.inc | 1 + src/vendorcode/amd/agesa/f15/Proc/CPU/cahalt.c | 146 --------------- src/vendorcode/amd/agesa/f15/Proc/CPU/cahaltasm.S | 209 ++++++++++++++++++++++ src/vendorcode/amd/agesa/f15/gcccar.inc | 15 ++ 4 files changed, 225 insertions(+), 146 deletions(-) diff --git a/src/vendorcode/amd/agesa/f15/Makefile.inc b/src/vendorcode/amd/agesa/f15/Makefile.inc index 1f3ba51..0762b08 100644 --- a/src/vendorcode/amd/agesa/f15/Makefile.inc +++ b/src/vendorcode/amd/agesa/f15/Makefile.inc @@ -88,6 +88,7 @@ agesa_lib_src += ./Proc/Common/CommonReturns.c agesa_lib_src += ./Proc/Common/CreateStruct.c agesa_lib_src += ./Proc/Common/S3RestoreState.c agesa_lib_src += ./Proc/Common/S3SaveState.c +agesa_lib_src += ./Proc/CPU/cahaltasm.S agesa_lib_src += ./Proc/CPU/cahalt.c agesa_lib_src += ./Proc/CPU/cpuApicUtilities.c agesa_lib_src += ./Proc/CPU/cpuBist.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cahalt.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/cahalt.c index e204a49..68ca272 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cahalt.c +++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/cahalt.c @@ -102,152 +102,6 @@ ExecuteWbinvdInstruction ( */ -//---------------------------------------------------------------------------- - -STATIC -VOID -PrimaryCoreFunctions (AP_MTRR_SETTINGS *ApMtrrSettingsList) - { - UINT64 data; - UINT32 msrno; - // Configure the MTRRs on the AP so - // when it runs remote code it will execute - // out of RAM instead of ROM. - // Disable MTRRs and turn on modification enable bit - - data = __readmsr (0xC0010010); // MTRR_SYS_CFG - data &= ~(1 << 18); // MtrrFixDramEn - data &= ~(1 << 20); // MtrrVarDramEn - data |= (1 << 19); // MtrrFixDramModEn - data |= (1 << 17); // SysUcLockEn - - - __writemsr (0xC0010010, data); - - // Set 7FFFh-00000h and 9FFFFh-80000h as WB DRAM - __writemsr (0x250, 0x1E1E1E1E1E1E1E1E); // AMD_MTRR_FIX64k_00000 - __writemsr (0x258, 0x1E1E1E1E1E1E1E1E); // AMD_MTRR_FIX16k_80000 - - // Set BFFFFh-A0000h, DFFFFh-C0000h as Uncacheable Memory-mapped IO - __writemsr (0x259, 0); // AMD_AP_MTRR_FIX16k_A0000 - __writemsr (0x268, 0); // AMD_MTRR_FIX4k_C0000 - __writemsr (0x269, 0); // AMD_MTRR_FIX4k_C8000 - __writemsr (0x26A, 0); // AMD_MTRR_FIX4k_D0000 - __writemsr (0x26B, 0); // AMD_MTRR_FIX4k_D8000 - - // Set FFFFFh-E0000h as Uncacheable Memory - for (msrno = 0x26C; msrno <= 0x26F; msrno++) - __writemsr (msrno, 0x1818181818181818); - - // If IBV provided settings for Fixed-Sized MTRRs, - // overwrite the default settings. - if ((uintptr_t) ApMtrrSettingsList != 0 && (uintptr_t) ApMtrrSettingsList != 0xFFFFFFFF) - { - int index; - for (index = 0; ApMtrrSettingsList [index].MsrAddr != CPU_LIST_TERMINAL; index++) - __writemsr (ApMtrrSettingsList [index].MsrAddr, ApMtrrSettingsList [index].MsrData); - } - - // restore variable MTTR6 and MTTR7 to default states - for (msrno = 0x20F; msrno <= 0x20C; msrno--) // decrement so that the pair is disable before the base is cleared - __writemsr (msrno, 0); - - // Enable fixed-range and variable-range MTRRs - // Set Fixed-Range Enable (FE) and MTRR Enable (E) bits - __writemsr (0x2FF, __readmsr (0x2FF) | 0xC00); - - // Enable Top-of-Memory setting - // Enable use of RdMem/WrMem bits attributes - data = __readmsr (0xC0010010); // MTRR_SYS_CFG - data |= (1 << 18); // MtrrFixDramEn - data |= (1 << 20); // MtrrVarDramEn - data &= ~(1 << 19); // MtrrFixDramModEn - __writemsr (0xC0010010, data); - } - -//---------------------------------------------------------------------------- - -VOID -ExecuteFinalHltInstruction ( - IN UINT32 SharedCore, - IN AP_MTRR_SETTINGS *ApMtrrSettingsList, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - int abcdRegs [4]; - UINT32 cr0val; - UINT64 data; - - cr0val = __readcr0 (); - if (SharedCore & 2) - { - // set CombineCr0Cd and enable cache in CR0 - __writemsr (MSR_CU_CFG3, __readmsr (MSR_CU_CFG3) | 1ULL << 49); - __writecr0 (cr0val & ~0x60000000); - } - else - __writecr0 (cr0val | 0x60000000); - - if (SharedCore & 1) PrimaryCoreFunctions (ApMtrrSettingsList); - - // Make sure not to touch any Shared MSR from this point on - - // Restore settings that were temporarily overridden for the cache as ram phase - data = __readmsr (0xC0011022); // MSR_DC_CFG - data &= ~(1 << 4); // DC_DIS_SPEC_TLB_RLD - data &= ~(1 << 8); // DIS_CLR_WBTOL2_SMC_HIT - data &= ~(1 << 13); // DIS_HW_PF - __writemsr (0xC0011022, data); - - data = __readmsr (0xC0011021); // MSR_IC_CFG - C001_1021 - data &= ~(1 << 9); // IC_DIS_SPEC_TLB_RLD - __writemsr (0xC0011021, data); - - // AMD_DISABLE_STACK_FAMILY_HOOK - __cpuid (abcdRegs, 1); - if ((abcdRegs [0] >> 20) == 1) //-----family 10h (Hydra) only----- - { - data = __readmsr (0xC0011022); - data &= ~(1 << 4); - data &= ~(1 << 8); - data &= ~(1 << 13); - __writemsr (0xC0011022, data); - - data = __readmsr (0xC0011021); - data &= ~(1 << 14); - data &= ~(1 << 9); - __writemsr (0xC0011021, data); - - data = __readmsr (0xC001102A); - data &= ~(1 << 15); - data &= ~(1ull << 35); - __writemsr (0xC001102A, data); - } - else if ((abcdRegs [0] >> 20) == 6) //-----family 15h (Orochi) only----- - { - data = __readmsr (0xC0011020); - data &= ~(1 << 28); - __writemsr (0xC0011020, data); - - data = __readmsr (0xC0011021); - data &= ~(1 << 9); - __writemsr (0xC0011021, data); - - data = __readmsr (0xC0011022); - data &= ~(1 << 4); - data &= ~(1l << 13); - __writemsr (0xC0011022, data); - } - - for (;;) - { - _disable (); - __halt (); - } - } - -//---------------------------------------------------------------------------- - /// Structure needed to load the IDTR using the lidt instruction VOID diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cahaltasm.S b/src/vendorcode/amd/agesa/f15/Proc/CPU/cahaltasm.S new file mode 100644 index 0000000..221805a --- /dev/null +++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/cahaltasm.S @@ -0,0 +1,209 @@ +/* + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +.include "src/vendorcode/amd/agesa/f15/gcccar.inc" + +.code32 +.align 4 +.globl ExecuteFinalHltInstruction + .type ExecuteFinalHltInstruction, @function +/* ExecuteFinalHltInstruction ( + IN UINT32 HaltFlags, + IN AP_MTRR_SETTINGS *ApMtrrSettingsList, + IN AMD_CONFIG_PARAMS *StdHeader + ) +*/ + +/* This function disables CAR. We don't care about the stack on this CPU */ +ExecuteFinalHltInstruction: + movl 4(%esp), %esi /* HaltFlags*/ + movl 8(%esp), %edi /* ApMtrrSettingList */ +//1: jmp 1b //good +/* Do these special steps in case if the core is part of a compute unit + * Note: The following bits are family specific flags, that gets set during build time, + * and indicates things like "family cache control methodology", etc. + * esi bit0 = 0 -> not a Primary core + * esi bit0 = 1 -> Primary core + * esi bit1 = 0 -> Cache disable + * esi bit1 = 1 -> Cache enable + */ + + bt $1, %esi /* .if (esi & 2h) */ + jz 0f + /* Set CombineCr0Cd bit */ + movl $CU_CFG3, %ecx + rdmsr + bts $(COMBINE_CR0_CD - 32), %edx + wrmsr + /* Clear the CR0.CD bit */ + movl %cr0, %eax /* Make sure cache is enabled for all APs */ + btr $CR0_CD, %eax + btr $CR0_NW, %eax + mov %eax, %cr0 /* Write back to CR0 */ + jmp 1f /* .else */ +0: + movl %cr0, %eax /* Make sure cache is disabled for all APs */ + bts $CR0_CD, %eax /* Disable cache */ + bts $CR0_NW, %eax + movl %eax, %cr0 /* Write back to CR0 */ +1: /* .endif */ + +// jmp 1b + bt $0, %esi /* .if (esi & 1h) */ + jz 2f + /* This core is a primary core and needs to do all the MTRRs, including shared MTRRs. */ + movl %edi, %esi /* Get ApMtrrSettingList */ + + /* Configure the MTRRs on the AP so + * when it runs remote code it will execute + * out of RAM instead of ROM. + */ + + /* Disable MTRRs and turn on modification enable bit */ + movl $MTRR_SYS_CFG, %ecx + rdmsr + /* TODO: why comment this? */ + //btr $MTRR_VAR_DRAM_EN, %eax /* Disable */ + bts $MTRR_FIX_DRAM_MOD_EN, %eax /* Enable */ + btr $MTRR_FIX_DRAM_EN, %eax /* Disable */ + //bts $SYS_UC_LOCK_EN, %eax + wrmsr + + /* Setup default values for Fixed-Sized MTRRs */ + /* Set 7FFFh-00000h as WB */ + movl $AMD_AP_MTRR_FIX64k_00000, %ecx + movl $0x1E1E1E1E, %eax + movl %eax, %edx + wrmsr + + /* Set 9FFFFh-80000h also as WB */ + movl $AMD_AP_MTRR_FIX16k_80000, %ecx + wrmsr + + /* Set BFFFFh-A0000h as Uncacheable Memory-mapped IO */ + movl $AMD_AP_MTRR_FIX16k_A0000, %ecx + xorl %eax, %eax + xorl %edx, %edx + wrmsr + + /* Set DFFFFh-C0000h as Uncacheable Memory-mapped IO */ + xorl %eax, %eax + xorl %edx, %edx + movl $AMD_AP_MTRR_FIX4k_C0000, %ecx + +CDLoop: + wrmsr + inc %ecx + cmp $AMD_AP_MTRR_FIX4k_D8000, %ecx + jbe CDLoop + + /* Set FFFFFh-E0000h as Uncacheable Memory */ + movl $0x18181818, %eax + movl %eax, %edx + + mov $AMD_AP_MTRR_FIX4k_E0000, %ecx + +EFLoop: + wrmsr + inc %ecx + cmp $AMD_AP_MTRR_FIX4k_F8000, %ecx + jbe EFLoop + + /* If IBV provided settings for Fixed-Sized MTRRs, + * overwrite the default settings. */ + cmp $0, %esi /*.if ((esi != 0) && (esi != 0FFFFFFFFh)) */ + jz 4f + cmp $0xFFFFFFFF, %esi + jz 4f + 5: + mov (%esi), %ecx /* (AP_MTRR_SETTINGS ptr [esi]).MsrAddr */ + /* While we are not at the end of the list */ + cmp $CPU_LIST_TERMINAL, %ecx /* .while (ecx != CPU_LIST_TERMINAL)*/ + je 4f + /* TODO - coreboot isn't checking for valid data. + * Ensure that the MSR address is valid for Fixed-Sized MTRRs */ + /*.if ( ((ecx >= AMD_AP_MTRR_FIX4k_C0000) && (ecx <= AMD_AP_MTRR_FIX4k_F8000)) || \ + (ecx == AMD_AP_MTRR_FIX64k_00000) || (ecx == AMD_AP_MTRR_FIX16k_80000 ) || \ + (ecx == AMD_AP_MTRR_FIX16k_A0000)) + */ + mov 4(%esi), %eax /* MsrData */ + mov 8(%esi), %edx /* MsrData */ + wrmsr + /* .endif */ + add $12, %esi /* sizeof (AP_MTRR_SETTINGS) */ + jmp 5b /* .endw */ + 4: /* .endif */ + + /* Enable fixed-range and variable-range MTRRs */ + mov $AMD_MTRR_DEFTYPE, %ecx + rdmsr + bts $MTRR_DEF_TYPE_EN, %eax /* MtrrDefTypeEn */ + bts $MTRR_DEF_TYPE_FIX_EN, %eax /* MtrrDefTypeFixEn */ + wrmsr + + /* Enable Top-of-Memory setting */ + /* Enable use of RdMem/WrMem bits attributes */ + mov $MTRR_SYS_CFG, %ecx + rdmsr + /* TODO: */ + //bts $MTRR_VAR_DRAM_EN, %eax /* Enable */ + btr $MTRR_FIX_DRAM_MOD_EN, %eax /* Disable */ + bts $MTRR_FIX_DRAM_EN, %eax /* Enable */ + wrmsr + + bts $FLAG_IS_PRIMARY, %esi + jmp 3f /* .else ; end if primary core */ + 2: + xor %esi, %esi + 3: /* .endif*/ + +//8: jmp 8b //bad + /* Make sure not to touch any Shared MSR from this point on */ + + AMD_DISABLE_STACK_FAMILY_HOOK + + /* restore variable MTTR6 and MTTR7 to default states */ + bt $FLAG_IS_PRIMARY, %esi /* .if (esi & 1h) */ + jz 6f + movl $AMD_MTRR_VARIABLE_MASK7, %ecx /* clear MTRRPhysBase6 MTRRPhysMask6 */ + xor %eax, %eax /* and MTRRPhysBase7 MTRRPhysMask7 */ + xor %edx, %edx + cmp $AMD_MTRR_VARIABLE_BASE6, %ecx /* .while (cl < 010h) */ + jl 6f + wrmsr + dec %ecx + 6: /* .endw */ + + xor %eax, %eax + +7: + cli + hlt + jmp 7b /* ExecuteHltInstruction */ + + .size ExecuteFinalHltInstruction, .-ExecuteFinalHltInstruction diff --git a/src/vendorcode/amd/agesa/f15/gcccar.inc b/src/vendorcode/amd/agesa/f15/gcccar.inc index 07e3285..423d404 100644 --- a/src/vendorcode/amd/agesa/f15/gcccar.inc +++ b/src/vendorcode/amd/agesa/f15/gcccar.inc @@ -49,6 +49,7 @@ APIC_BASE_ADDRESS = 0x0000001B AMD_MTRR_VARIABLE_BASE0 = 0x0200 AMD_MTRR_VARIABLE_BASE6 = 0x020C +AMD_MTRR_VARIABLE_MASK7 = 0x020F AMD_MTRR_FIX64k_00000 = 0x0250 AMD_MTRR_FIX16k_80000 = 0x0258 AMD_MTRR_FIX16k_A0000 = 0x0259 @@ -61,6 +62,20 @@ AMD_MTRR_FIX4k_E8000 = 0x026D AMD_MTRR_FIX4k_F0000 = 0x026E AMD_MTRR_FIX4k_F8000 = 0x026F +/* Reproduced from AGESA.h */ +AMD_AP_MTRR_FIX64k_00000 = 0x00000250 +AMD_AP_MTRR_FIX16k_80000 = 0x00000258 +AMD_AP_MTRR_FIX16k_A0000 = 0x00000259 +AMD_AP_MTRR_FIX4k_C0000 = 0x00000268 +AMD_AP_MTRR_FIX4k_C8000 = 0x00000269 +AMD_AP_MTRR_FIX4k_D0000 = 0x0000026A +AMD_AP_MTRR_FIX4k_D8000 = 0x0000026B +AMD_AP_MTRR_FIX4k_E0000 = 0x0000026C +AMD_AP_MTRR_FIX4k_E8000 = 0x0000026D +AMD_AP_MTRR_FIX4k_F0000 = 0x0000026E +AMD_AP_MTRR_FIX4k_F8000 = 0x0000026F +CPU_LIST_TERMINAL = 0xFFFFFFFF + AMD_MTRR_DEFTYPE = 0x02FF WB_DRAM_TYPE = 0x1E /* MemType - memory type */ MTRR_DEF_TYPE_EN = 11 /* MtrrDefTypeEn - variable and fixed MTRRs default enabled */

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coreboot October 2012