coreboot October 2012

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Patch set updated for coreboot: 439fbb4 inteltool: fix Makefile
by Stefan Tauner 12 Oct '12

12 Oct '12

Stefan Tauner (stefan.tauner(a)gmx.at) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1573 -gerrit commit 439fbb4d32066294281046436813a10968fc6432 Author: Stefan Tauner <stefan.tauner(a)gmx.at> Date: Fri Oct 12 10:36:49 2012 +0200 inteltool: fix Makefile Note the changed redirection in the CC call. &> is a bashism to reditect both, stdout and stderr, but with other shells this introduces a race condition with the rm command afterwards, because the compiler execution is done in the background/in parallel. This patch also adds the verbatim variable method to define and export test code and the actual libpci test as it is used in flashrom. Change-Id: I08516494828c9f7af168f954f2df027372657867 Signed-off-by: Stefan Tauner <stefan.tauner(a)gmx.at> --- util/inteltool/Makefile | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/util/inteltool/Makefile b/util/inteltool/Makefile index d754005..6c94460 100644 --- a/util/inteltool/Makefile +++ b/util/inteltool/Makefile @@ -53,13 +53,25 @@ distclean: clean dep: @$(CC) $(CFLAGS) -MM *.c > .dependencies +define LIBPCI_TEST +/* Avoid a failing test due to libpci header symbol shadowing breakage */ +#define index shadow_workaround_index +#include <pci/pci.h> +struct pci_access *pacc; +int main(int argc, char **argv) +{ + (void) argc; + (void) argv; + pacc = pci_alloc(); + return 0; +} +endef +export LIBPCI_TEST + pciutils: @printf "\nChecking for pciutils and zlib... " - @$(shell ( printf "#include <pci/pci.h>\n"; \ - printf "struct pci_access *pacc;\n"; \ - printf "int main(int argc, char **argv)\n"; \ - printf "{ pacc = pci_alloc(); return 0; }\n"; ) > .test.c ) - @$(CC) $(CFLAGS) .test.c -o .test $(LDFLAGS) &>/dev/null && \ + @echo "$$LIBPCI_TEST" > .test.c + @$(CC) $(CFLAGS) .test.c -o .test $(LDFLAGS) >/dev/null 2>&1 && \ printf "found.\n" || ( printf "not found.\n\n"; \ printf "Please install pciutils-devel and zlib-devel.\n"; \ printf "See README for more information.\n\n"; \

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Patch set updated for coreboot: 4175511 inteltool: new definitions and cleanup
by Stefan Tauner 12 Oct '12

12 Oct '12

Stefan Tauner (stefan.tauner(a)gmx.at) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1574 -gerrit commit 417551197d9e456e6ec7699be86d14507316311c Author: Stefan Tauner <stefan.tauner(a)gmx.at> Date: Fri Oct 12 08:50:07 2012 +0200 inteltool: new definitions and cleanup - Separate host bridges/DRAM controllers from LPC controllers in supported_chips_list[]. - Refine some names and macros. - Clean up some whitespace errors. - Add IDs and names of... * 5, 6 and 7 Series southbridges * the three latest Core CPU families with integrated memory controllers (the first one is already supported, although it was wrongly named after the PCH) but do not implement any dump routines for them yet. Change-Id: Ief81e57f7c065cafac52e48b6364b57c72fcdf95 Signed-off-by: Stefan Tauner <stefan.tauner(a)gmx.at> --- util/inteltool/inteltool.c | 128 +++++++++++++++++++++++++++++++++------------ util/inteltool/inteltool.h | 28 +++++----- util/inteltool/memory.c | 42 +++++++-------- util/inteltool/pcie.c | 64 +++++++++++------------ 4 files changed, 164 insertions(+), 98 deletions(-) diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 56bbc4a..60e9630 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -30,36 +30,54 @@ #include <unistd.h> #endif +/* + * http://pci-ids.ucw.cz/read/PC/8086 + * http://en.wikipedia.org/wiki/Intel_Tick-Tock + * http://en.wikipedia.org/wiki/List_of_Intel_chipsets + * http://en.wikipedia.org/wiki/Intel_Xeon_chipsets + */ static const struct { uint16_t vendor_id, device_id; char *name; } supported_chips_list[] = { - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX, "82443LX" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX, "82443BX" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_NO_AGP, "82443BX without AGP" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810, "i810" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810DC, "i810-DC100" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810E_MC, "i810E DC-133" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82830M, "i830M" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845, "i845" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865, "i865" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915, "82915G/P/GV/GL/PL/910GL" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945P, "i945P" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GM, "i945GM" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GSE, "i945GSE" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PM965, "PM965" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q965, "Q963/965" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82975X, "i975X" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q35, "Q35" }, + /* Host bridges/DRAM controllers (Northbridges) */ + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX, "443LX" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX, "443BX" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_NO_AGP, "443BX without AGP" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810, "810" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_DC, "810-DC100" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810E_DC, "810E DC-133" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82830M, "830M" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845, "845" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865, "865" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915, "915G/P/GV/GL/PL/910GL" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945P, "945P" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GM, "945GM" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GSE, "945GSE" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82965PM, "965PM" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q965, "Q963/82Q965" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82975X, "975X" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82G33, "P35/G33/G31/P31" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q33, "Q33" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58, "X58" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM65E, "HM65 Express" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GS45, "GS45ME" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q35, "Q35" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82X38, "X38/X48" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_32X0, "3200/3210" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82X4X, "GL40/GS40/GM45/GS45/PM45" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82X58, "X58" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000P, "Intel i5000P Memory Controller Hub" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000X, "Intel i5000X Memory Controller Hub" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000Z, "Intel i5000Z Memory Controller Hub" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000V, "Intel i5000V Memory Controller Hub" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_POULSBO, "SCH Poulsbo" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ATOM_DXXX, "Atom D400/500 Series" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ATOM_NXXX, "Atom N400 Series" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_POULSBO, "SCH Poulsbo" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC, "SCH Poulsbo" }, + /* Host bridges /DRAM controllers integrated in CPUs */ + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_1ST_GEN, "1st generation (Westmere family) Core Processor" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_2ND_GEN, "2nd generation (Sandy family) Core Processor" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_3RD_GEN, "3rd generation (Ivy Bridge family) Core Processor" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_4TH_GEN, "4th generation (Haswell family) Core Processor" }, + /* Southbridges (LPC controllers) */ + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "371AB/EB/MB" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10R, "ICH10R" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9DH, "ICH9DH" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9DO, "ICH9DO" }, @@ -81,14 +99,58 @@ static const struct { { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH2, "ICH2" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH0, "ICH0" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH, "ICH" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "82371AB/EB/MB" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X44, "82X38/X48" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_32X0, "3200/3210" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I63XX, "Intel 63xx I/O Controller Hub" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000P, "Intel i5000P Memory Controller Hub" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000X, "Intel i5000X Memory Controller Hub" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000Z, "Intel i5000Z Memory Controller Hub" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000V, "Intel i5000V Memory Controller Hub" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I63XX, "631xESB/632xESB/3100" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC, "SCH Poulsbo" }, + { PCI_VENDOR_ID_INTEL, 0x3b00, "3400 Desktop" }, + { PCI_VENDOR_ID_INTEL, 0x3b01, "3400 Mobile" }, + { PCI_VENDOR_ID_INTEL, 0x3b02, "P55" }, + { PCI_VENDOR_ID_INTEL, 0x3b03, "PM55" }, + { PCI_VENDOR_ID_INTEL, 0x3b06, "H55" }, + { PCI_VENDOR_ID_INTEL, 0x3b07, "QM57" }, + { PCI_VENDOR_ID_INTEL, 0x3b08, "H57" }, + { PCI_VENDOR_ID_INTEL, 0x3b09, "HM55" }, + { PCI_VENDOR_ID_INTEL, 0x3b0a, "Q57" }, + { PCI_VENDOR_ID_INTEL, 0x3b0b, "HM57" }, + { PCI_VENDOR_ID_INTEL, 0x3b0d, "3400 Mobile SFF" }, + { PCI_VENDOR_ID_INTEL, 0x3b0e, "B55" }, + { PCI_VENDOR_ID_INTEL, 0x3b0f, "QS57" }, + { PCI_VENDOR_ID_INTEL, 0x3b12, "3400" }, + { PCI_VENDOR_ID_INTEL, 0x3b14, "3420" }, + { PCI_VENDOR_ID_INTEL, 0x3b16, "3450" }, + { PCI_VENDOR_ID_INTEL, 0x3b1e, "B55" }, + { PCI_VENDOR_ID_INTEL, 0x1c44, "Z68" }, + { PCI_VENDOR_ID_INTEL, 0x1c46, "P67" }, + { PCI_VENDOR_ID_INTEL, 0x1c47, "UM67" }, + { PCI_VENDOR_ID_INTEL, 0x1c49, "HM65" }, + { PCI_VENDOR_ID_INTEL, 0x1c4a, "H67" }, + { PCI_VENDOR_ID_INTEL, 0x1c4b, "HM67" }, + { PCI_VENDOR_ID_INTEL, 0x1c4c, "Q65" }, + { PCI_VENDOR_ID_INTEL, 0x1c4d, "QS67" }, + { PCI_VENDOR_ID_INTEL, 0x1c4e, "Q67" }, + { PCI_VENDOR_ID_INTEL, 0x1c4f, "QM67" }, + { PCI_VENDOR_ID_INTEL, 0x1c50, "B65" }, + { PCI_VENDOR_ID_INTEL, 0x1c52, "C202" }, + { PCI_VENDOR_ID_INTEL, 0x1c54, "C204" }, + { PCI_VENDOR_ID_INTEL, 0x1c56, "C206" }, + { PCI_VENDOR_ID_INTEL, 0x1c5c, "H61" }, + { PCI_VENDOR_ID_INTEL, 0x1d40, "X79" }, + { PCI_VENDOR_ID_INTEL, 0x1d41, "X79" }, + { PCI_VENDOR_ID_INTEL, 0x1e44, "Z77" }, + { PCI_VENDOR_ID_INTEL, 0x1e46, "Z75" }, + { PCI_VENDOR_ID_INTEL, 0x1e47, "Q77" }, + { PCI_VENDOR_ID_INTEL, 0x1e48, "Q75" }, + { PCI_VENDOR_ID_INTEL, 0x1e49, "B75" }, + { PCI_VENDOR_ID_INTEL, 0x1e4a, "H77" }, + { PCI_VENDOR_ID_INTEL, 0x1e53, "C216" }, + { PCI_VENDOR_ID_INTEL, 0x1e55, "QM77" }, + { PCI_VENDOR_ID_INTEL, 0x1e56, "QS77" }, + { PCI_VENDOR_ID_INTEL, 0x1e57, "HM77" }, + { PCI_VENDOR_ID_INTEL, 0x1e58, "UM77" }, + { PCI_VENDOR_ID_INTEL, 0x1e59, "HM76" }, + { PCI_VENDOR_ID_INTEL, 0x1e5d, "HM75" }, + { PCI_VENDOR_ID_INTEL, 0x1e5e, "HM70" }, + { PCI_VENDOR_ID_INTEL, 0x1e5f, "NM70" }, + { PCI_VENDOR_ID_INTEL, 0x2310, "DH89xxCC" }, }; #ifndef __DARWIN__ @@ -309,7 +371,7 @@ int main(int argc, char *argv[]) * left-shifted "Extended Model" fields. * http://download.intel.com/design/processor/applnots/24161832.pdf */ - printf("Intel CPU: Processor Type: %x, Family %x, Model %x, Stepping %x\n", + printf("CPU: Processor Type: %x, Family %x, Model %x, Stepping %x\n", (id >> 12) & 0x3, ((id >> 8) & 0xf) + ((id >> 20) & 0xff), ((id >> 12) & 0xf0) + ((id >> 4) & 0xf), (id & 0xf)); @@ -321,10 +383,10 @@ int main(int argc, char *argv[]) if (sb->device_id == supported_chips_list[i].device_id) sbname = supported_chips_list[i].name; - printf("Intel Northbridge: %04x:%04x (%s)\n", + printf("Northbridge: %04x:%04x (%s)\n", nb->vendor_id, nb->device_id, nbname); - printf("Intel Southbridge: %04x:%04x (%s)\n", + printf("Southbridge: %04x:%04x (%s)\n", sb->vendor_id, sb->device_id, sbname); /* Now do the deed */ diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index aa8a292..7ef2d8d 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -63,27 +63,27 @@ #define PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC 0x8119 #define PCI_DEVICE_ID_INTEL_82810 0x7120 -#define PCI_DEVICE_ID_INTEL_82810DC 0x7122 -#define PCI_DEVICE_ID_INTEL_82810E_MC 0x7124 +#define PCI_DEVICE_ID_INTEL_82810_DC 0x7122 +#define PCI_DEVICE_ID_INTEL_82810E_DC 0x7124 #define PCI_DEVICE_ID_INTEL_82830M 0x3575 #define PCI_DEVICE_ID_INTEL_82845 0x1a30 #define PCI_DEVICE_ID_INTEL_82865 0x2570 #define PCI_DEVICE_ID_INTEL_82915 0x2580 #define PCI_DEVICE_ID_INTEL_82945P 0x2770 #define PCI_DEVICE_ID_INTEL_82945GM 0x27a0 -#define PCI_DEVICE_ID_INTEL_82945GSE 0x27ac -#define PCI_DEVICE_ID_INTEL_PM965 0x2a00 -#define PCI_DEVICE_ID_INTEL_Q965 0x2990 +#define PCI_DEVICE_ID_INTEL_82945GSE 0x27ac +#define PCI_DEVICE_ID_INTEL_82965PM 0x2a00 +#define PCI_DEVICE_ID_INTEL_82Q965 0x2990 #define PCI_DEVICE_ID_INTEL_82975X 0x277c #define PCI_DEVICE_ID_INTEL_82Q35 0x29b0 #define PCI_DEVICE_ID_INTEL_82G33 0x29c0 #define PCI_DEVICE_ID_INTEL_82Q33 0x29d0 -#define PCI_DEVICE_ID_INTEL_X44 0x29e0 +#define PCI_DEVICE_ID_INTEL_82X38 0x29e0 #define PCI_DEVICE_ID_INTEL_32X0 0x29f0 -#define PCI_DEVICE_ID_INTEL_GS45 0x2a40 -#define PCI_DEVICE_ID_INTEL_X58 0x3405 -#define PCI_DEVICE_ID_INTEL_SCH_POULSBO 0x8100 -#define PCI_DEVICE_ID_INTEL_ATOM_DXXX 0xa000 +#define PCI_DEVICE_ID_INTEL_82X4X 0x2a40 +#define PCI_DEVICE_ID_INTEL_82X58 0x3405 +#define PCI_DEVICE_ID_INTEL_SCH_POULSBO 0x8100 +#define PCI_DEVICE_ID_INTEL_ATOM_DXXX 0xa000 #define PCI_DEVICE_ID_INTEL_I63XX 0x2670 #define PCI_DEVICE_ID_INTEL_I5000X 0x25c0 @@ -92,7 +92,7 @@ #define PCI_DEVICE_ID_INTEL_I5000P 0x25d8 /* untested, but almost identical to D-series */ -#define PCI_DEVICE_ID_INTEL_ATOM_NXXX 0xa010 +#define PCI_DEVICE_ID_INTEL_ATOM_NXXX 0xa010 #define PCI_DEVICE_ID_INTEL_82443LX 0x7180 /* 82443BX has a different device ID if AGP is disabled (hardware-wise). */ @@ -102,7 +102,11 @@ /* 82371AB/EB/MB use the same device ID value. */ #define PCI_DEVICE_ID_INTEL_82371XX 0x7110 -#define PCI_DEVICE_ID_INTEL_HM65E 0x0104 +/* Intel starts counting these generations with the integration of the DRAM controller */ +#define PCI_DEVICE_ID_INTEL_CORE_1ST_GEN 0x0044 /* Westmere */ +#define PCI_DEVICE_ID_INTEL_CORE_2ND_GEN 0x0104 /* Sandy Bridge */ +#define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN 0x0154 /* Ivy Bridge */ +#define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN 0x0c04 /* Haswell */ #define ARRAY_SIZE(a) ((int)(sizeof(a) / sizeof((a)[0]))) diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c index d66ee48..a68da60 100644 --- a/util/inteltool/memory.c +++ b/util/inteltool/memory.c @@ -108,20 +108,20 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc) case PCI_DEVICE_ID_INTEL_82945GM: case PCI_DEVICE_ID_INTEL_82945GSE: case PCI_DEVICE_ID_INTEL_82945P: - case PCI_DEVICE_ID_INTEL_82975X: + case PCI_DEVICE_ID_INTEL_82975X: mchbar_phys = pci_read_long(nb, 0x44) & 0xfffffffe; break; - case PCI_DEVICE_ID_INTEL_PM965: - case PCI_DEVICE_ID_INTEL_82Q35: - case PCI_DEVICE_ID_INTEL_82G33: - case PCI_DEVICE_ID_INTEL_82Q33: - mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe; - mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; - break; - case PCI_DEVICE_ID_INTEL_Q965: + case PCI_DEVICE_ID_INTEL_82965PM: + case PCI_DEVICE_ID_INTEL_82Q35: + case PCI_DEVICE_ID_INTEL_82G33: + case PCI_DEVICE_ID_INTEL_82Q33: + mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe; + mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; + break; + case PCI_DEVICE_ID_INTEL_82Q965: case PCI_DEVICE_ID_INTEL_ATOM_DXXX: case PCI_DEVICE_ID_INTEL_ATOM_NXXX: - mchbar_phys = pci_read_long(nb, 0x48); + mchbar_phys = pci_read_long(nb, 0x48); /* Test if bit 0 of the MCHBAR reg is 1 to enable memory reads. * If it isn't, try to set it. This may fail, because there is @@ -131,33 +131,33 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc) if(!(mchbar_phys & 1)) { - printf("Access to the MCHBAR is currently disabled, "\ - "attempting to enable.\n"); + printf("Access to the MCHBAR is currently disabled, " + "attempting to enable.\n"); mchbar_phys |= 0x1; pci_write_long(nb, 0x48, mchbar_phys); - if(pci_read_long(nb, 0x48) & 1) + if(pci_read_long(nb, 0x48) & 1) printf("Enabled successfully.\n"); else printf("Enable FAILED!\n"); } mchbar_phys &= 0xfffffffe; - mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; - break; + mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; + break; case PCI_DEVICE_ID_INTEL_82443LX: case PCI_DEVICE_ID_INTEL_82443BX: case PCI_DEVICE_ID_INTEL_82810: - case PCI_DEVICE_ID_INTEL_82810E_MC: - case PCI_DEVICE_ID_INTEL_82810DC: + case PCI_DEVICE_ID_INTEL_82810E_DC: + case PCI_DEVICE_ID_INTEL_82810_DC: case PCI_DEVICE_ID_INTEL_82830M: printf("This northbridge does not have MCHBAR.\n"); return 1; - case PCI_DEVICE_ID_INTEL_GS45: - case PCI_DEVICE_ID_INTEL_X44: + case PCI_DEVICE_ID_INTEL_82X4X: + case PCI_DEVICE_ID_INTEL_82X38: case PCI_DEVICE_ID_INTEL_32X0: mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe; mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; - break; - case PCI_DEVICE_ID_INTEL_HM65E: + break; + case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN: mchbar_phys = pci_read_long(nb, 0x48) & 0xffff8000; mch_registers = sandybridge_mch_registers; size = ARRAY_SIZE(sandybridge_mch_registers); diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c index a7429a0..bb63586 100644 --- a/util/inteltool/pcie.c +++ b/util/inteltool/pcie.c @@ -94,22 +94,22 @@ int print_epbar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_82975X: epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; break; - case PCI_DEVICE_ID_INTEL_PM965: - case PCI_DEVICE_ID_INTEL_Q965: - case PCI_DEVICE_ID_INTEL_82Q35: - case PCI_DEVICE_ID_INTEL_82G33: - case PCI_DEVICE_ID_INTEL_82Q33: - case PCI_DEVICE_ID_INTEL_X44: + case PCI_DEVICE_ID_INTEL_82965PM: + case PCI_DEVICE_ID_INTEL_82Q965: + case PCI_DEVICE_ID_INTEL_82Q35: + case PCI_DEVICE_ID_INTEL_82G33: + case PCI_DEVICE_ID_INTEL_82Q33: + case PCI_DEVICE_ID_INTEL_82X38: case PCI_DEVICE_ID_INTEL_32X0: - case PCI_DEVICE_ID_INTEL_GS45: + case PCI_DEVICE_ID_INTEL_82X4X: case PCI_DEVICE_ID_INTEL_ATOM_DXXX: case PCI_DEVICE_ID_INTEL_ATOM_NXXX: - epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; - epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32; - break; + epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; + epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32; + break; case PCI_DEVICE_ID_INTEL_82810: - case PCI_DEVICE_ID_INTEL_82810DC: - case PCI_DEVICE_ID_INTEL_82810E_MC: + case PCI_DEVICE_ID_INTEL_82810_DC: + case PCI_DEVICE_ID_INTEL_82810E_DC: case PCI_DEVICE_ID_INTEL_82830M: case PCI_DEVICE_ID_INTEL_82865: printf("This northbridge does not have EPBAR.\n"); @@ -156,29 +156,29 @@ int print_dmibar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_82975X: dmibar_phys = pci_read_long(nb, 0x4c) & 0xfffffffe; break; - case PCI_DEVICE_ID_INTEL_PM965: - case PCI_DEVICE_ID_INTEL_Q965: + case PCI_DEVICE_ID_INTEL_82965PM: + case PCI_DEVICE_ID_INTEL_82Q965: case PCI_DEVICE_ID_INTEL_82Q35: case PCI_DEVICE_ID_INTEL_82G33: case PCI_DEVICE_ID_INTEL_82Q33: - case PCI_DEVICE_ID_INTEL_X44: + case PCI_DEVICE_ID_INTEL_82X38: case PCI_DEVICE_ID_INTEL_32X0: - case PCI_DEVICE_ID_INTEL_GS45: + case PCI_DEVICE_ID_INTEL_82X4X: case PCI_DEVICE_ID_INTEL_ATOM_DXXX: case PCI_DEVICE_ID_INTEL_ATOM_NXXX: dmibar_phys = pci_read_long(nb, 0x68) & 0xfffffffe; dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32; break; case PCI_DEVICE_ID_INTEL_82810: - case PCI_DEVICE_ID_INTEL_82810DC: - case PCI_DEVICE_ID_INTEL_82810E_MC: + case PCI_DEVICE_ID_INTEL_82810_DC: + case PCI_DEVICE_ID_INTEL_82810E_DC: case PCI_DEVICE_ID_INTEL_82865: printf("This northbridge does not have DMIBAR.\n"); return 1; - case PCI_DEVICE_ID_INTEL_X58: + case PCI_DEVICE_ID_INTEL_82X58: dmibar_phys = pci_read_long(nb, 0x50) & 0xfffff000; break; - case PCI_DEVICE_ID_INTEL_HM65E: + case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN: dmibar_phys = pci_read_long(nb, 0x68) & 0xfffff000; dmi_registers = sandybridge_dmi_registers; size = ARRAY_SIZE(sandybridge_dmi_registers); @@ -251,22 +251,22 @@ int print_pciexbar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_82975X: pciexbar_reg = pci_read_long(nb, 0x48); break; - case PCI_DEVICE_ID_INTEL_PM965: - case PCI_DEVICE_ID_INTEL_Q965: - case PCI_DEVICE_ID_INTEL_82Q35: - case PCI_DEVICE_ID_INTEL_82G33: - case PCI_DEVICE_ID_INTEL_82Q33: - case PCI_DEVICE_ID_INTEL_X44: + case PCI_DEVICE_ID_INTEL_82965PM: + case PCI_DEVICE_ID_INTEL_82Q965: + case PCI_DEVICE_ID_INTEL_82Q35: + case PCI_DEVICE_ID_INTEL_82G33: + case PCI_DEVICE_ID_INTEL_82Q33: + case PCI_DEVICE_ID_INTEL_82X38: case PCI_DEVICE_ID_INTEL_32X0: - case PCI_DEVICE_ID_INTEL_GS45: + case PCI_DEVICE_ID_INTEL_82X4X: case PCI_DEVICE_ID_INTEL_ATOM_DXXX: case PCI_DEVICE_ID_INTEL_ATOM_NXXX: - pciexbar_reg = pci_read_long(nb, 0x60); - pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32; - break; + pciexbar_reg = pci_read_long(nb, 0x60); + pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32; + break; case PCI_DEVICE_ID_INTEL_82810: - case PCI_DEVICE_ID_INTEL_82810DC: - case PCI_DEVICE_ID_INTEL_82810E_MC: + case PCI_DEVICE_ID_INTEL_82810_DC: + case PCI_DEVICE_ID_INTEL_82810E_DC: case PCI_DEVICE_ID_INTEL_82865: printf("Error: This northbridge does not have PCIEXBAR.\n"); return 1;

1 0

New patch to review for coreboot: f6a90be inteltool: new definitions and cleanup
by Stefan Tauner 12 Oct '12

12 Oct '12

Stefan Tauner (stefan.tauner(a)gmx.at) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1574 -gerrit commit f6a90bed83329227b7db4f3cf95ae9148e0fa2d6 Author: Stefan Tauner <stefan.tauner(a)gmx.at> Date: Fri Oct 12 08:50:07 2012 +0200 inteltool: new definitions and cleanup - Separate host bridges/DRAM controllers from LPC controllers in supported_chips_list[]. - Refine some names and macros. - Add IDs and names of... * 5, 6 and 7 Series southbridges * the three latest Core CPU families with integrated memory controllers (the first one is already supported, although it was wrongly named after the PCH) but do not implement any dump routines for them yet. Change-Id: Ief81e57f7c065cafac52e48b6364b57c72fcdf95 Signed-off-by: Stefan Tauner <stefan.tauner(a)gmx.at> --- util/inteltool/inteltool.c | 128 +++++++++++++++++++++++++++++++++------------ util/inteltool/inteltool.h | 28 +++++----- util/inteltool/memory.c | 14 ++--- util/inteltool/pcie.c | 40 +++++++------- 4 files changed, 138 insertions(+), 72 deletions(-) diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 56bbc4a..60e9630 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -30,36 +30,54 @@ #include <unistd.h> #endif +/* + * http://pci-ids.ucw.cz/read/PC/8086 + * http://en.wikipedia.org/wiki/Intel_Tick-Tock + * http://en.wikipedia.org/wiki/List_of_Intel_chipsets + * http://en.wikipedia.org/wiki/Intel_Xeon_chipsets + */ static const struct { uint16_t vendor_id, device_id; char *name; } supported_chips_list[] = { - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX, "82443LX" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX, "82443BX" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_NO_AGP, "82443BX without AGP" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810, "i810" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810DC, "i810-DC100" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810E_MC, "i810E DC-133" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82830M, "i830M" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845, "i845" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865, "i865" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915, "82915G/P/GV/GL/PL/910GL" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945P, "i945P" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GM, "i945GM" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GSE, "i945GSE" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PM965, "PM965" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q965, "Q963/965" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82975X, "i975X" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q35, "Q35" }, + /* Host bridges/DRAM controllers (Northbridges) */ + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX, "443LX" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX, "443BX" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_NO_AGP, "443BX without AGP" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810, "810" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_DC, "810-DC100" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810E_DC, "810E DC-133" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82830M, "830M" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845, "845" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865, "865" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915, "915G/P/GV/GL/PL/910GL" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945P, "945P" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GM, "945GM" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GSE, "945GSE" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82965PM, "965PM" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q965, "Q963/82Q965" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82975X, "975X" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82G33, "P35/G33/G31/P31" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q33, "Q33" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58, "X58" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM65E, "HM65 Express" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GS45, "GS45ME" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q35, "Q35" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82X38, "X38/X48" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_32X0, "3200/3210" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82X4X, "GL40/GS40/GM45/GS45/PM45" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82X58, "X58" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000P, "Intel i5000P Memory Controller Hub" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000X, "Intel i5000X Memory Controller Hub" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000Z, "Intel i5000Z Memory Controller Hub" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000V, "Intel i5000V Memory Controller Hub" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_POULSBO, "SCH Poulsbo" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ATOM_DXXX, "Atom D400/500 Series" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ATOM_NXXX, "Atom N400 Series" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_POULSBO, "SCH Poulsbo" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC, "SCH Poulsbo" }, + /* Host bridges /DRAM controllers integrated in CPUs */ + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_1ST_GEN, "1st generation (Westmere family) Core Processor" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_2ND_GEN, "2nd generation (Sandy family) Core Processor" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_3RD_GEN, "3rd generation (Ivy Bridge family) Core Processor" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_4TH_GEN, "4th generation (Haswell family) Core Processor" }, + /* Southbridges (LPC controllers) */ + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "371AB/EB/MB" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10R, "ICH10R" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9DH, "ICH9DH" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9DO, "ICH9DO" }, @@ -81,14 +99,58 @@ static const struct { { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH2, "ICH2" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH0, "ICH0" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH, "ICH" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "82371AB/EB/MB" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X44, "82X38/X48" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_32X0, "3200/3210" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I63XX, "Intel 63xx I/O Controller Hub" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000P, "Intel i5000P Memory Controller Hub" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000X, "Intel i5000X Memory Controller Hub" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000Z, "Intel i5000Z Memory Controller Hub" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000V, "Intel i5000V Memory Controller Hub" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I63XX, "631xESB/632xESB/3100" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC, "SCH Poulsbo" }, + { PCI_VENDOR_ID_INTEL, 0x3b00, "3400 Desktop" }, + { PCI_VENDOR_ID_INTEL, 0x3b01, "3400 Mobile" }, + { PCI_VENDOR_ID_INTEL, 0x3b02, "P55" }, + { PCI_VENDOR_ID_INTEL, 0x3b03, "PM55" }, + { PCI_VENDOR_ID_INTEL, 0x3b06, "H55" }, + { PCI_VENDOR_ID_INTEL, 0x3b07, "QM57" }, + { PCI_VENDOR_ID_INTEL, 0x3b08, "H57" }, + { PCI_VENDOR_ID_INTEL, 0x3b09, "HM55" }, + { PCI_VENDOR_ID_INTEL, 0x3b0a, "Q57" }, + { PCI_VENDOR_ID_INTEL, 0x3b0b, "HM57" }, + { PCI_VENDOR_ID_INTEL, 0x3b0d, "3400 Mobile SFF" }, + { PCI_VENDOR_ID_INTEL, 0x3b0e, "B55" }, + { PCI_VENDOR_ID_INTEL, 0x3b0f, "QS57" }, + { PCI_VENDOR_ID_INTEL, 0x3b12, "3400" }, + { PCI_VENDOR_ID_INTEL, 0x3b14, "3420" }, + { PCI_VENDOR_ID_INTEL, 0x3b16, "3450" }, + { PCI_VENDOR_ID_INTEL, 0x3b1e, "B55" }, + { PCI_VENDOR_ID_INTEL, 0x1c44, "Z68" }, + { PCI_VENDOR_ID_INTEL, 0x1c46, "P67" }, + { PCI_VENDOR_ID_INTEL, 0x1c47, "UM67" }, + { PCI_VENDOR_ID_INTEL, 0x1c49, "HM65" }, + { PCI_VENDOR_ID_INTEL, 0x1c4a, "H67" }, + { PCI_VENDOR_ID_INTEL, 0x1c4b, "HM67" }, + { PCI_VENDOR_ID_INTEL, 0x1c4c, "Q65" }, + { PCI_VENDOR_ID_INTEL, 0x1c4d, "QS67" }, + { PCI_VENDOR_ID_INTEL, 0x1c4e, "Q67" }, + { PCI_VENDOR_ID_INTEL, 0x1c4f, "QM67" }, + { PCI_VENDOR_ID_INTEL, 0x1c50, "B65" }, + { PCI_VENDOR_ID_INTEL, 0x1c52, "C202" }, + { PCI_VENDOR_ID_INTEL, 0x1c54, "C204" }, + { PCI_VENDOR_ID_INTEL, 0x1c56, "C206" }, + { PCI_VENDOR_ID_INTEL, 0x1c5c, "H61" }, + { PCI_VENDOR_ID_INTEL, 0x1d40, "X79" }, + { PCI_VENDOR_ID_INTEL, 0x1d41, "X79" }, + { PCI_VENDOR_ID_INTEL, 0x1e44, "Z77" }, + { PCI_VENDOR_ID_INTEL, 0x1e46, "Z75" }, + { PCI_VENDOR_ID_INTEL, 0x1e47, "Q77" }, + { PCI_VENDOR_ID_INTEL, 0x1e48, "Q75" }, + { PCI_VENDOR_ID_INTEL, 0x1e49, "B75" }, + { PCI_VENDOR_ID_INTEL, 0x1e4a, "H77" }, + { PCI_VENDOR_ID_INTEL, 0x1e53, "C216" }, + { PCI_VENDOR_ID_INTEL, 0x1e55, "QM77" }, + { PCI_VENDOR_ID_INTEL, 0x1e56, "QS77" }, + { PCI_VENDOR_ID_INTEL, 0x1e57, "HM77" }, + { PCI_VENDOR_ID_INTEL, 0x1e58, "UM77" }, + { PCI_VENDOR_ID_INTEL, 0x1e59, "HM76" }, + { PCI_VENDOR_ID_INTEL, 0x1e5d, "HM75" }, + { PCI_VENDOR_ID_INTEL, 0x1e5e, "HM70" }, + { PCI_VENDOR_ID_INTEL, 0x1e5f, "NM70" }, + { PCI_VENDOR_ID_INTEL, 0x2310, "DH89xxCC" }, }; #ifndef __DARWIN__ @@ -309,7 +371,7 @@ int main(int argc, char *argv[]) * left-shifted "Extended Model" fields. * http://download.intel.com/design/processor/applnots/24161832.pdf */ - printf("Intel CPU: Processor Type: %x, Family %x, Model %x, Stepping %x\n", + printf("CPU: Processor Type: %x, Family %x, Model %x, Stepping %x\n", (id >> 12) & 0x3, ((id >> 8) & 0xf) + ((id >> 20) & 0xff), ((id >> 12) & 0xf0) + ((id >> 4) & 0xf), (id & 0xf)); @@ -321,10 +383,10 @@ int main(int argc, char *argv[]) if (sb->device_id == supported_chips_list[i].device_id) sbname = supported_chips_list[i].name; - printf("Intel Northbridge: %04x:%04x (%s)\n", + printf("Northbridge: %04x:%04x (%s)\n", nb->vendor_id, nb->device_id, nbname); - printf("Intel Southbridge: %04x:%04x (%s)\n", + printf("Southbridge: %04x:%04x (%s)\n", sb->vendor_id, sb->device_id, sbname); /* Now do the deed */ diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index aa8a292..7ef2d8d 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -63,27 +63,27 @@ #define PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC 0x8119 #define PCI_DEVICE_ID_INTEL_82810 0x7120 -#define PCI_DEVICE_ID_INTEL_82810DC 0x7122 -#define PCI_DEVICE_ID_INTEL_82810E_MC 0x7124 +#define PCI_DEVICE_ID_INTEL_82810_DC 0x7122 +#define PCI_DEVICE_ID_INTEL_82810E_DC 0x7124 #define PCI_DEVICE_ID_INTEL_82830M 0x3575 #define PCI_DEVICE_ID_INTEL_82845 0x1a30 #define PCI_DEVICE_ID_INTEL_82865 0x2570 #define PCI_DEVICE_ID_INTEL_82915 0x2580 #define PCI_DEVICE_ID_INTEL_82945P 0x2770 #define PCI_DEVICE_ID_INTEL_82945GM 0x27a0 -#define PCI_DEVICE_ID_INTEL_82945GSE 0x27ac -#define PCI_DEVICE_ID_INTEL_PM965 0x2a00 -#define PCI_DEVICE_ID_INTEL_Q965 0x2990 +#define PCI_DEVICE_ID_INTEL_82945GSE 0x27ac +#define PCI_DEVICE_ID_INTEL_82965PM 0x2a00 +#define PCI_DEVICE_ID_INTEL_82Q965 0x2990 #define PCI_DEVICE_ID_INTEL_82975X 0x277c #define PCI_DEVICE_ID_INTEL_82Q35 0x29b0 #define PCI_DEVICE_ID_INTEL_82G33 0x29c0 #define PCI_DEVICE_ID_INTEL_82Q33 0x29d0 -#define PCI_DEVICE_ID_INTEL_X44 0x29e0 +#define PCI_DEVICE_ID_INTEL_82X38 0x29e0 #define PCI_DEVICE_ID_INTEL_32X0 0x29f0 -#define PCI_DEVICE_ID_INTEL_GS45 0x2a40 -#define PCI_DEVICE_ID_INTEL_X58 0x3405 -#define PCI_DEVICE_ID_INTEL_SCH_POULSBO 0x8100 -#define PCI_DEVICE_ID_INTEL_ATOM_DXXX 0xa000 +#define PCI_DEVICE_ID_INTEL_82X4X 0x2a40 +#define PCI_DEVICE_ID_INTEL_82X58 0x3405 +#define PCI_DEVICE_ID_INTEL_SCH_POULSBO 0x8100 +#define PCI_DEVICE_ID_INTEL_ATOM_DXXX 0xa000 #define PCI_DEVICE_ID_INTEL_I63XX 0x2670 #define PCI_DEVICE_ID_INTEL_I5000X 0x25c0 @@ -92,7 +92,7 @@ #define PCI_DEVICE_ID_INTEL_I5000P 0x25d8 /* untested, but almost identical to D-series */ -#define PCI_DEVICE_ID_INTEL_ATOM_NXXX 0xa010 +#define PCI_DEVICE_ID_INTEL_ATOM_NXXX 0xa010 #define PCI_DEVICE_ID_INTEL_82443LX 0x7180 /* 82443BX has a different device ID if AGP is disabled (hardware-wise). */ @@ -102,7 +102,11 @@ /* 82371AB/EB/MB use the same device ID value. */ #define PCI_DEVICE_ID_INTEL_82371XX 0x7110 -#define PCI_DEVICE_ID_INTEL_HM65E 0x0104 +/* Intel starts counting these generations with the integration of the DRAM controller */ +#define PCI_DEVICE_ID_INTEL_CORE_1ST_GEN 0x0044 /* Westmere */ +#define PCI_DEVICE_ID_INTEL_CORE_2ND_GEN 0x0104 /* Sandy Bridge */ +#define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN 0x0154 /* Ivy Bridge */ +#define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN 0x0c04 /* Haswell */ #define ARRAY_SIZE(a) ((int)(sizeof(a) / sizeof((a)[0]))) diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c index d66ee48..3513466 100644 --- a/util/inteltool/memory.c +++ b/util/inteltool/memory.c @@ -111,14 +111,14 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc) case PCI_DEVICE_ID_INTEL_82975X: mchbar_phys = pci_read_long(nb, 0x44) & 0xfffffffe; break; - case PCI_DEVICE_ID_INTEL_PM965: + case PCI_DEVICE_ID_INTEL_82965PM: case PCI_DEVICE_ID_INTEL_82Q35: case PCI_DEVICE_ID_INTEL_82G33: case PCI_DEVICE_ID_INTEL_82Q33: mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe; mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; break; - case PCI_DEVICE_ID_INTEL_Q965: + case PCI_DEVICE_ID_INTEL_82Q965: case PCI_DEVICE_ID_INTEL_ATOM_DXXX: case PCI_DEVICE_ID_INTEL_ATOM_NXXX: mchbar_phys = pci_read_long(nb, 0x48); @@ -146,18 +146,18 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc) case PCI_DEVICE_ID_INTEL_82443LX: case PCI_DEVICE_ID_INTEL_82443BX: case PCI_DEVICE_ID_INTEL_82810: - case PCI_DEVICE_ID_INTEL_82810E_MC: - case PCI_DEVICE_ID_INTEL_82810DC: + case PCI_DEVICE_ID_INTEL_82810E_DC: + case PCI_DEVICE_ID_INTEL_82810_DC: case PCI_DEVICE_ID_INTEL_82830M: printf("This northbridge does not have MCHBAR.\n"); return 1; - case PCI_DEVICE_ID_INTEL_GS45: - case PCI_DEVICE_ID_INTEL_X44: + case PCI_DEVICE_ID_INTEL_82X4X: + case PCI_DEVICE_ID_INTEL_82X38: case PCI_DEVICE_ID_INTEL_32X0: mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe; mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; break; - case PCI_DEVICE_ID_INTEL_HM65E: + case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN: mchbar_phys = pci_read_long(nb, 0x48) & 0xffff8000; mch_registers = sandybridge_mch_registers; size = ARRAY_SIZE(sandybridge_mch_registers); diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c index a7429a0..0d61547 100644 --- a/util/inteltool/pcie.c +++ b/util/inteltool/pcie.c @@ -94,22 +94,22 @@ int print_epbar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_82975X: epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; break; - case PCI_DEVICE_ID_INTEL_PM965: - case PCI_DEVICE_ID_INTEL_Q965: + case PCI_DEVICE_ID_INTEL_82965PM: + case PCI_DEVICE_ID_INTEL_82Q965: case PCI_DEVICE_ID_INTEL_82Q35: case PCI_DEVICE_ID_INTEL_82G33: case PCI_DEVICE_ID_INTEL_82Q33: - case PCI_DEVICE_ID_INTEL_X44: + case PCI_DEVICE_ID_INTEL_82X38: case PCI_DEVICE_ID_INTEL_32X0: - case PCI_DEVICE_ID_INTEL_GS45: + case PCI_DEVICE_ID_INTEL_82X4X: case PCI_DEVICE_ID_INTEL_ATOM_DXXX: case PCI_DEVICE_ID_INTEL_ATOM_NXXX: epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32; break; case PCI_DEVICE_ID_INTEL_82810: - case PCI_DEVICE_ID_INTEL_82810DC: - case PCI_DEVICE_ID_INTEL_82810E_MC: + case PCI_DEVICE_ID_INTEL_82810_DC: + case PCI_DEVICE_ID_INTEL_82810E_DC: case PCI_DEVICE_ID_INTEL_82830M: case PCI_DEVICE_ID_INTEL_82865: printf("This northbridge does not have EPBAR.\n"); @@ -156,29 +156,29 @@ int print_dmibar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_82975X: dmibar_phys = pci_read_long(nb, 0x4c) & 0xfffffffe; break; - case PCI_DEVICE_ID_INTEL_PM965: - case PCI_DEVICE_ID_INTEL_Q965: + case PCI_DEVICE_ID_INTEL_82965PM: + case PCI_DEVICE_ID_INTEL_82Q965: case PCI_DEVICE_ID_INTEL_82Q35: case PCI_DEVICE_ID_INTEL_82G33: case PCI_DEVICE_ID_INTEL_82Q33: - case PCI_DEVICE_ID_INTEL_X44: + case PCI_DEVICE_ID_INTEL_82X38: case PCI_DEVICE_ID_INTEL_32X0: - case PCI_DEVICE_ID_INTEL_GS45: + case PCI_DEVICE_ID_INTEL_82X4X: case PCI_DEVICE_ID_INTEL_ATOM_DXXX: case PCI_DEVICE_ID_INTEL_ATOM_NXXX: dmibar_phys = pci_read_long(nb, 0x68) & 0xfffffffe; dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32; break; case PCI_DEVICE_ID_INTEL_82810: - case PCI_DEVICE_ID_INTEL_82810DC: - case PCI_DEVICE_ID_INTEL_82810E_MC: + case PCI_DEVICE_ID_INTEL_82810_DC: + case PCI_DEVICE_ID_INTEL_82810E_DC: case PCI_DEVICE_ID_INTEL_82865: printf("This northbridge does not have DMIBAR.\n"); return 1; - case PCI_DEVICE_ID_INTEL_X58: + case PCI_DEVICE_ID_INTEL_82X58: dmibar_phys = pci_read_long(nb, 0x50) & 0xfffff000; break; - case PCI_DEVICE_ID_INTEL_HM65E: + case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN: dmibar_phys = pci_read_long(nb, 0x68) & 0xfffff000; dmi_registers = sandybridge_dmi_registers; size = ARRAY_SIZE(sandybridge_dmi_registers); @@ -251,22 +251,22 @@ int print_pciexbar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_82975X: pciexbar_reg = pci_read_long(nb, 0x48); break; - case PCI_DEVICE_ID_INTEL_PM965: - case PCI_DEVICE_ID_INTEL_Q965: + case PCI_DEVICE_ID_INTEL_82965PM: + case PCI_DEVICE_ID_INTEL_82Q965: case PCI_DEVICE_ID_INTEL_82Q35: case PCI_DEVICE_ID_INTEL_82G33: case PCI_DEVICE_ID_INTEL_82Q33: - case PCI_DEVICE_ID_INTEL_X44: + case PCI_DEVICE_ID_INTEL_82X38: case PCI_DEVICE_ID_INTEL_32X0: - case PCI_DEVICE_ID_INTEL_GS45: + case PCI_DEVICE_ID_INTEL_82X4X: case PCI_DEVICE_ID_INTEL_ATOM_DXXX: case PCI_DEVICE_ID_INTEL_ATOM_NXXX: pciexbar_reg = pci_read_long(nb, 0x60); pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32; break; case PCI_DEVICE_ID_INTEL_82810: - case PCI_DEVICE_ID_INTEL_82810DC: - case PCI_DEVICE_ID_INTEL_82810E_MC: + case PCI_DEVICE_ID_INTEL_82810_DC: + case PCI_DEVICE_ID_INTEL_82810E_DC: case PCI_DEVICE_ID_INTEL_82865: printf("Error: This northbridge does not have PCIEXBAR.\n"); return 1;

1 0

New patch to review for coreboot: 59d339f inteltool: fix Makefile
by Stefan Tauner 12 Oct '12

12 Oct '12

Stefan Tauner (stefan.tauner(a)gmx.at) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1573 -gerrit commit 59d339fd69fb909f0cb34963f9ab0db86fd19894 Author: Stefan Tauner <stefan.tauner(a)gmx.at> Date: Fri Oct 12 05:18:19 2012 +0200 inteltool: fix Makefile Note the removed '&' in the CC call. This introduced a race condition with the following rm command, because the compiler execution was done in the background/in parallel. This patch also adds the verbatim variable method to define and export test code and the actual libpci test as it is used in flashrom. Change-Id: I08516494828c9f7af168f954f2df027372657867 Signed-off-by: Stefan Tauner <stefan.tauner(a)gmx.at> --- util/inteltool/Makefile | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/util/inteltool/Makefile b/util/inteltool/Makefile index d754005..9803baa 100644 --- a/util/inteltool/Makefile +++ b/util/inteltool/Makefile @@ -53,13 +53,25 @@ distclean: clean dep: @$(CC) $(CFLAGS) -MM *.c > .dependencies +define LIBPCI_TEST +/* Avoid a failing test due to libpci header symbol shadowing breakage */ +#define index shadow_workaround_index +#include <pci/pci.h> +struct pci_access *pacc; +int main(int argc, char **argv) +{ + (void) argc; + (void) argv; + pacc = pci_alloc(); + return 0; +} +endef +export LIBPCI_TEST + pciutils: @printf "\nChecking for pciutils and zlib... " - @$(shell ( printf "#include <pci/pci.h>\n"; \ - printf "struct pci_access *pacc;\n"; \ - printf "int main(int argc, char **argv)\n"; \ - printf "{ pacc = pci_alloc(); return 0; }\n"; ) > .test.c ) - @$(CC) $(CFLAGS) .test.c -o .test $(LDFLAGS) &>/dev/null && \ + @echo "$$LIBPCI_TEST" > .test.c + @$(CC) $(CFLAGS) .test.c -o .test $(LDFLAGS) >/dev/null && \ printf "found.\n" || ( printf "not found.\n\n"; \ printf "Please install pciutils-devel and zlib-devel.\n"; \ printf "See README for more information.\n\n"; \

1 0

New patch to review for coreboot: 680a64b Update .gitignore
by Stefan Tauner 12 Oct '12

12 Oct '12

Stefan Tauner (stefan.tauner(a)gmx.at) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1572 -gerrit commit 680a64b4a61ddb2ff622341447bc7d8829f10756 Author: Stefan Tauner <stefan.tauner(a)gmx.at> Date: Wed Oct 10 07:33:46 2012 +0200 Update .gitignore Add... - generated documentation files - all kinds of stuff in the util subdirectories Change-Id: I47ab6d239aae725f54413f03424f40002ac5a275 Signed-off-by: Stefan Tauner <stefan.tauner(a)gmx.at> --- .gitignore | 27 +++++++++++++++++++++++++-- documentation/Makefile | 5 +++-- 2 files changed, 28 insertions(+), 4 deletions(-) diff --git a/.gitignore b/.gitignore index ea10be7..15d1c17 100644 --- a/.gitignore +++ b/.gitignore @@ -44,15 +44,38 @@ util/crossgcc/w32api-*/ # Ignore Kdevelop project file .kdev4 +util/*/.dependencies +util/*/.test +util/cbfstool/cbfstool +util/dumpmmcr/dumpmmcr util/ectool/ectool +util/getpir/getpir +util/ifdtool/ifdtool util/inteltool/.dependencies util/inteltool/inteltool +util/k8resdump/k8resdump +util/lbtdump/lbtdump +util/mptable/mptable util/msrtool/Makefile util/msrtool/Makefile.deps util/msrtool/msrtool +util/nrv2b/nrv2b util/nvramtool/.dependencies util/nvramtool/nvramtool -util/superiotool/superiotool +util/optionlist/Options.wiki util/romcc/romcc -util/romcc/tests/*.S-O2-mmmx util/romcc/tests/fail_test*.S +util/romcc/tests/*.S-O2-mmmx +util/superiotool/superiotool +util/vgabios/testbios + +documentation/*.aux +documentation/*.idx +documentation/*.log +documentation/*.toc +documentation/*.out +documentation/*.pdf +documentation/mainboardkconfig.tex +documentation/skconfig.tex +documentation/cpukconfig.tex +documentation/socketfkconfig.tex diff --git a/documentation/Makefile b/documentation/Makefile index 84ac0b5..df6df66 100644 --- a/documentation/Makefile +++ b/documentation/Makefile @@ -6,8 +6,9 @@ PDFLATEX=pdflatex -t a4 FIGS=codeflow.pdf hypertransport.pdf +PAPERS=LinuxBIOS-AMD64.pdf Kconfig.pdf -all: LinuxBIOS-AMD64.pdf Kconfig.pdf +all: $(PAPERS) SVG2PDF=$(shell which svg2pdf) INKSCAPE=$(shell which inkscape) @@ -67,5 +68,5 @@ clean: rm -f *.aux *.idx *.log *.toc *.out $(FIGS) mainboardkconfig.tex skconfig.tex cpukconfig.tex socketfkconfig.tex distclean: clean - rm -f LinuxBIOS-AMD64.pdf Kconfig.pdf + rm -f $(PAPERS)

1 0

Re: [coreboot] [SeaBIOS] USB Problems geode lx800
by Christian Gmeiner 11 Oct '12

11 Oct '12

Christian Gmeiner, MSc 2012/10/11 Christian Gmeiner <christian.gmeiner(a)gmail.com>: > 2012/10/11 Kevin O'Connor <kevin(a)koconnor.net>: >> On Tue, Oct 09, 2012 at 02:31:05PM +0200, Christian Gmeiner wrote: >>> 2012/10/9 Kevin O'Connor <kevin(a)koconnor.net>: >>> > On Mon, Oct 08, 2012 at 02:14:03PM +0200, Christian Gmeiner wrote: >>> >> HI all >>> >> >>> >> I am running into some usb problems with coreboot & seabios: >>> > Can you set the debug level to 8 and post the whole log? Also, for >>> > timeout issues, having timestamps (via tools/readserial.py tool) >>> > sometimes helps. >>> >>> Attached >> >> Hrmm, I guess you've disabled threads in your config? >> > yep... > > >> From your log, I see: >> >> [14:23:00.5] ehci_send_bulk qh=0x000ef680 dir=0 data=0x00006d55 size=31^M >> [14:23:00.5] ehci_send_bulk qh=0x000ef700 dir=128 data=0x00006e3c size=36^M >> [14:23:00.5] ehci_send_bulk qh=0x000ef700 dir=128 data=0x00006d8f size=13^M >> [14:23:05.5] WARNING - Timeout at ehci_wait_td:542!^M >> [14:23:05.5] ehci pipe=0x000ef700 cur=00000000 tok=00000000 next=6b80 td=0x00006b80 >> +status=d0d80^M >> [14:23:05.5] USB transmission failed^M >> [14:23:05.5] Unable to configure USB MSC drive.^M >> >> This looks like the transfer is stalling in the cdb_get_inquiry() call >> as part of scsi_init_drive(). The drive is identified okay and at >> least some transfers look okay, so it doesn't appear to be a >> controller issue. >> >> I've been told some USB sticks are very picky about init order, but >> I'm surprised to see that this is occuring for you on a variety of USB >> sticks. >> >> It's possible to verify that a stall has occurred - print out >> tds[i].token for all tds in ehci_send_bulk() on the error path. >> >> Does this device still have problems if you soft-reset after a failed >> boot? >> > > Here are the results with some more debug: > > Cold Reboot > ------------ > > |0f7a5000| pmm_malloc zone=0x0f7afe87 handle=ffffffff size=192 > align=40 ret=0x0f7a7bc0 (detail=0x0f7a7d70) > |0f7a5000| ehci_control: td at phys(f7a7bc0): status: 80 : token 80e80 > |0f7a5000| - cerr: 3, total_len: 0 > |0f7a5000| ehci_control: td at phys(f7a7c00): status: 0 : token d00 > |0f7a5000| - cerr: 3, total_len: 0 > |0f7a5000| ehci_control: td at phys(f7a7c40): status: 0 : token 0 > |0f7a5000| - cerr: 0, total_len: 0 > |0f7a5000| pmm_free 0x0f7a7bc0 (detail=0x0f7a7d70) > |0f7a5000| ehci_alloc_async_pipe 0x0f7a9090 2 > |0f7a5000| pmm_malloc zone=0x0f7afe7f handle=ffffffff size=92 align=80 > ret=0x000ef700 (detail=0x0f7a7d70) > |0f7a5000| ehci_alloc_async_pipe 0x0f7a9090 2 > |0f7a5000| pmm_malloc zone=0x0f7afe7f handle=ffffffff size=92 align=80 > ret=0x000ef680 (detail=0x0f7a7d10) > |0f7a5000| ehci_control 0x0f7a7cd0 (dir=128 cmd=8 data=1) > |0f7a5000| pmm_malloc zone=0x0f7afe87 handle=ffffffff size=192 > align=40 ret=0x0f7a7bc0 (detail=0x0f7a7ce0) > |0f7a5000| ehci_control: td at phys(f7a7bc0): status: 80 : token 80e80 > |0f7a5000| - cerr: 3, total_len: 0 > |0f7a5000| ehci_control: td at phys(f7a7c00): status: 0 : token d00 > |0f7a5000| - cerr: 3, total_len: 0 > |0f7a5000| ehci_control: td at phys(f7a7c40): status: 0 : token 1c00 > |0f7a5000| - cerr: 3, total_len: 0 > |0f7a5000| pmm_free 0x0f7a7bc0 (detail=0x0f7a7ce0) > |0f7a5000| pmm_malloc zone=0x0f7afe83 handle=ffffffff size=48 align=10 > ret=0x000fdae0 (detail=0x0f7a7ce0) > |0f7a5000| usb_cmd_data id=0x000fdae0 write=0 count=1 bs=36 buf=0x0f7a5f3c > |0f7a5000| cbw to device > |0f7a5000| ehci_send_bulk qh=0x000ef680 dir=0 data=0x0f7a5e65 size=31 > |0f7a5000| before setup: td at phys(f7a5c80): status: 0 : token 0 > |0f7a5000| - cerr: 0, total_len: 0 > |0f7a5000| ehci_send_bulk: td at phys(f7a5c80): status: 80 : token c80 > |0f7a5000| - cerr: 3, total_len: 0 > |0f7a5000| Data-In from the device to the host - 36 bytes > |0f7a5000| ehci_send_bulk qh=0x000ef700 dir=128 data=0x0f7a5f3c size=36 > |0f7a5000| before setup: td at phys(f7a5c80): status: 0 : token 0 > |0f7a5000| - cerr: 0, total_len: 0 > |0f7a5000| ehci_send_bulk: td at phys(f7a5c80): status: 80 : token d80 > |0f7a5000| - cerr: 3, total_len: 0 > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token d80 > |0f7a5000| - cerr: 3, total_len: 0 > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token d80 > |0f7a5000| - cerr: 3, total_len: 0 > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token d80 > |0f7a5000| - cerr: 3, total_len: 0 > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token d80 > |0f7a5000| - cerr: 3, total_len: 0 > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token d80 > |0f7a5000| - cerr: 3, total_len: 0 > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token d80 > |0f7a5000| - cerr: 3, total_len: 0 > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token d80 > |0f7a5000| - cerr: 3, total_len: 0 > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token d80 > |0f7a5000| - cerr: 3, total_len: 0 > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token d80 > |0f7a5000| - cerr: 3, total_len: 0 > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token d80 > |0f7a5000| - cerr: 3, total_len: 0 > > > Warm Reboot > ----------- > > 0f7a5000| pmm_free 0x0f7a7bc0 (detail=0x0f7a7d70) > |0f7a5000| ehci_alloc_async_pipe 0x0f7a9090 2 > |0f7a5000| pmm_malloc zone=0x0f7afe7f handle=ffffffff size=92 align=80 > ret=0x000ef700 (detail=0x0f7a7d70) > |0f7a5000| ehci_alloc_async_pipe 0x0f7a9090 2 > |0f7a5000| pmm_malloc zone=0x0f7afe7f handle=ffffffff size=92 align=80 > ret=0x000ef680 (detail=0x0f7a7d10) > |0f7a5000| ehci_control 0x0f7a7cd0 (dir=128 cmd=8 data=1) > |0f7a5000| pmm_malloc zone=0x0f7afe87 handle=ffffffff size=192 > align=40 ret=0x0f7a7bc0 (detail=0x0f7a7ce0) > |0f7a5000| ehci_control: td at phys(f7a7bc0): status: 80 : token 80e80 > |0f7a5000| - cerr: 3, total_len: 0 > |0f7a5000| ehci_control: td at phys(f7a7c00): status: 0 : token d00 > |0f7a5000| - cerr: 3, total_len: 0 > |0f7a5000| ehci_control: td at phys(f7a7c40): status: 0 : token 1c00 > |0f7a5000| - cerr: 3, total_len: 0 > |0f7a5000| pmm_free 0x0f7a7bc0 (detail=0x0f7a7ce0) > |0f7a5000| pmm_malloc zone=0x0f7afe83 handle=ffffffff size=48 align=10 > ret=0x000fdae0 (detail=0x0f7a7ce0) > |0f7a5000| usb_cmd_data id=0x000fdae0 write=0 count=1 bs=36 buf=0x0f7a5f3c > |0f7a5000| cbw to device > |0f7a5000| ehci_send_bulk qh=0x000ef680 dir=0 data=0x0f7a5e65 size=31 > |0f7a5000| before setup: td at phys(f7a5c80): status: 0 : token 0 > |0f7a5000| - cerr: 0, total_len: 0 > |0f7a5000| ehci_send_bulk: td at phys(f7a5c80): status: 80 : token c80 > |0f7a5000| - cerr: 3, total_len: 0 > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token c80 > |0f7a5000| - cerr: 3, total_len: 0 > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token c80 > |0f7a5000| - cerr: 3, total_len: 0 > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token c80 > |0f7a5000| - cerr: 3, total_len: 0 > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token c80 > |0f7a5000| - cerr: 3, total_len: 0 > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token c80 > |0f7a5000| - cerr: 3, total_len: 0 > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token c80 > |0f7a5000| - cerr: 3, total_len: 0 > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token c80 > |0f7a5000| - cerr: 3, total_len: 0 > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token c80 > |0f7a5000| - cerr: 3, total_len: 0 > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token c80 > |0f7a5000| - cerr: 3, total_len: 0 > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token c80 > |0f7a5000| - cerr: 3, total_len: 0 > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token c80 > |0f7a5000| - cerr: 3, total_len: 0 > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token c80 > |0f7a5000| - cerr: 3, total_len: 0 > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token c80 > |0f7a5000| - cerr: 3, total_len: 0 > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token c80 > |0f7a5000| - cerr: 3, total_len: 0 > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token c80 > |0f7a5000| - cerr: 3, total_len: 0 > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token c80 > |0f7a5000| - cerr: 3, total_len: 0 > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token c80 > |0f7a5000| - cerr: 3, total_len: 0 > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token c80 > |0f7a5000| - cerr: 3, total_len: 0 > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token c80 > |0f7a5000| - cerr: 3, total_len: 0 > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token c80 > |0f7a5000| - cerr: 3, total_len: 0 > > > This is the used patch: > > diff --git a/src/usb-ehci.c b/src/usb-ehci.c > index 2676615..92a9c60 100644 > --- a/src/usb-ehci.c > +++ b/src/usb-ehci.c > @@ -178,6 +178,14 @@ check_ehci_ports(struct usb_ehci_s *cntl) > * Setup > ****************************************************************/ > > +static void dump_td(struct ehci_qtd *td, const char *func) > +{ > + u32 addr = (u32)td; > + dprintf(1, "%s: td at phys(%x): status: %x : token %x\n", func, > addr, td->token & QTD_STS_MASK, td->token); > + dprintf(1, "- cerr: %x, total_len: %x\n", (td->token & > QTD_CERR_MASK) >> QTD_CERR_SHIFT, > + (td->token & QTD_LENGTH_MASK) >> QTD_LENGTH_SHIFT); > +} > + > // Wait for next USB async frame to start - for ensuring safe memory release. > static void > ehci_waittick(struct usb_ehci_s *cntl) > @@ -535,6 +543,9 @@ ehci_wait_td(struct ehci_pipe *pipe, struct > ehci_qtd *td, int timeout) > status = td->token; > if (!(status & QTD_STS_ACTIVE)) > break; > + > + dump_td(td, __func__); > + > if (check_tsc(end)) { > u32 cur = GET_LOWFLAT(pipe->qh.current); > u32 tok = GET_LOWFLAT(pipe->qh.token); > @@ -633,6 +644,7 @@ ehci_control(struct usb_pipe *p, int dir, const > void *cmd, int cmdsize > int i, ret=0; > for (i=0; i<3; i++) { > struct ehci_qtd *td = &tds[i]; > + dump_td(td, __func__); > ret = ehci_wait_td(pipe, td, 500); > if (ret) > break; > @@ -665,18 +677,25 @@ ehci_send_bulk(struct usb_pipe *p, int dir, void > *data, int datasize) > struct ehci_qtd *td = &tds[tdpos++ % STACKQTDS]; > int ret = ehci_wait_td(pipe, td, 5000); > if (ret) > + { > + dump_td(td, "ehci_send_bulk ERROR2"); > return -1; > + } > > struct ehci_qtd *nexttd_fl = MAKE_FLATPTR(GET_SEG(SS) > , &tds[tdpos % STACKQTDS]); > > + dump_td(td, "before setup"); > + > int transfer = fillTDbuffer(td, maxpacket, data, datasize); > td->qtd_next = (transfer==datasize ? EHCI_PTR_TERM : (u32)nexttd_fl); > td->alt_next = EHCI_PTR_TERM; > barrier(); > - td->token = (ehci_explen(transfer) | QTD_STS_ACTIVE > + td->token = (/*ehci_explen(transfer) | */QTD_STS_ACTIVE > | (dir ? QTD_PID_IN : QTD_PID_OUT) | ehci_maxerr(3)); > > + dump_td(td, __func__); > + > data += transfer; > datasize -= transfer; > } > @@ -685,7 +704,10 @@ ehci_send_bulk(struct usb_pipe *p, int dir, void > *data, int datasize) > struct ehci_qtd *td = &tds[tdpos++ % STACKQTDS]; > int ret = ehci_wait_td(pipe, td, 5000); > if (ret) > + { > + dump_td(td, "ehci_send_bulk ERROR2"); > return -1; > + } > } > > return 0; > > > > greets Here is the log of filo using libpayload [16:40:24.5] FILO version 0.6.0 (christian@chgm-pc) Thu Oct 11 16:12:26 CEST 2012 [16:40:24.5] 00:0f.5 2095:1022.5 EHCI controller [16:40:24.7] highspeed device [16:40:24.7] wait_for_tds: td at phys(1f6b2260): status: 0 token: 80000e00 [16:40:24.8] - cerr: 3, total_len: 0 [16:40:24.8] wait_for_tds done: td at phys(1f6b2260): status: 0 token: 80000e00 [16:40:24.8] - cerr: 3, total_len: 0 [16:40:24.8] moving from 148260 to 1482a0 [16:40:24.8] wait_for_tds: td at phys(1f6b22a0): status: 0 token: 100 [16:40:24.8] - cerr: 0, total_len: 0 [16:40:24.8] wait_for_tds: td at phys(1f6b2260): status: 0 token: 80000e00 [16:40:24.8] - cerr: 3, total_len: 0 [16:40:24.8] wait_for_tds done: td at phys(1f6b2260): status: 0 token: 80000e00 [16:40:24.9] - cerr: 3, total_len: 0 [16:40:24.9] moving from 148260 to 1482a0 [16:40:24.9] wait_for_tds: td at phys(1f6b22a0): status: 0 token: d00 [16:40:25.0] - cerr: 3, total_len: 0 [16:40:25.0] wait_for_tds done: td at phys(1f6b22a0): status: 0 token: d00 [16:40:25.0] - cerr: 3, total_len: 0 [16:40:25.1] moving from 1482a0 to 1482e0 [16:40:25.1] wait_for_tds: td at phys(1f6b22e0): status: 0 token: 1000 [16:40:25.2] - cerr: 0, total_len: 0 [16:40:25.2] maxPacketSize0: 40 [16:40:25.2] wait_for_tds: td at phys(1f6b2260): status: 0 token: 80000e00 [16:40:25.2] - cerr: 3, total_len: 0 [16:40:25.3] wait_for_tds done: td at phys(1f6b2260): status: 0 token: 80000e00 [16:40:25.3] - cerr: 3, total_len: 0 [16:40:25.4] moving from 148260 to 1482a0 [16:40:25.4] wait_for_tds: td at phys(1f6b22a0): status: 0 token: d00 [16:40:25.5] - cerr: 3, total_len: 0 [16:40:25.5] wait_for_tds done: td at phys(1f6b22a0): status: 0 token: d00 [16:40:25.5] - cerr: 3, total_len: 0 [16:40:25.6] moving from 1482a0 to 1482e0 [16:40:25.6] wait_for_tds: td at phys(1f6b22e0): status: 0 token: 1000 [16:40:25.7] - cerr: 0, total_len: 0 [16:40:25.7] * found device (0x1370:0x3252, USB 2.0) [16:40:25.7] device has 1 configurations [16:40:25.7] wait_for_tds: td at phys(1f6b2260): status: 0 token: 80000e00 [16:40:25.8] - cerr: 3, total_len: 0 [16:40:25.8] wait_for_tds done: td at phys(1f6b2260): status: 0 token: 80000e00 [16:40:25.9] - cerr: 3, total_len: 0 [16:40:25.9] moving from 148260 to 1482a0 [16:40:26.0] wait_for_tds: td at phys(1f6b22a0): status: 0 token: d00 [16:40:26.0] - cerr: 3, total_len: 0 [16:40:26.0] wait_for_tds done: td at phys(1f6b22a0): status: 0 token: d00 [16:40:26.1] - cerr: 3, total_len: 0 [16:40:26.1] moving from 1482a0 to 1482e0 [16:40:26.1] wait_for_tds: td at phys(1f6b22e0): status: 0 token: 1000 [16:40:26.2] - cerr: 0, total_len: 0 [16:40:26.2] wait_for_tds: td at phys(1f6b2260): status: 0 token: 80000e00 [16:40:26.3] - cerr: 3, total_len: 0 [16:40:26.3] wait_for_tds done: td at phys(1f6b2260): status: 0 token: 80000e00 [16:40:26.4] - cerr: 3, total_len: 0 [16:40:26.4] moving from 148260 to 1482a0 [16:40:26.4] wait_for_tds: td at phys(1f6b22a0): status: 0 token: d00 [16:40:26.5] - cerr: 3, total_len: 0 [16:40:26.5] wait_for_tds done: td at phys(1f6b22a0): status: 0 token: d00 [16:40:26.6] - cerr: 3, total_len: 0 [16:40:26.6] moving from 1482a0 to 1482e0 [16:40:26.7] wait_for_tds: td at phys(1f6b22e0): status: 0 token: 1000 [16:40:26.7] - cerr: 0, total_len: 0 [16:40:26.7] wait_for_tds: td at phys(1f6b2260): status: 0 token: 80000e00 [16:40:26.8] - cerr: 3, total_len: 0 [16:40:26.8] wait_for_tds done: td at phys(1f6b2260): status: 0 token: 80000e00 [16:40:26.8] - cerr: 3, total_len: 0 [16:40:26.9] moving from 148260 to 1482a0 [16:40:26.9] wait_for_tds: td at phys(1f6b22a0): status: 0 token: 100 [16:40:27.0] - cerr: 0, total_len: 0 [16:40:27.0] device has 1 interfaces [16:40:27.0] #0 has 2 endpoints, interface 8:6, protocol 50 [16:40:27.0] #1: Endpoint 1 (in), max packet size 200, type bulk [16:40:27.1] #2: Endpoint 2 (out), max packet size 200, type bulk [16:40:27.1] , class: MSC [16:40:27.1] Waiting for device to become ready...ehci_bulk: setup: td at phys(148260): status: 0 token: 0 [16:40:27.2] - cerr: 0, total_len: 0 [16:40:27.2] wait_for_tds: td at phys(1f6b2260): status: 1 token: 80000001 [16:40:27.3] - cerr: 0, total_len: 0 [16:40:27.3] ehci_bulk: setup: td at phys(148260): status: 0 token: 0 [16:40:27.3] - cerr: 0, total_len: 0 [16:40:27.4] wait_for_tds: td at phys(1f6b2260): status: 0 token: 80000100 [16:40:27.4] - cerr: 0, total_len: 0 [16:40:27.5] ehci_bulk: setup: td at phys(148260): status: 0 token: 0 [16:40:27.5] - cerr: 0, total_len: 0 [16:40:27.5] wait_for_tds: td at phys(1f6b2260): status: 1 token: 1 [16:40:27.6] - cerr: 0, total_len: 0 [16:40:27.6] ehci_bulk: setup: td at phys(148260): status: 0 token: 0 [16:40:27.7] - cerr: 0, total_len: 0 [16:40:27.7] wait_for_tds: td at phys(1f6b2260): status: 0 token: 100 [16:40:27.7] - cerr: 0, total_len: 0 [16:40:27.8] ehci_bulk: setup: td at phys(148260): status: 0 token: 0 [16:40:27.8] - cerr: 0, total_len: 0 [16:40:27.9] wait_for_tds: td at phys(1f6b2260): status: 0 token: 80000100 [16:40:27.9] - cerr: 0, total_len: 0 [16:40:28.1] ehci_bulk: setup: td at phys(148260): status: 0 token: 0 [16:40:28.1] - cerr: 0, total_len: 0 [16:40:28.2] wait_for_tds: td at phys(1f6b2260): status: 1 token: 80000001 [16:40:28.2] - cerr: 0, total_len: 0 [16:40:28.2] ehci_bulk: setup: td at phys(148260): status: 0 token: 0 [16:40:28.3] - cerr: 0, total_len: 0 [16:40:28.3] wait_for_tds: td at phys(1f6b2260): status: 0 token: 100 [16:40:28.3] - cerr: 0, total_len: 0 [16:40:28.4] ok. [16:40:28.4] ehci_bulk: setup: td at phys(148260): status: 0 token: 0 [16:40:28.4] - cerr: 0, total_len: 0 [16:40:28.5] wait_for_tds: td at phys(1f6b2260): status: 1 token: 1 [16:40:28.5] - cerr: 0, total_len: 0 [16:40:28.6] ehci_bulk: setup: td at phys(148260): status: 0 token: 0 [16:40:28.6] - cerr: 0, total_len: 0 [16:40:28.6] wait_for_tds: td at phys(1f6b2260): status: 0 token: 80000100 [16:40:28.7] - cerr: 0, total_len: 0 [16:40:28.7] ehci_bulk: setup: td at phys(148260): status: 0 token: 0 [16:40:28.8] - cerr: 0, total_len: 0 [16:40:28.8] wait_for_tds: td at phys(1f6b2260): status: 1 token: 80000001 [16:40:28.9] - cerr: 0, total_len: 0 [16:40:28.9] ehci_bulk: setup: td at phys(148260): status: 0 token: 0 [16:40:28.9] - cerr: 0, total_len: 0 [16:40:29.0] wait_for_tds: td at phys(1f6b2260): status: 0 token: 100 [16:40:29.0] - cerr: 0, total_len: 0 [16:40:29.1] ehci_bulk: setup: td at phys(148260): status: 0 token: 0 [16:40:29.1] - cerr: 0, total_len: 0 [16:40:29.2] wait_for_tds: td at phys(1f6b2260): status: 0 token: 80000100 [16:40:29.2] - cerr: 0, total_len: 0 [16:40:29.2] 15663104 512-byte sectors (8019 MB) [16:40:29.3] 00:0f.4 2094:1022.4 OHCI controller [16:40:29.3] OHCI Version 1.0 [16:40:29.4] ERROR: No such CMOS option (boot_devices) [16:40:29.4] menu: hda3:/boot/filo/menu.lst --- Christian Gmeiner, MSc

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Re: [coreboot] [SeaBIOS] USB Problems geode lx800
by Kevin O'Connor 11 Oct '12

11 Oct '12

On Tue, Oct 09, 2012 at 02:31:05PM +0200, Christian Gmeiner wrote: > 2012/10/9 Kevin O'Connor <kevin(a)koconnor.net>: > > On Mon, Oct 08, 2012 at 02:14:03PM +0200, Christian Gmeiner wrote: > >> HI all > >> > >> I am running into some usb problems with coreboot & seabios: > > Can you set the debug level to 8 and post the whole log? Also, for > > timeout issues, having timestamps (via tools/readserial.py tool) > > sometimes helps. > > Attached Hrmm, I guess you've disabled threads in your config? >From your log, I see: [14:23:00.5] ehci_send_bulk qh=0x000ef680 dir=0 data=0x00006d55 size=31^M [14:23:00.5] ehci_send_bulk qh=0x000ef700 dir=128 data=0x00006e3c size=36^M [14:23:00.5] ehci_send_bulk qh=0x000ef700 dir=128 data=0x00006d8f size=13^M [14:23:05.5] WARNING - Timeout at ehci_wait_td:542!^M [14:23:05.5] ehci pipe=0x000ef700 cur=00000000 tok=00000000 next=6b80 td=0x00006b80 +status=d0d80^M [14:23:05.5] USB transmission failed^M [14:23:05.5] Unable to configure USB MSC drive.^M This looks like the transfer is stalling in the cdb_get_inquiry() call as part of scsi_init_drive(). The drive is identified okay and at least some transfers look okay, so it doesn't appear to be a controller issue. I've been told some USB sticks are very picky about init order, but I'm surprised to see that this is occuring for you on a variety of USB sticks. It's possible to verify that a stall has occurred - print out tds[i].token for all tds in ehci_send_bulk() on the error path. Does this device still have problems if you soft-reset after a failed boot? -Kevin

2 1

Re: [coreboot] how to assign irq to a device
by Andrew Goodbody 11 Oct '12

11 Oct '12

On 10/10/12 12:11, WANG Siyuan wrote: > hi, > i am debugging a mainboard with an external pci network adapter. > the adapter share irq with usb. it seems not correct, so i want to assign > an irq for this adapter. > how to do that? > thank you. 1) PCI interrupts can be shared. It is OK and usual for this to happen. 2) Manually assigning interrupts is pointless, let the firmware or OS do it. It knows what is possible and will do the best that it can. 3) What is possible depends on the motherboard. It may be impossible for those devices to have different IRQs assigned. 4) This is a coreboot mailing list. Is the motherboard using coreboot? If so then please tell us the exact motherboard and where the coreboot code came from. Andrew

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Re: [coreboot] how to assign irq to a device
by Marc Jones 10 Oct '12

10 Oct '12

On Wed, Oct 10, 2012 at 7:19 AM, WANG Siyuan <wangsiyuanbuaa(a)gmail.com> wrote: > hi, ali > thank you. this is an Ethernet controller plugged in PCI slot. maybe it is > also called LAN card. > this card is not plugged in USB slot, it is plugged in PCI slot. > so I think the irq is not right. > > On Wed, Oct 10, 2012 at 7:34 PM, ali hagigat <hagigatali(a)gmail.com> wrote: > >> External PCI network adaptor? >> If it is plugged in PCI slot so it is internal. Is it a LAN card >> plugged into USB slot? >> >> On Wed, Oct 10, 2012 at 2:41 PM, WANG Siyuan <wangsiyuanbuaa(a)gmail.com> >> wrote: >> > hi, >> > i am debugging a mainboard with an external pci network adapter. >> > the adapter share irq with usb. it seems not correct, so i want to assign >> > an irq for this adapter. >> > how to do that? >> > thank you. >> > >> > /proc/interrupt >> > eth1 is an external pci network adapter. i want to assign irq 21 for it. >> > >> > CPU0 CPU1 CPU2 CPU3 CPU4 CPU5 >> > CPU6 CPU7 >> > 0: 59 0 0 0 0 0 >> > 0 0 IO-APIC-edge timer >> > 1: 0 0 1 0 1 1 >> > 0 0 IO-APIC-edge i8042 >> > 7: 1 0 0 0 0 0 >> > 0 0 IO-APIC-edge >> > 8: 0 0 0 0 0 0 >> > 0 0 IO-APIC-edge rtc0 >> > 9: 0 0 0 0 0 0 >> > 0 0 IO-APIC-fasteoi acpi >> > 12: 0 0 0 1 1 0 >> > 1 1 IO-APIC-edge i8042 >> > 14: 0 0 0 0 0 0 >> > 0 0 IO-APIC-edge pata_atiixp >> > 15: 0 0 0 0 0 0 >> > 0 0 IO-APIC-edge pata_atiixp >> > 16: 93 95 80 91 96 94 >> > 98 97 IO-APIC-fasteoi ohci_hcd:usb3, ohci_hcd:usb4 >> > 17: 1 0 1 0 0 0 >> > 0 0 IO-APIC-fasteoi ehci_hcd:usb1 >> > 18: 4 4 4 4 4 4 >> > 2 4 IO-APIC-fasteoi ohci_hcd:usb5, ohci_hcd:usb6, >> > ohci_hcd:usb7 >> > 19: 1 1 0 0 0 0 >> > 0 0 IO-APIC-fasteoi ehci_hcd:usb2, eth1 >> > 22: 672 685 691 692 693 683 >> > 687 681 IO-APIC-fasteoi ahci >> > 296: 119 99 127 87 125 96 >> > 121 105 PCI-MSI-edge eth0-rx-0 >> > 297: 0 0 0 0 0 0 >> > 0 0 PCI-MSI-edge eth0-tx-0 >> > 298: 1 0 0 0 0 0 >> > 0 0 PCI-MSI-edge eth0 >> > 299: 123 125 105 138 93 135 >> > 106 132 PCI-MSI-edge eth2-rx-0 >> > 300: 2 4 4 0 1 2 >> > 1 3 PCI-MSI-edge eth2-tx-0 >> > 301: 0 0 1 0 0 0 >> > 0 2 PCI-MSI-edge eth2 >> > NMI: 0 0 0 0 0 0 >> > 0 0 Non-maskable interrupts >> > LOC: 4050 1673 3943 2348 2519 2963 >> > 3093 1644 Local timer interrupts >> > SPU: 0 0 0 0 0 0 >> > 0 0 Spurious interrupts >> > PMI: 0 0 0 0 0 0 >> > 0 0 Performance monitoring interrupts >> > IWI: 0 0 0 0 0 0 >> > 0 0 IRQ work interrupts >> > RTR: 0 0 0 0 0 0 >> > 0 0 APIC ICR read retries >> > RES: 5454 4177 5477 3690 5121 3822 >> > 5342 3630 Rescheduling interrupts >> > CAL: 44 58 52 57 46 56 >> > 50 59 Function call interrupts >> > TLB: 291 391 291 336 274 344 >> > 237 395 TLB shootdowns >> > TRM: 0 0 0 0 0 0 >> > 0 0 Thermal event interrupts >> > THR: 0 0 0 0 0 0 >> > 0 0 Threshold APIC interrupts >> > MCE: 0 0 0 0 0 0 >> > 0 0 Machine check exceptions >> > MCP: 6 6 6 6 6 6 >> > 6 6 Machine check polls >> > ERR: 1 >> > MIS: 0 >> > >> > >> > -- >> > WANG Siyuan >> > -- >> > coreboot mailing list: coreboot(a)coreboot.org >> > http://www.coreboot.org/mailman/listinfo/coreboot >> > > > > -- > WANG Siyuan > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot It sounds like you have to update the ACPI IRQ routing. Marc -- http://se-eng.com

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Re: [coreboot] [SeaBIOS] USB Problems geode lx800
by Christian Gmeiner 10 Oct '12

10 Oct '12

2012/10/9 Christian Gmeiner <christian.gmeiner(a)gmail.com>: > 2012/10/9 Kevin O'Connor <kevin(a)koconnor.net>: >> On Mon, Oct 08, 2012 at 02:14:03PM +0200, Christian Gmeiner wrote: >>> HI all >>> >>> I am running into some usb problems with coreboot & seabios: >>> >>> >>> init usb >>> pmm_malloc zone=0x1f7afe7f handle=ffffffff size=72 align=10 >>> ret=0x1f7a8860 (detail=0x1f7a88b0) >> [...] >>> >>> Mabye somebody has some hints how to start debugging this and what I >>> should look for. >> >> Hi Christian, >> >> Can you set the debug level to 8 and post the whole log? Also, for >> timeout issues, having timestamps (via tools/readserial.py tool) >> sometimes helps. > > > Attached > >> >> Did this regress, or has it never worked? What type of USB drive are >> you attempting to use? > > > It never worked and tried it with a hand full of different usb sticks. > This one is my target stick, which must work: > > Bus 002 Device 029: ID 1370:3252 Swissbit > Device Descriptor: > bLength 18 > bDescriptorType 1 > bcdUSB 2.00 > bDeviceClass 0 (Defined at Interface level) > bDeviceSubClass 0 > bDeviceProtocol 0 > bMaxPacketSize0 64 > idVendor 0x1370 Swissbit > idProduct 0x3252 > bcdDevice 1.00 > iManufacturer 1 Swissbit > iProduct 2 unitedCONTRAST > iSerial 3 60042417C3000001 > bNumConfigurations 1 > Configuration Descriptor: > bLength 9 > bDescriptorType 2 > wTotalLength 32 > bNumInterfaces 1 > bConfigurationValue 1 > iConfiguration 0 > bmAttributes 0x80 > (Bus Powered) > MaxPower 200mA > Interface Descriptor: > bLength 9 > bDescriptorType 4 > bInterfaceNumber 0 > bAlternateSetting 0 > bNumEndpoints 2 > bInterfaceClass 8 Mass Storage > bInterfaceSubClass 6 SCSI > bInterfaceProtocol 80 Bulk-Only > iInterface 0 > Endpoint Descriptor: > bLength 7 > bDescriptorType 5 > bEndpointAddress 0x81 EP 1 IN > bmAttributes 2 > Transfer Type Bulk > Synch Type None > Usage Type Data > wMaxPacketSize 0x0200 1x 512 bytes > bInterval 255 > Endpoint Descriptor: > bLength 7 > bDescriptorType 5 > bEndpointAddress 0x02 EP 2 OUT > bmAttributes 2 > Transfer Type Bulk > Synch Type None > Usage Type Data > wMaxPacketSize 0x0200 1x 512 bytes > bInterval 255 > Device Qualifier (for other device speed): > bLength 10 > bDescriptorType 6 > bcdUSB 2.00 > bDeviceClass 0 (Defined at Interface level) > bDeviceSubClass 0 > bDeviceProtocol 0 > bMaxPacketSize0 64 > bNumConfigurations 1 > Device Status: 0x0000 > (Bus Powered) > I got access to an ellisys usb explorer and dumped the whole transfer between usb stick and lx800. I started to look at the whole USB stuff this day and I hope we can get it working :) To view the dump you need this: http://www.ellisys.com/products/usbex200/download.php The dump can be found here: https://docs.google.com/open?id=0B_fznDimUHVuTkRfYkE5b0NtRzg greets --- Christian Gmeiner, MSc

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coreboot October 2012