coreboot October 2012

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Patch set updated for coreboot: 386758f Update SeaBIOS stable to the release-1.7.1 commit
by Peter Stuge 16 Oct '12

16 Oct '12

Peter Stuge (peter(a)stuge.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1583 -gerrit commit 386758f46625a3e61b44bc9342f48d261e895091 Author: Peter Stuge <peter(a)stuge.se> Date: Tue Oct 16 02:25:07 2012 +0200 Update SeaBIOS stable to the release-1.7.1 commit Change-Id: I0dffe89c31e45914f795d9ad8efb787b5fdbb7a8 Signed-off-by: Peter Stuge <peter(a)stuge.se> --- payloads/external/SeaBIOS/Makefile.inc | 2 +- src/Kconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index d856f37..5e1df47 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -1,7 +1,7 @@ TAG-$(CONFIG_SEABIOS_MASTER)=origin/master -TAG-$(CONFIG_SEABIOS_STABLE)=385a7d0dec28841a05531cba96c62138c3959fef +TAG-$(CONFIG_SEABIOS_STABLE)=51755c3b5ed9dcdfdef8cee56631d68642bde416 unexport KCONFIG_AUTOCONFIG diff --git a/src/Kconfig b/src/Kconfig index e0062dd..9630e0c 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -508,7 +508,7 @@ choice depends on PAYLOAD_SEABIOS config SEABIOS_STABLE - bool "stable" + bool "1.7.1" help Stable SeaBIOS version config SEABIOS_MASTER

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New patch to review for coreboot: 94686fb Update SeaBIOS stable to the release-1.7.1 commit
by Peter Stuge 16 Oct '12

16 Oct '12

Peter Stuge (peter(a)stuge.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1583 -gerrit commit 94686fbc8598750c96adbdd969969cc95e664c14 Author: Peter Stuge <peter(a)stuge.se> Date: Tue Oct 16 02:25:07 2012 +0200 Update SeaBIOS stable to the release-1.7.1 commit Change-Id: I0dffe89c31e45914f795d9ad8efb787b5fdbb7a8 Signed-off-by: Peter Stuge <peter(a)stuge.se> --- payloads/external/SeaBIOS/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index d856f37..5e1df47 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -1,7 +1,7 @@ TAG-$(CONFIG_SEABIOS_MASTER)=origin/master -TAG-$(CONFIG_SEABIOS_STABLE)=385a7d0dec28841a05531cba96c62138c3959fef +TAG-$(CONFIG_SEABIOS_STABLE)=51755c3b5ed9dcdfdef8cee56631d68642bde416 unexport KCONFIG_AUTOCONFIG

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Re: [coreboot] #188: gcc-4.7 miscompiles coreboot on -Os, -O1, -O2, -O3 in 3 different ways
by ron minnich 15 Oct '12

15 Oct '12

> 2012/10/15 Hristo Venev <mustrumr97(a)gmail.com>: >> Fixed it by using my linux distribution's toolchain but specifying -march=i686 >> Probable reason: some instructions enabled by default by gcc but not enabled at >> early stages of booting. Oh my. What instructions are these? ron

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Re: [coreboot] #188: gcc-4.7 miscompiles coreboot on -Os, -O1, -O2, -O3 in 3 different ways
by Hristo Venev 15 Oct '12

15 Oct '12

It turned out that gcc was trying to use a xmm register. But I had set coreboot to build for qemu. This means SSE is disabled. If I enable SSE from .config, it gets initialized in romstage (I think) so it even compiles with gcc -march=corei7 -O3. Maybe -march should be set by Kconfig according to the CPU. . On Mon, Oct 15, 2012 at 10:56 PM, Idwer Vollering <vidwer(a)gmail.com> wrote: > Please reply with "reply to all", thanks. > > 2012/10/15 Hristo Venev <mustrumr97(a)gmail.com>: >> Fixed it by using my linux distribution's toolchain but specifying -march=i686 >> Probable reason: some instructions enabled by default by gcc but not enabled at >> early stages of booting. > > Hm, I suppose that i686 is not (exactly) the same as -march=i386 (?) > and therefor is not suitable as a generic solution. > >> >> P.S. I didn't see any patches applied to my gcc which are not about >> _FORTIFY_SOURCE/relro/gnu hash.

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Re: [coreboot] #188: gcc-4.7 miscompiles coreboot on -Os, -O1, -O2, -O3 in 3 different ways
by Idwer Vollering 15 Oct '12

15 Oct '12

Please reply with "reply to all", thanks. 2012/10/15 Hristo Venev <mustrumr97(a)gmail.com>: > Fixed it by using my linux distribution's toolchain but specifying -march=i686 > Probable reason: some instructions enabled by default by gcc but not enabled at > early stages of booting. Hm, I suppose that i686 is not (exactly) the same as -march=i386 (?) and therefor is not suitable as a generic solution. > > P.S. I didn't see any patches applied to my gcc which are not about > _FORTIFY_SOURCE/relro/gnu hash.

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Re: [coreboot] #188: gcc-4.7 miscompiles coreboot on -Os, -O1, -O2, -O3 in 3 different ways
by Idwer Vollering 15 Oct '12

15 Oct '12

2012/10/15 Hristo Venev <mustrumr97(a)gmail.com>: > Binutils bug or feature? Rather a distribution feature. http://www.coreboot.org/Development_Guidelines#Required_Toolchain --> "Linux distributions usually modify their compilers in ways incompatible with coreboot. If in doubt, use our toolchain."

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Re: [coreboot] #188: gcc-4.7 miscompiles coreboot on -Os, -O1, -O2, -O3 in 3 different ways
by Peter Stuge 15 Oct '12

15 Oct '12

Idwer Vollering wrote: > > Is it a gcc bug or is it a coreboot bug? > > Actually it is a binutils 'bug'. You should run 'make crossgcc' > (and remove .xcompile) in the top directory, where you run 'make > menuconfig'. make crossgcc removes .xcompile after having built the toolchain. It could still be improved to re-run detection and create a new one, to allow for easy verification before running another make command. //Peter

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Re: [coreboot] #188: gcc-4.7 miscompiles coreboot on -Os, -O1, -O2, -O3 in 3 different ways
by Idwer Vollering 15 Oct '12

15 Oct '12

2012/10/15 Hristo Venev <mustrumr97(a)gmail.com>: > Is it a gcc bug or is it a coreboot bug? Actually it is a binutils 'bug'. You should run 'make crossgcc' (and remove .xcompile) in the top directory, where you run 'make menuconfig'.

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Re: [coreboot] how to assign irq to a device
by Andrew Goodbody 15 Oct '12

15 Oct '12

On 14/10/12 05:12, WANG Siyuan wrote: > hi, Andrew > thank you. this issue has been solved by updating the acpi routing The ACPI routing tables are a description of the underlying hardware configuration. If you have not also changed the hardware configuration then you may well have an invalid ACPI table now. If interrupts are still working with an invalid ACPI table then it probably means the device is using MSI(1), so all this worry about interrupt assignments is a waste of time. Also please always reply to the list. Andrew 1) http://en.wikipedia.org/wiki/Message_Signaled_Interrupts

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Re: [coreboot] how to assign irq to a device
by ali hagigat 15 Oct '12

15 Oct '12

You need to reprogram the config space registers of your PCI bridge or your USB controller to assign a new IRQ for each.

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coreboot October 2012