coreboot October 2012

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Re: [coreboot] [SeaBIOS] USB Problems geode lx800
by Peter Stuge 18 Oct '12

18 Oct '12

Christian Gmeiner wrote: > USB is finally working :) http://dpaste.com/815054/ Very nice! //Peter

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Re: [coreboot] [SeaBIOS] USB Problems geode lx800
by Kevin O'Connor 18 Oct '12

18 Oct '12

On Wed, Oct 17, 2012 at 07:42:33AM +0200, Christian Gmeiner wrote: > 2012/10/17 Kevin O'Connor <kevin(a)koconnor.net>: > > On Tue, Oct 16, 2012 at 04:11:08PM +0200, Christian Gmeiner wrote: > >> I have made some success to get USB working - current SeaBios ehci > >> driver does not support toggling between > >> DATA0 and DATA1. Here is my current patch to get a little bit more running: > > > > The toggle bit should be updated automatically by the controller. It > > should not be necessary to do it manually. If this is impacting your > > results, something subtle must going on. > > > > Maybe you are right (starred at the spec for some minutes), but who > updates the toggle bit in the qh? > > So I think that this line is needed: > pipe->qh.token|= (pipe->pipe.toogle?QTD_TOGGLE:0); The controller is supposed to update the toggle bit in the qh. The same qh is used for all transfers, so it should already be up to date between transfers. It is possible something subtle is going on here. -Kevin

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Patch set updated for coreboot: b068a07 AMD SB800: PCI(E) slots on Persimmon
by Zheng Bao 18 Oct '12

18 Oct '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1098 -gerrit commit b068a0753e63f8ddbeaaa2bc265a456655904b5e Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Fri Oct 12 11:17:20 2012 +0800 AMD SB800: PCI(E) slots on Persimmon (routine.asl):Set the correct device number in the pcie interrupt routine in ACPI asl. The device number is decided by which address pin is connected to IDSEL. Table 3-1: IDSEL Generation Primary Address AD[15::11] Secondary Address AD[31::16] 0 0000 0000 0000 0000 0001 0 0001 0000 0000 0000 0010 0 0010 0000 0000 0000 0100 0 0011 0000 0000 0000 1000 0 0100 0000 0000 0001 0000 0 0101 0000 0000 0010 0000 0 0110 0000 0000 0100 0000 0 0111 0000 0000 1000 0000 0 1000 0000 0001 0000 0000 0 1001 0000 0010 0000 0000 0 1010 0000 0100 0000 0000 0 1011 0000 1000 0000 0000 0 1100 0001 0000 0000 0000 0 1101 0010 0000 0000 0000 0 1110 0100 0000 0000 0000 0 1111 1000 0000 0000 0000 1 xxxx 0000 0000 0000 0000 On persimmon, PCI slot 0's IDSEL is connected to AD19, so the device number is 3. Slot 1's IDSEL is connected to AD20, so the device number is 4. (devicetree.cb): Enable the PCIE bridge which is connected to the PCIE slot. Change-Id: I1b3fb59990e06d7bc7cf19639f2b93dbb7bf9b3e Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/mainboard/amd/persimmon/acpi/routing.asl | 24 ++++++++++++------------ src/mainboard/amd/persimmon/devicetree.cb | 10 +++++----- 2 files changed, 17 insertions(+), 17 deletions(-) diff --git a/src/mainboard/amd/persimmon/acpi/routing.asl b/src/mainboard/amd/persimmon/acpi/routing.asl index d7e4687..24bc809 100644 --- a/src/mainboard/amd/persimmon/acpi/routing.asl +++ b/src/mainboard/amd/persimmon/acpi/routing.asl @@ -391,17 +391,17 @@ Scope(\_SB) { Name(PCIB, Package(){ /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */ - Package(){0x0005FFFF, 0, 0, 0x14 }, - Package(){0x0005FFFF, 1, 0, 0x15 }, - Package(){0x0005FFFF, 2, 0, 0x16 }, - Package(){0x0005FFFF, 3, 0, 0x17 }, - Package(){0x0006FFFF, 0, 0, 0x15 }, - Package(){0x0006FFFF, 1, 0, 0x16 }, - Package(){0x0006FFFF, 2, 0, 0x17 }, - Package(){0x0006FFFF, 3, 0, 0x14 }, - Package(){0x0007FFFF, 0, 0, 0x16 }, - Package(){0x0007FFFF, 1, 0, 0x17 }, - Package(){0x0007FFFF, 2, 0, 0x14 }, - Package(){0x0007FFFF, 3, 0, 0x15 }, + Package(){0x0003FFFF, 0, 0, 0x14 }, + Package(){0x0003FFFF, 1, 0, 0x15 }, + Package(){0x0003FFFF, 2, 0, 0x16 }, + Package(){0x0003FFFF, 3, 0, 0x17 }, + Package(){0x0004FFFF, 0, 0, 0x15 }, + Package(){0x0004FFFF, 1, 0, 0x16 }, + Package(){0x0004FFFF, 2, 0, 0x17 }, + Package(){0x0004FFFF, 3, 0, 0x14 }, + Package(){0x0005FFFF, 0, 0, 0x16 }, + Package(){0x0005FFFF, 1, 0, 0x17 }, + Package(){0x0005FFFF, 2, 0, 0x14 }, + Package(){0x0005FFFF, 3, 0, 0x15 }, }) } diff --git a/src/mainboard/amd/persimmon/devicetree.cb b/src/mainboard/amd/persimmon/devicetree.cb index e5bbca2..da81dc3 100644 --- a/src/mainboard/amd/persimmon/devicetree.cb +++ b/src/mainboard/amd/persimmon/devicetree.cb @@ -28,12 +28,12 @@ chip northbridge/amd/agesa/family14/root_complex # device pci 18.0 on # northbridge chip northbridge/amd/agesa/family14 # PCI side of HT root complex device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 + device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456] device pci 1.1 on end # Internal Multimedia - device pci 4.0 on end # PCIE P2P bridge 0x9604 - device pci 5.0 off end # PCIE P2P bridge 0x9605 - device pci 6.0 off end # PCIE P2P bridge 0x9606 - device pci 7.0 off end # PCIE P2P bridge 0x9607 + device pci 4.0 on end # PCIE P2P bridge on-board NIC + device pci 5.0 off end # PCIE P2P bridge + device pci 6.0 on end # PCIE P2P bridge PCIe slot + device pci 7.0 off end # PCIE P2P bridge device pci 8.0 off end # NB/SB Link P2P bridge end # agesa northbridge

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Re: [coreboot] Generic AMD E350 Support
by Florian Zumbiehl 18 Oct '12

18 Oct '12

Hi, > > I notice that there are already support for the Asus E35M1 > > Please note that the supported boards is the ASRock E350M1. Florian > Zumbiehl tried to make a port for the ASUS E35M1, but for some reason it > failed quite early as far as I am remember. I am putting him in CC just > in case. E35M1-M PRO to be precise. The problem was a mysterious reset that happened in the middle of some code somewhere (IIRC somewhat indeterministically) around RAM controller init or something, details should be in the mailing list archive. I had waited for Frank Vibrans (who AFAIR isn't with AMD anymore?) to analyze the problem and in the meantime had done the port to the K8V-X instead, and then I ran out of time ;-) I intend to look into that again sooner or later, but don't hold your breath for it ... Florian

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Re: [coreboot] Google I/O Chromebox
by Stefan Reinauer 17 Oct '12

17 Oct '12

Hi Chris, some people on this mailing list had success with their ChromeBooks. I don't know if anyone in the community tried the ChromeBox yet, but it should be fairly similar. You will need an external flash writer, and/or disable the machine's hardware write protection for the SPI flash (the little white 2pin jumper next to the RAM) For debugging, you can hook up a SuperIO card (if you find one) to the board's LPC connector (right by the WP switch), or an OxPCIe serial port card or USB debug port for console. The code in coreboot's master branch should work fine. You will need the blobs from the blobs repository, too. Stefan * Chris Bobrowitz <nctightend(a)gmail.com> [121003 23:49]: > Hello! > > I was at Google I/O this past summer and have finally had time to sit down > with the chromebox. > > My version has the Intel i5 processor and am looking to flash a custom BIOS > for the reason of flashing linux to the machine. > > What is the current supported version of coreboot or is this even possible. > > Sincerely, > > Chris > > -- > *Chris Bobrowitz* > FCB IT Help-Desk Technician > FCB Information Technology Dpt. > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot >

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Re: [coreboot] Generic AMD E350 Support
by Peter Stuge 17 Oct '12

17 Oct '12

Graeme Russ wrote: > >> MX25L1606E > > > > MXIC yep. Solder something to it so that you can reprogram. Use the > > I was thinking of buying an 8 pin SOIP test clip Yes, that of course works too. > > VCC on the chip for programming. Hold the mainboard in reset while > > you drive the SPI signals. I would check first that the chipset > > doesn't sink too much current. (Ampmeter+2k2 resistor between VCC > > and one signal at a time. The current should stay well under 1.5mA.) > > I have an in-circuit programmer I used on another board (which had a > breakout header for the SPI flash). Do you think I could just use this > with the board powered-down? Unsure. You would then be powering one of the 3v3 rails (where the flash chip is connected) from the programmer, without powering any other rail on the board. The southbridge may not like it at all when your programmer drives the SPI pins in that state. //Peter

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Re: [coreboot] Generic AMD E350 Support
by Peter Stuge 17 Oct '12

17 Oct '12

Graeme Russ wrote: > I've taken some hi-res photos using a DLSR with a macro lens. Where can I see them? Can upload at http://ge.tt/ or another favorite image hoster. //Peter

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Re: [coreboot] [SeaBIOS] USB Problems geode lx800
by Kevin O'Connor 16 Oct '12

16 Oct '12

On Tue, Oct 16, 2012 at 04:11:08PM +0200, Christian Gmeiner wrote: > 2012/10/15 Kevin O'Connor <kevin(a)koconnor.net>: > > On Sun, Oct 14, 2012 at 07:48:00PM +0000, Christian Gmeiner wrote: > >> On 11 Oct 2012 16:42, "Christian Gmeiner" <christian.gmeiner(a)gmail.com> > >> wrote: > >> > 2012/10/11 Christian Gmeiner <christian.gmeiner(a)gmail.com>: > >> > > 2012/10/11 Kevin O'Connor <kevin(a)koconnor.net>: > >> > >> On Tue, Oct 09, 2012 at 02:31:05PM +0200, Christian Gmeiner wrote: > >> > >>> 2012/10/9 Kevin O'Connor <kevin(a)koconnor.net>: > >> > >>> > On Mon, Oct 08, 2012 at 02:14:03PM +0200, Christian Gmeiner wrote: > >> > >>> >> HI all > >> > >>> >> > >> > >>> >> I am running into some usb problems with coreboot & seabios: > >> > >>> > Can you set the debug level to 8 and post the whole log? Also, for > >> > >>> > timeout issues, having timestamps (via tools/readserial.py tool) > >> > >>> > sometimes helps. > > [...] > >> Kevin do you have an idea what could be wrong? > > > > I haven't had a chance to take a look at it. Something odd is going > > on, as it appears the transfer that's failing isn't even being > > started. I'll see if I can take a look this week. > > > > -Kevin > > He Kevin, > > I have made some success to get USB working - current SeaBios ehci > driver does not support toggling between > DATA0 and DATA1. Here is my current patch to get a little bit more running: The toggle bit should be updated automatically by the controller. It should not be necessary to do it manually. If this is impacting your results, something subtle must going on. -Kevin

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Re: [coreboot] Generic AMD E350 Support
by Graeme Russ 16 Oct '12

16 Oct '12

Hi Guys, On Tue, Oct 16, 2012 at 12:24 PM, Graeme Russ <graeme.russ(a)gmail.com> wrote: > Hi Guys, > > I have just purchased a AMD E350 based motherboard (an I35CT from > Qotom) The labelling on the motherboard includes "HEDY" and "T6941" A Google on HEDY ITX leads to http://en.hedy.com.cn/ - The logo font matches, so I appear to have narrowed down the origin of the motherboard but that has resulted in an otherwise dead-end Still, for less than AU$200 for the motherboard, case, power supply, 2GB RAM and 8GB SSD it's worth the trouble :) Regards, Graeme

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Re: [coreboot] Generic AMD E350 Support
by Graeme Russ 16 Oct '12

16 Oct '12

Hi David, On Wed, Oct 17, 2012 at 1:36 PM, David Hendricks <dhendrix(a)google.com> wrote: > On Tue, Oct 16, 2012 at 5:01 PM, Graeme Russ <graeme.russ(a)gmail.com> wrote: >> >> Hi Peter, >> >> On Wed, Oct 17, 2012 at 10:57 AM, Peter Stuge <peter(a)stuge.se> wrote: >> > Graeme Russ wrote: >> >> I've taken some hi-res photos using a DLSR with a macro lens. >> > >> > Where can I see them? Can upload at http://ge.tt/ or another favorite >> > image hoster. >> >> I'll hopefully upload them tonight (10 hours or so) > > > BTW -- try to peak under the southbridge heatsink if it's not too much of a > hassle. Will do. Regards, Graeme

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coreboot October 2012