coreboot October 2012

coreboot@coreboot.org

34 participants
312 discussions

Re: [coreboot] enable Fan Control for AMD Persimmon
by Rudolf Marek 15 Oct '12

15 Oct '12

Hi, You need to send correct commands to firmware. Plz check http://www.coreboot.org/AMD_IMC for a summary. Then I would say the interface did not change much, so looking into some agesa code will tell you how to program stuff there (there are files like imcEnv.c iirc) I need run now, plz ask if you want more info. Also, you will need to enable the IMC and load firmware. The agesa has some straps override for this. You just need to place the imc.bin in cbfs on right offset. Thanks Rudolf

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Patch merged into coreboot/master: dd52aa7 inteltool: remove bashism from Makefile
by gerrit＠coreboot.org 14 Oct '12

14 Oct '12

the following patch was just integrated into master: commit dd52aa7d313901269d9c5dfacad85022c3241168 Author: Stefan Tauner <stefan.tauner(a)gmx.at> Date: Sat Oct 13 02:33:35 2012 +0200 inteltool: remove bashism from Makefile &> is a bashism to redirect both outward streams (stdout and stderr), but with other shells this introduces a race condition with the rm command after it, because the compiler execution is done in the background/ in parallel. Found and tested with dash. Change-Id: I08516494828c9f7af168f954f2df027372657867 Signed-off-by: Stefan Tauner <stefan.tauner(a)gmx.at> Build-Tested: build bot (Jenkins) at Sun Oct 14 04:36:53 2012, giving +1 Reviewed-By: Peter Stuge <peter(a)stuge.se> at Sun Oct 14 22:22:59 2012, giving +2 See http://review.coreboot.org/1573 for details. -gerrit

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Re: [coreboot] [SeaBIOS] USB Problems geode lx800
by Christian Gmeiner 14 Oct '12

14 Oct '12

On 11 Oct 2012 16:42, "Christian Gmeiner" <christian.gmeiner(a)gmail.com> wrote: > > Christian Gmeiner, MSc > > > 2012/10/11 Christian Gmeiner <christian.gmeiner(a)gmail.com>: > > 2012/10/11 Kevin O'Connor <kevin(a)koconnor.net>: > >> On Tue, Oct 09, 2012 at 02:31:05PM +0200, Christian Gmeiner wrote: > >>> 2012/10/9 Kevin O'Connor <kevin(a)koconnor.net>: > >>> > On Mon, Oct 08, 2012 at 02:14:03PM +0200, Christian Gmeiner wrote: > >>> >> HI all > >>> >> > >>> >> I am running into some usb problems with coreboot & seabios: > >>> > Can you set the debug level to 8 and post the whole log? Also, for > >>> > timeout issues, having timestamps (via tools/readserial.py tool) > >>> > sometimes helps. > >>> > >>> Attached > >> > >> Hrmm, I guess you've disabled threads in your config? > >> > > yep... > > > > > >> From your log, I see: > >> > >> [14:23:00.5] ehci_send_bulk qh=0x000ef680 dir=0 data=0x00006d55 size=31^M > >> [14:23:00.5] ehci_send_bulk qh=0x000ef700 dir=128 data=0x00006e3c size=36^M > >> [14:23:00.5] ehci_send_bulk qh=0x000ef700 dir=128 data=0x00006d8f size=13^M > >> [14:23:05.5] WARNING - Timeout at ehci_wait_td:542!^M > >> [14:23:05.5] ehci pipe=0x000ef700 cur=00000000 tok=00000000 next=6b80 td=0x00006b80 > >> +status=d0d80^M > >> [14:23:05.5] USB transmission failed^M > >> [14:23:05.5] Unable to configure USB MSC drive.^M > >> > >> This looks like the transfer is stalling in the cdb_get_inquiry() call > >> as part of scsi_init_drive(). The drive is identified okay and at > >> least some transfers look okay, so it doesn't appear to be a > >> controller issue. > >> > >> I've been told some USB sticks are very picky about init order, but > >> I'm surprised to see that this is occuring for you on a variety of USB > >> sticks. > >> > >> It's possible to verify that a stall has occurred - print out > >> tds[i].token for all tds in ehci_send_bulk() on the error path. > >> > >> Does this device still have problems if you soft-reset after a failed > >> boot? > >> > > > > Here are the results with some more debug: > > > > Cold Reboot > > ------------ > > > > |0f7a5000| pmm_malloc zone=0x0f7afe87 handle=ffffffff size=192 > > align=40 ret=0x0f7a7bc0 (detail=0x0f7a7d70) > > |0f7a5000| ehci_control: td at phys(f7a7bc0): status: 80 : token 80e80 > > |0f7a5000| - cerr: 3, total_len: 0 > > |0f7a5000| ehci_control: td at phys(f7a7c00): status: 0 : token d00 > > |0f7a5000| - cerr: 3, total_len: 0 > > |0f7a5000| ehci_control: td at phys(f7a7c40): status: 0 : token 0 > > |0f7a5000| - cerr: 0, total_len: 0 > > |0f7a5000| pmm_free 0x0f7a7bc0 (detail=0x0f7a7d70) > > |0f7a5000| ehci_alloc_async_pipe 0x0f7a9090 2 > > |0f7a5000| pmm_malloc zone=0x0f7afe7f handle=ffffffff size=92 align=80 > > ret=0x000ef700 (detail=0x0f7a7d70) > > |0f7a5000| ehci_alloc_async_pipe 0x0f7a9090 2 > > |0f7a5000| pmm_malloc zone=0x0f7afe7f handle=ffffffff size=92 align=80 > > ret=0x000ef680 (detail=0x0f7a7d10) > > |0f7a5000| ehci_control 0x0f7a7cd0 (dir=128 cmd=8 data=1) > > |0f7a5000| pmm_malloc zone=0x0f7afe87 handle=ffffffff size=192 > > align=40 ret=0x0f7a7bc0 (detail=0x0f7a7ce0) > > |0f7a5000| ehci_control: td at phys(f7a7bc0): status: 80 : token 80e80 > > |0f7a5000| - cerr: 3, total_len: 0 > > |0f7a5000| ehci_control: td at phys(f7a7c00): status: 0 : token d00 > > |0f7a5000| - cerr: 3, total_len: 0 > > |0f7a5000| ehci_control: td at phys(f7a7c40): status: 0 : token 1c00 > > |0f7a5000| - cerr: 3, total_len: 0 > > |0f7a5000| pmm_free 0x0f7a7bc0 (detail=0x0f7a7ce0) > > |0f7a5000| pmm_malloc zone=0x0f7afe83 handle=ffffffff size=48 align=10 > > ret=0x000fdae0 (detail=0x0f7a7ce0) > > |0f7a5000| usb_cmd_data id=0x000fdae0 write=0 count=1 bs=36 buf=0x0f7a5f3c > > |0f7a5000| cbw to device > > |0f7a5000| ehci_send_bulk qh=0x000ef680 dir=0 data=0x0f7a5e65 size=31 > > |0f7a5000| before setup: td at phys(f7a5c80): status: 0 : token 0 > > |0f7a5000| - cerr: 0, total_len: 0 > > |0f7a5000| ehci_send_bulk: td at phys(f7a5c80): status: 80 : token c80 > > |0f7a5000| - cerr: 3, total_len: 0 > > |0f7a5000| Data-In from the device to the host - 36 bytes > > |0f7a5000| ehci_send_bulk qh=0x000ef700 dir=128 data=0x0f7a5f3c size=36 > > |0f7a5000| before setup: td at phys(f7a5c80): status: 0 : token 0 > > |0f7a5000| - cerr: 0, total_len: 0 > > |0f7a5000| ehci_send_bulk: td at phys(f7a5c80): status: 80 : token d80 > > |0f7a5000| - cerr: 3, total_len: 0 > > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token d80 > > |0f7a5000| - cerr: 3, total_len: 0 > > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token d80 > > |0f7a5000| - cerr: 3, total_len: 0 > > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token d80 > > |0f7a5000| - cerr: 3, total_len: 0 > > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token d80 > > |0f7a5000| - cerr: 3, total_len: 0 > > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token d80 > > |0f7a5000| - cerr: 3, total_len: 0 > > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token d80 > > |0f7a5000| - cerr: 3, total_len: 0 > > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token d80 > > |0f7a5000| - cerr: 3, total_len: 0 > > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token d80 > > |0f7a5000| - cerr: 3, total_len: 0 > > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token d80 > > |0f7a5000| - cerr: 3, total_len: 0 > > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token d80 > > |0f7a5000| - cerr: 3, total_len: 0 > > > > > > Warm Reboot > > ----------- > > > > 0f7a5000| pmm_free 0x0f7a7bc0 (detail=0x0f7a7d70) > > |0f7a5000| ehci_alloc_async_pipe 0x0f7a9090 2 > > |0f7a5000| pmm_malloc zone=0x0f7afe7f handle=ffffffff size=92 align=80 > > ret=0x000ef700 (detail=0x0f7a7d70) > > |0f7a5000| ehci_alloc_async_pipe 0x0f7a9090 2 > > |0f7a5000| pmm_malloc zone=0x0f7afe7f handle=ffffffff size=92 align=80 > > ret=0x000ef680 (detail=0x0f7a7d10) > > |0f7a5000| ehci_control 0x0f7a7cd0 (dir=128 cmd=8 data=1) > > |0f7a5000| pmm_malloc zone=0x0f7afe87 handle=ffffffff size=192 > > align=40 ret=0x0f7a7bc0 (detail=0x0f7a7ce0) > > |0f7a5000| ehci_control: td at phys(f7a7bc0): status: 80 : token 80e80 > > |0f7a5000| - cerr: 3, total_len: 0 > > |0f7a5000| ehci_control: td at phys(f7a7c00): status: 0 : token d00 > > |0f7a5000| - cerr: 3, total_len: 0 > > |0f7a5000| ehci_control: td at phys(f7a7c40): status: 0 : token 1c00 > > |0f7a5000| - cerr: 3, total_len: 0 > > |0f7a5000| pmm_free 0x0f7a7bc0 (detail=0x0f7a7ce0) > > |0f7a5000| pmm_malloc zone=0x0f7afe83 handle=ffffffff size=48 align=10 > > ret=0x000fdae0 (detail=0x0f7a7ce0) > > |0f7a5000| usb_cmd_data id=0x000fdae0 write=0 count=1 bs=36 buf=0x0f7a5f3c > > |0f7a5000| cbw to device > > |0f7a5000| ehci_send_bulk qh=0x000ef680 dir=0 data=0x0f7a5e65 size=31 > > |0f7a5000| before setup: td at phys(f7a5c80): status: 0 : token 0 > > |0f7a5000| - cerr: 0, total_len: 0 > > |0f7a5000| ehci_send_bulk: td at phys(f7a5c80): status: 80 : token c80 > > |0f7a5000| - cerr: 3, total_len: 0 > > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token c80 > > |0f7a5000| - cerr: 3, total_len: 0 > > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token c80 > > |0f7a5000| - cerr: 3, total_len: 0 > > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token c80 > > |0f7a5000| - cerr: 3, total_len: 0 > > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token c80 > > |0f7a5000| - cerr: 3, total_len: 0 > > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token c80 > > |0f7a5000| - cerr: 3, total_len: 0 > > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token c80 > > |0f7a5000| - cerr: 3, total_len: 0 > > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token c80 > > |0f7a5000| - cerr: 3, total_len: 0 > > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token c80 > > |0f7a5000| - cerr: 3, total_len: 0 > > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token c80 > > |0f7a5000| - cerr: 3, total_len: 0 > > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token c80 > > |0f7a5000| - cerr: 3, total_len: 0 > > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token c80 > > |0f7a5000| - cerr: 3, total_len: 0 > > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token c80 > > |0f7a5000| - cerr: 3, total_len: 0 > > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token c80 > > |0f7a5000| - cerr: 3, total_len: 0 > > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token c80 > > |0f7a5000| - cerr: 3, total_len: 0 > > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token c80 > > |0f7a5000| - cerr: 3, total_len: 0 > > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token c80 > > |0f7a5000| - cerr: 3, total_len: 0 > > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token c80 > > |0f7a5000| - cerr: 3, total_len: 0 > > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token c80 > > |0f7a5000| - cerr: 3, total_len: 0 > > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token c80 > > |0f7a5000| - cerr: 3, total_len: 0 > > |0f7a5000| ehci_wait_td: td at phys(f7a5c80): status: 80 : token c80 > > |0f7a5000| - cerr: 3, total_len: 0 > > > > > > This is the used patch: > > > > diff --git a/src/usb-ehci.c b/src/usb-ehci.c > > index 2676615..92a9c60 100644 > > --- a/src/usb-ehci.c > > +++ b/src/usb-ehci.c > > @@ -178,6 +178,14 @@ check_ehci_ports(struct usb_ehci_s *cntl) > > * Setup > > ****************************************************************/ > > > > +static void dump_td(struct ehci_qtd *td, const char *func) > > +{ > > + u32 addr = (u32)td; > > + dprintf(1, "%s: td at phys(%x): status: %x : token %x\n", func, > > addr, td->token & QTD_STS_MASK, td->token); > > + dprintf(1, "- cerr: %x, total_len: %x\n", (td->token & > > QTD_CERR_MASK) >> QTD_CERR_SHIFT, > > + (td->token & QTD_LENGTH_MASK) >> QTD_LENGTH_SHIFT); > > +} > > + > > // Wait for next USB async frame to start - for ensuring safe memory release. > > static void > > ehci_waittick(struct usb_ehci_s *cntl) > > @@ -535,6 +543,9 @@ ehci_wait_td(struct ehci_pipe *pipe, struct > > ehci_qtd *td, int timeout) > > status = td->token; > > if (!(status & QTD_STS_ACTIVE)) > > break; > > + > > + dump_td(td, __func__); > > + > > if (check_tsc(end)) { > > u32 cur = GET_LOWFLAT(pipe->qh.current); > > u32 tok = GET_LOWFLAT(pipe->qh.token); > > @@ -633,6 +644,7 @@ ehci_control(struct usb_pipe *p, int dir, const > > void *cmd, int cmdsize > > int i, ret=0; > > for (i=0; i<3; i++) { > > struct ehci_qtd *td = &tds[i]; > > + dump_td(td, __func__); > > ret = ehci_wait_td(pipe, td, 500); > > if (ret) > > break; > > @@ -665,18 +677,25 @@ ehci_send_bulk(struct usb_pipe *p, int dir, void > > *data, int datasize) > > struct ehci_qtd *td = &tds[tdpos++ % STACKQTDS]; > > int ret = ehci_wait_td(pipe, td, 5000); > > if (ret) > > + { > > + dump_td(td, "ehci_send_bulk ERROR2"); > > return -1; > > + } > > > > struct ehci_qtd *nexttd_fl = MAKE_FLATPTR(GET_SEG(SS) > > , &tds[tdpos % STACKQTDS]); > > > > + dump_td(td, "before setup"); > > + > > int transfer = fillTDbuffer(td, maxpacket, data, datasize); > > td->qtd_next = (transfer==datasize ? EHCI_PTR_TERM : (u32)nexttd_fl); > > td->alt_next = EHCI_PTR_TERM; > > barrier(); > > - td->token = (ehci_explen(transfer) | QTD_STS_ACTIVE > > + td->token = (/*ehci_explen(transfer) | */QTD_STS_ACTIVE > > | (dir ? QTD_PID_IN : QTD_PID_OUT) | ehci_maxerr(3)); > > > > + dump_td(td, __func__); > > + > > data += transfer; > > datasize -= transfer; > > } > > @@ -685,7 +704,10 @@ ehci_send_bulk(struct usb_pipe *p, int dir, void > > *data, int datasize) > > struct ehci_qtd *td = &tds[tdpos++ % STACKQTDS]; > > int ret = ehci_wait_td(pipe, td, 5000); > > if (ret) > > + { > > + dump_td(td, "ehci_send_bulk ERROR2"); > > return -1; > > + } > > } > > > > return 0; > > > > > > > > greets > > > Here is the log of filo using libpayload > > [16:40:24.5] FILO version 0.6.0 (christian@chgm-pc) Thu Oct 11 > 16:12:26 CEST 2012 > [16:40:24.5] 00:0f.5 2095:1022.5 EHCI controller > [16:40:24.7] highspeed device > [16:40:24.7] wait_for_tds: td at phys(1f6b2260): status: 0 token: 80000e00 > > [16:40:24.8] - cerr: 3, total_len: 0 > > [16:40:24.8] wait_for_tds done: td at phys(1f6b2260): status: 0 token: 80000e00 > > [16:40:24.8] - cerr: 3, total_len: 0 > > > [16:40:24.8] moving from 148260 to 1482a0 > [16:40:24.8] wait_for_tds: td at phys(1f6b22a0): status: 0 token: 100 > > [16:40:24.8] - cerr: 0, total_len: 0 > > [16:40:24.8] wait_for_tds: td at phys(1f6b2260): status: 0 token: 80000e00 > > [16:40:24.8] - cerr: 3, total_len: 0 > > [16:40:24.8] wait_for_tds done: td at phys(1f6b2260): status: 0 token: 80000e00 > > [16:40:24.9] - cerr: 3, total_len: 0 > > > [16:40:24.9] moving from 148260 to 1482a0 > [16:40:24.9] wait_for_tds: td at phys(1f6b22a0): status: 0 token: d00 > > [16:40:25.0] - cerr: 3, total_len: 0 > > [16:40:25.0] wait_for_tds done: td at phys(1f6b22a0): status: 0 token: d00 > > [16:40:25.0] - cerr: 3, total_len: 0 > > > [16:40:25.1] moving from 1482a0 to 1482e0 > [16:40:25.1] wait_for_tds: td at phys(1f6b22e0): status: 0 token: 1000 > > [16:40:25.2] - cerr: 0, total_len: 0 > > [16:40:25.2] maxPacketSize0: 40 > [16:40:25.2] wait_for_tds: td at phys(1f6b2260): status: 0 token: 80000e00 > > [16:40:25.2] - cerr: 3, total_len: 0 > > [16:40:25.3] wait_for_tds done: td at phys(1f6b2260): status: 0 token: 80000e00 > > [16:40:25.3] - cerr: 3, total_len: 0 > > > [16:40:25.4] moving from 148260 to 1482a0 > [16:40:25.4] wait_for_tds: td at phys(1f6b22a0): status: 0 token: d00 > > [16:40:25.5] - cerr: 3, total_len: 0 > > [16:40:25.5] wait_for_tds done: td at phys(1f6b22a0): status: 0 token: d00 > > [16:40:25.5] - cerr: 3, total_len: 0 > > > [16:40:25.6] moving from 1482a0 to 1482e0 > [16:40:25.6] wait_for_tds: td at phys(1f6b22e0): status: 0 token: 1000 > > [16:40:25.7] - cerr: 0, total_len: 0 > > [16:40:25.7] * found device (0x1370:0x3252, USB 2.0) > [16:40:25.7] device has 1 configurations > [16:40:25.7] wait_for_tds: td at phys(1f6b2260): status: 0 token: 80000e00 > > [16:40:25.8] - cerr: 3, total_len: 0 > > [16:40:25.8] wait_for_tds done: td at phys(1f6b2260): status: 0 token: 80000e00 > > [16:40:25.9] - cerr: 3, total_len: 0 > > > [16:40:25.9] moving from 148260 to 1482a0 > [16:40:26.0] wait_for_tds: td at phys(1f6b22a0): status: 0 token: d00 > > [16:40:26.0] - cerr: 3, total_len: 0 > > [16:40:26.0] wait_for_tds done: td at phys(1f6b22a0): status: 0 token: d00 > > [16:40:26.1] - cerr: 3, total_len: 0 > > > [16:40:26.1] moving from 1482a0 to 1482e0 > [16:40:26.1] wait_for_tds: td at phys(1f6b22e0): status: 0 token: 1000 > > [16:40:26.2] - cerr: 0, total_len: 0 > > [16:40:26.2] wait_for_tds: td at phys(1f6b2260): status: 0 token: 80000e00 > > [16:40:26.3] - cerr: 3, total_len: 0 > > [16:40:26.3] wait_for_tds done: td at phys(1f6b2260): status: 0 token: 80000e00 > > [16:40:26.4] - cerr: 3, total_len: 0 > > > [16:40:26.4] moving from 148260 to 1482a0 > [16:40:26.4] wait_for_tds: td at phys(1f6b22a0): status: 0 token: d00 > > [16:40:26.5] - cerr: 3, total_len: 0 > > [16:40:26.5] wait_for_tds done: td at phys(1f6b22a0): status: 0 token: d00 > > [16:40:26.6] - cerr: 3, total_len: 0 > > > [16:40:26.6] moving from 1482a0 to 1482e0 > [16:40:26.7] wait_for_tds: td at phys(1f6b22e0): status: 0 token: 1000 > > [16:40:26.7] - cerr: 0, total_len: 0 > > [16:40:26.7] wait_for_tds: td at phys(1f6b2260): status: 0 token: 80000e00 > > [16:40:26.8] - cerr: 3, total_len: 0 > > [16:40:26.8] wait_for_tds done: td at phys(1f6b2260): status: 0 token: 80000e00 > > [16:40:26.8] - cerr: 3, total_len: 0 > > > [16:40:26.9] moving from 148260 to 1482a0 > [16:40:26.9] wait_for_tds: td at phys(1f6b22a0): status: 0 token: 100 > > [16:40:27.0] - cerr: 0, total_len: 0 > > [16:40:27.0] device has 1 interfaces > [16:40:27.0] #0 has 2 endpoints, interface 8:6, protocol 50 > [16:40:27.0] #1: Endpoint 1 (in), max packet size 200, type bulk > [16:40:27.1] #2: Endpoint 2 (out), max packet size 200, type bulk > [16:40:27.1] , class: MSC > [16:40:27.1] Waiting for device to become ready...ehci_bulk: setup: > td at phys(148260): status: 0 token: 0 > > [16:40:27.2] - cerr: 0, total_len: 0 > > [16:40:27.2] wait_for_tds: td at phys(1f6b2260): status: 1 token: 80000001 > > [16:40:27.3] - cerr: 0, total_len: 0 > > [16:40:27.3] ehci_bulk: setup: td at phys(148260): status: 0 token: 0 > > [16:40:27.3] - cerr: 0, total_len: 0 > > [16:40:27.4] wait_for_tds: td at phys(1f6b2260): status: 0 token: 80000100 > > [16:40:27.4] - cerr: 0, total_len: 0 > > [16:40:27.5] ehci_bulk: setup: td at phys(148260): status: 0 token: 0 > > [16:40:27.5] - cerr: 0, total_len: 0 > > [16:40:27.5] wait_for_tds: td at phys(1f6b2260): status: 1 token: 1 > > [16:40:27.6] - cerr: 0, total_len: 0 > > [16:40:27.6] ehci_bulk: setup: td at phys(148260): status: 0 token: 0 > > [16:40:27.7] - cerr: 0, total_len: 0 > > [16:40:27.7] wait_for_tds: td at phys(1f6b2260): status: 0 token: 100 > > [16:40:27.7] - cerr: 0, total_len: 0 > > [16:40:27.8] ehci_bulk: setup: td at phys(148260): status: 0 token: 0 > > [16:40:27.8] - cerr: 0, total_len: 0 > > [16:40:27.9] wait_for_tds: td at phys(1f6b2260): status: 0 token: 80000100 > > [16:40:27.9] - cerr: 0, total_len: 0 > > [16:40:28.1] ehci_bulk: setup: td at phys(148260): status: 0 token: 0 > > [16:40:28.1] - cerr: 0, total_len: 0 > > [16:40:28.2] wait_for_tds: td at phys(1f6b2260): status: 1 token: 80000001 > > [16:40:28.2] - cerr: 0, total_len: 0 > > [16:40:28.2] ehci_bulk: setup: td at phys(148260): status: 0 token: 0 > > [16:40:28.3] - cerr: 0, total_len: 0 > > [16:40:28.3] wait_for_tds: td at phys(1f6b2260): status: 0 token: 100 > > [16:40:28.3] - cerr: 0, total_len: 0 > > [16:40:28.4] ok. > [16:40:28.4] ehci_bulk: setup: td at phys(148260): status: 0 token: 0 > > [16:40:28.4] - cerr: 0, total_len: 0 > > [16:40:28.5] wait_for_tds: td at phys(1f6b2260): status: 1 token: 1 > > [16:40:28.5] - cerr: 0, total_len: 0 > > [16:40:28.6] ehci_bulk: setup: td at phys(148260): status: 0 token: 0 > > [16:40:28.6] - cerr: 0, total_len: 0 > > [16:40:28.6] wait_for_tds: td at phys(1f6b2260): status: 0 token: 80000100 > > [16:40:28.7] - cerr: 0, total_len: 0 > > [16:40:28.7] ehci_bulk: setup: td at phys(148260): status: 0 token: 0 > > [16:40:28.8] - cerr: 0, total_len: 0 > > [16:40:28.8] wait_for_tds: td at phys(1f6b2260): status: 1 token: 80000001 > > [16:40:28.9] - cerr: 0, total_len: 0 > > [16:40:28.9] ehci_bulk: setup: td at phys(148260): status: 0 token: 0 > > [16:40:28.9] - cerr: 0, total_len: 0 > > [16:40:29.0] wait_for_tds: td at phys(1f6b2260): status: 0 token: 100 > > [16:40:29.0] - cerr: 0, total_len: 0 > > [16:40:29.1] ehci_bulk: setup: td at phys(148260): status: 0 token: 0 > > [16:40:29.1] - cerr: 0, total_len: 0 > > [16:40:29.2] wait_for_tds: td at phys(1f6b2260): status: 0 token: 80000100 > > [16:40:29.2] - cerr: 0, total_len: 0 > > [16:40:29.2] 15663104 512-byte sectors (8019 MB) > [16:40:29.3] 00:0f.4 2094:1022.4 OHCI controller > [16:40:29.3] OHCI Version 1.0 > [16:40:29.4] ERROR: No such CMOS option (boot_devices) > [16:40:29.4] menu: hda3:/boot/filo/menu.lst > Kevin do you have an idea what could be wrong? --- Christian Gmeiner, MSc

1 0

Patch merged into coreboot/master: 1518063 crossgcc: Allow the non-gnu tar and patch work on XxxBSD
by gerrit＠coreboot.org 14 Oct '12

14 Oct '12

the following patch was just integrated into master: commit 1518063a5f96afeed1ae19b93011c37e13b2ce44 Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Fri Sep 28 16:18:58 2012 +0800 crossgcc: Allow the non-gnu tar and patch work on XxxBSD For BSD, patch and tar are not default GNU. Add a work around to let the non-gun patch and tar work. Change-Id: I0a9d0bb0e535aa5e0dde146db330c3c8d7b4d8cb Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Build-Tested: build bot (Jenkins) at Fri Sep 28 09:46:04 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Sun Oct 14 20:15:45 2012, giving +2 See http://review.coreboot.org/1502 for details. -gerrit

1 0

Patch merged into coreboot/master: b68f2bc libpayload: CMOS access was implemented in a backward way
by gerrit＠coreboot.org 14 Oct '12

14 Oct '12

the following patch was just integrated into master: commit b68f2bc158d91dbc60305c3d9375dff53a7ff4f4 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Mon Sep 24 20:47:03 2012 +0200 libpayload: CMOS access was implemented in a backward way Instead of having the highlevel functions make use of the lowlevel functions, it implemented the lowlevel stuff in terms of highlevel. Change-Id: I530bfe3cbc6f57a6294d86fbf1739e06467a2318 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Build-Tested: build bot (Jenkins) at Sun Oct 7 16:34:07 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Sun Oct 14 20:12:11 2012, giving +2 See http://review.coreboot.org/1539 for details. -gerrit

1 0

Patch merged into coreboot/master: 6e7892a abuild: allow building with no payload
by gerrit＠coreboot.org 14 Oct '12

14 Oct '12

the following patch was just integrated into master: commit 6e7892abf007fd9981449b9ec2f0f5980eab1850 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sun Oct 7 15:05:42 2012 +0200 abuild: allow building with no payload Change-Id: I167f0bb57bb40f0426182c0abe868bdad58eb120 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Build-Tested: build bot (Jenkins) at Sun Oct 7 15:37:26 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Sun Oct 14 20:10:14 2012, giving +2 See http://review.coreboot.org/1563 for details. -gerrit

1 0

enable Fan Control for AMD Persimmon
by Wolfgang Kamp - datakamp 14 Oct '12

14 Oct '12

Does anyone have an idea what steps are necessary to enable the Fan control for the AMD Persimmon board? It seem we have to enable the CIMx integrated Microcontroller (IMC) in the Southbridge, but how does it work?. Wolfgang

1 0

#188: gcc-4.7 miscompiles coreboot on -Os, -O1, -O2, -O3 in 3 different ways
by coreboot 14 Oct '12

14 Oct '12

#188: gcc-4.7 miscompiles coreboot on -Os, -O1,-O2,-O3 in 3 different ways -----------------------------+---------------------------------- Reporter: mustrumr97@… | Owner: stepan@… Type: defect | Status: new Priority: major | Milestone: Component: coreboot | Keywords: Dependencies: | Patch Status: there is no patch -----------------------------+---------------------------------- Coreboot 1b97bdc42a91746906b99a37ad15ba0a0039e4a3 Has been doing the same for at least 3 months On -O1: After printing {{{ Adjust low_table_end from 0x00000528 to 0x00001000 Adjust rom_table_end from 0x07fe0400 to 0x07ff0000 Adding high table area coreboot memory table: }}} {{{ #0 unpack_lb64 (value=...) at src/include/boot/coreboot_tables.h:54 #1 lb_dump_memory_ranges (mem=0x7fe0418) at src/arch/x86/boot/coreboot_table.c:523 #2 write_coreboot_table (low_table_start=low_table_start@entry=0, low_table_end=<optimized out>, low_table_end@entry=1280, rom_table_start=134086656, rom_table_end=<optimized out>, rom_table_end@entry=134087680) at src/arch/x86/boot/coreboot_table.c:669 #3 0x00109004 in write_tables () at src/arch/x86/boot/tables.c:214 #4 0x00100999 in hardwaremain (boot_complete=0) at src/boot/hardwaremain.c:146 #5 0x0010009c in _text () at src/arch/x86/lib/c_start.S:89 }}} On -O2 and -Os After printing {{{ Adjust low_table_end from 0x00000528 to 0x00001000 Adjust rom_table_end from 0x07fe0400 to 0x07ff0000 }}} same stack trace On -O3 qemu resets after prining {{{ coreboot-4.0-2820-g1b97bdc-dirty Sun Oct 14 15:07:41 EEST 2012 starting... Loading image. CBFS: Looking for 'fallback/coreboot_ram' CBFS: found. CBFS: loading stage fallback/coreboot_ram @ 0x100000 (180224 bytes), entry @ 0x100000 }}} -- Ticket URL: <https://tracker.coreboot.org/trac/coreboot/ticket/188> coreboot <http://www.coreboot.org/>

2 1

New patch to review for coreboot: f87b008 Add support for socket LGA775
by Stefan Tauner 14 Oct '12

14 Oct '12

Stefan Tauner (stefan.tauner(a)gmx.at) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1581 -gerrit commit f87b0084fb4ffad4cafb9df88a2e65e291b8e556 Author: Stefan Tauner <stefan.tauner(a)gmx.at> Date: Sat Oct 13 13:15:04 2012 +0200 Add support for socket LGA775 Change-Id: Ia7ef3a4cbc3638a9c9a48b297e392e4e655b6e6b Signed-off-by: Stefan Tauner <stefan.tauner(a)gmx.at> --- src/cpu/intel/Kconfig | 1 + src/cpu/intel/Makefile.inc | 1 + src/cpu/intel/socket_LGA775/Kconfig | 28 ++++++++++++++++++++++++++++ src/cpu/intel/socket_LGA775/Makefile.inc | 17 +++++++++++++++++ src/cpu/intel/socket_LGA775/socket_LGA775.c | 5 +++++ 5 files changed, 52 insertions(+) diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig index c6dab12..c3cf4c9 100644 --- a/src/cpu/intel/Kconfig +++ b/src/cpu/intel/Kconfig @@ -30,4 +30,5 @@ source src/cpu/intel/socket_mPGA604/Kconfig source src/cpu/intel/socket_PGA370/Kconfig source src/cpu/intel/socket_441/Kconfig source src/cpu/intel/socket_LGA771/Kconfig +source src/cpu/intel/socket_LGA775/Kconfig source src/cpu/intel/socket_rPGA989/Kconfig diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc index 9e498f1..782c15a 100644 --- a/src/cpu/intel/Makefile.inc +++ b/src/cpu/intel/Makefile.inc @@ -20,6 +20,7 @@ subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += model_206ax subdirs-$(CONFIG_CPU_INTEL_SLOT_2) += slot_2 subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1 subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA771) += socket_LGA771 +subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA775) += socket_LGA775 #socket_mPGA604_533Mhz #socket_mPGA604_800Mhz diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig new file mode 100644 index 0000000..dfb3181 --- /dev/null +++ b/src/cpu/intel/socket_LGA775/Kconfig @@ -0,0 +1,28 @@ +config CPU_INTEL_SOCKET_LGA775 + bool + +if CPU_INTEL_SOCKET_LGA775 + +config SOCKET_SPECIFIC_OPTIONS # dummy + def_bool y + select CPU_INTEL_MODEL_6EX + select CPU_INTEL_MODEL_6FX + select CPU_INTEL_MODEL_F3X + select CPU_INTEL_MODEL_F4X +# select CPU_INTEL_MODEL_F6X +# select CPU_INTEL_MODEL_1066X + select CPU_INTEL_MODEL_1067X + select MMX + select SSE + select UDELAY_TSC + select SIPI_VECTOR_IN_ROM + +config DCACHE_RAM_SIZE + hex + default 0x4000 # 16 kB + +config DCACHE_RAM_BASE + hex + default 0xfeffc000 # 4GB - 16MB - DCACHE_RAM_SIZE + +endif # CPU_INTEL_SOCKET_LGA775 diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc new file mode 100644 index 0000000..100b4d8 --- /dev/null +++ b/src/cpu/intel/socket_LGA775/Makefile.inc @@ -0,0 +1,17 @@ +ramstage-y += socket_LGA775.c +subdirs-y += ../model_6ex +subdirs-y += ../model_6fx +subdirs-y += ../model_f3x +subdirs-y += ../model_f4x +#subdirs-y += ../model_f6x +#subdirs-y += ../model_1066x +subdirs-y += ../model_1067x +subdirs-y += ../../x86/tsc +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/smm +subdirs-y += ../microcode +subdirs-y += ../hyperthreading + +cpu_incs-$(CONFIG_CACHE_AS_RAM) += $(src)/cpu/intel/car/cache_as_ram_ht.inc diff --git a/src/cpu/intel/socket_LGA775/socket_LGA775.c b/src/cpu/intel/socket_LGA775/socket_LGA775.c new file mode 100644 index 0000000..7ec4e5e --- /dev/null +++ b/src/cpu/intel/socket_LGA775/socket_LGA775.c @@ -0,0 +1,5 @@ +#include <device/device.h> + +struct chip_operations cpu_intel_socket_LGA775_ops = { + CHIP_NAME("Socket LGA775 CPU") +};

1 0

Patch set updated for coreboot: dd52aa7 inteltool: remove bashism from Makefile
by Stefan Tauner 14 Oct '12

14 Oct '12

Stefan Tauner (stefan.tauner(a)gmx.at) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1573 -gerrit commit dd52aa7d313901269d9c5dfacad85022c3241168 Author: Stefan Tauner <stefan.tauner(a)gmx.at> Date: Sat Oct 13 02:33:35 2012 +0200 inteltool: remove bashism from Makefile &> is a bashism to redirect both outward streams (stdout and stderr), but with other shells this introduces a race condition with the rm command after it, because the compiler execution is done in the background/ in parallel. Found and tested with dash. Change-Id: I08516494828c9f7af168f954f2df027372657867 Signed-off-by: Stefan Tauner <stefan.tauner(a)gmx.at> --- util/inteltool/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/inteltool/Makefile b/util/inteltool/Makefile index d754005..af79b1e 100644 --- a/util/inteltool/Makefile +++ b/util/inteltool/Makefile @@ -59,7 +59,7 @@ pciutils: printf "struct pci_access *pacc;\n"; \ printf "int main(int argc, char **argv)\n"; \ printf "{ pacc = pci_alloc(); return 0; }\n"; ) > .test.c ) - @$(CC) $(CFLAGS) .test.c -o .test $(LDFLAGS) &>/dev/null && \ + @$(CC) $(CFLAGS) .test.c -o .test $(LDFLAGS) >/dev/null 2>&1 && \ printf "found.\n" || ( printf "not found.\n\n"; \ printf "Please install pciutils-devel and zlib-devel.\n"; \ printf "See README for more information.\n\n"; \

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coreboot October 2012