coreboot October 2012

coreboot@coreboot.org

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312 discussions

Patch set updated for coreboot: b55f300 inteltool: improve the libpci test in the Makefile
by Stefan Tauner 14 Oct '12

14 Oct '12

Stefan Tauner (stefan.tauner(a)gmx.at) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1575 -gerrit commit b55f300c915f099161a9686d9bcd820940b93010 Author: Stefan Tauner <stefan.tauner(a)gmx.at> Date: Fri Oct 12 10:36:49 2012 +0200 inteltool: improve the libpci test in the Makefile Use the verbatim variable method to define and export test code and the actual libpci test from flashrom. This improves readability and will work with stricter compiler (settings). Change-Id: Iace7d53b0b992c4fde596ce1d606ad715d6dfc2a Signed-off-by: Stefan Tauner <stefan.tauner(a)gmx.at> --- util/inteltool/Makefile | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/util/inteltool/Makefile b/util/inteltool/Makefile index af79b1e..6c94460 100644 --- a/util/inteltool/Makefile +++ b/util/inteltool/Makefile @@ -53,12 +53,24 @@ distclean: clean dep: @$(CC) $(CFLAGS) -MM *.c > .dependencies +define LIBPCI_TEST +/* Avoid a failing test due to libpci header symbol shadowing breakage */ +#define index shadow_workaround_index +#include <pci/pci.h> +struct pci_access *pacc; +int main(int argc, char **argv) +{ + (void) argc; + (void) argv; + pacc = pci_alloc(); + return 0; +} +endef +export LIBPCI_TEST + pciutils: @printf "\nChecking for pciutils and zlib... " - @$(shell ( printf "#include <pci/pci.h>\n"; \ - printf "struct pci_access *pacc;\n"; \ - printf "int main(int argc, char **argv)\n"; \ - printf "{ pacc = pci_alloc(); return 0; }\n"; ) > .test.c ) + @echo "$$LIBPCI_TEST" > .test.c @$(CC) $(CFLAGS) .test.c -o .test $(LDFLAGS) >/dev/null 2>&1 && \ printf "found.\n" || ( printf "not found.\n\n"; \ printf "Please install pciutils-devel and zlib-devel.\n"; \

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New patch to review for coreboot: 40fec90 inteltool: add support for 946GZ and 946PL
by Stefan Tauner 13 Oct '12

13 Oct '12

Stefan Tauner (stefan.tauner(a)gmx.at) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1576 -gerrit commit 40fec9087f4116f0a136ec4f79f5bf2345e300fa Author: Stefan Tauner <stefan.tauner(a)gmx.at> Date: Sat Oct 13 06:23:52 2012 +0200 inteltool: add support for 946GZ and 946PL Change-Id: Ied0ff16c16d8c2f04b55fe6b0a6ee38966d3c424 Signed-off-by: Stefan Tauner <stefan.tauner(a)gmx.at> --- util/inteltool/inteltool.c | 1 + util/inteltool/inteltool.h | 1 + util/inteltool/memory.c | 1 + util/inteltool/pcie.c | 3 +++ 4 files changed, 6 insertions(+) diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 2d99863..be2b721 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -54,6 +54,7 @@ static const struct { { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945P, "945P" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GM, "945GM" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GSE, "945GSE" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82946, "946GZ/PL" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82965PM, "965PM" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q965, "Q963/82Q965" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82975X, "975X" }, diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 7ef2d8d..00adc68 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -72,6 +72,7 @@ #define PCI_DEVICE_ID_INTEL_82945P 0x2770 #define PCI_DEVICE_ID_INTEL_82945GM 0x27a0 #define PCI_DEVICE_ID_INTEL_82945GSE 0x27ac +#define PCI_DEVICE_ID_INTEL_82946 0x2970 #define PCI_DEVICE_ID_INTEL_82965PM 0x2a00 #define PCI_DEVICE_ID_INTEL_82Q965 0x2990 #define PCI_DEVICE_ID_INTEL_82975X 0x277c diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c index 62d7217..72a2de4 100644 --- a/util/inteltool/memory.c +++ b/util/inteltool/memory.c @@ -118,6 +118,7 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc) mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe; mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; break; + case PCI_DEVICE_ID_INTEL_82946: case PCI_DEVICE_ID_INTEL_82Q965: case PCI_DEVICE_ID_INTEL_ATOM_DXXX: case PCI_DEVICE_ID_INTEL_ATOM_NXXX: diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c index e454f44..752d7b0 100644 --- a/util/inteltool/pcie.c +++ b/util/inteltool/pcie.c @@ -91,6 +91,7 @@ int print_epbar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_82945GM: case PCI_DEVICE_ID_INTEL_82945GSE: case PCI_DEVICE_ID_INTEL_82945P: + case PCI_DEVICE_ID_INTEL_82946: case PCI_DEVICE_ID_INTEL_82975X: epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; break; @@ -156,6 +157,7 @@ int print_dmibar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_82975X: dmibar_phys = pci_read_long(nb, 0x4c) & 0xfffffffe; break; + case PCI_DEVICE_ID_INTEL_82946: case PCI_DEVICE_ID_INTEL_82965PM: case PCI_DEVICE_ID_INTEL_82Q965: case PCI_DEVICE_ID_INTEL_82Q35: @@ -260,6 +262,7 @@ int print_pciexbar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_82975X: pciexbar_reg = pci_read_long(nb, 0x48); break; + case PCI_DEVICE_ID_INTEL_82946: case PCI_DEVICE_ID_INTEL_82965PM: case PCI_DEVICE_ID_INTEL_82Q965: case PCI_DEVICE_ID_INTEL_82Q35:

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Patch set updated for coreboot: 0c12d0c Update .gitignore
by Stefan Tauner 13 Oct '12

13 Oct '12

Stefan Tauner (stefan.tauner(a)gmx.at) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1572 -gerrit commit 0c12d0c4c57e0c555931c416e47eff3e75ede25f Author: Stefan Tauner <stefan.tauner(a)gmx.at> Date: Sat Oct 13 02:45:13 2012 +0200 Update .gitignore Add... - generated documentation files - all kinds of stuff in the util subdirectories Change-Id: I47ab6d239aae725f54413f03424f40002ac5a275 Signed-off-by: Stefan Tauner <stefan.tauner(a)gmx.at> --- .gitignore | 27 +++++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/.gitignore b/.gitignore index ea10be7..15d1c17 100644 --- a/.gitignore +++ b/.gitignore @@ -44,15 +44,38 @@ util/crossgcc/w32api-*/ # Ignore Kdevelop project file .kdev4 +util/*/.dependencies +util/*/.test +util/cbfstool/cbfstool +util/dumpmmcr/dumpmmcr util/ectool/ectool +util/getpir/getpir +util/ifdtool/ifdtool util/inteltool/.dependencies util/inteltool/inteltool +util/k8resdump/k8resdump +util/lbtdump/lbtdump +util/mptable/mptable util/msrtool/Makefile util/msrtool/Makefile.deps util/msrtool/msrtool +util/nrv2b/nrv2b util/nvramtool/.dependencies util/nvramtool/nvramtool -util/superiotool/superiotool +util/optionlist/Options.wiki util/romcc/romcc -util/romcc/tests/*.S-O2-mmmx util/romcc/tests/fail_test*.S +util/romcc/tests/*.S-O2-mmmx +util/superiotool/superiotool +util/vgabios/testbios + +documentation/*.aux +documentation/*.idx +documentation/*.log +documentation/*.toc +documentation/*.out +documentation/*.pdf +documentation/mainboardkconfig.tex +documentation/skconfig.tex +documentation/cpukconfig.tex +documentation/socketfkconfig.tex

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Patch set updated for coreboot: 1a1217e inteltool: improve the libpci test in the Makefile
by Stefan Tauner 13 Oct '12

13 Oct '12

Stefan Tauner (stefan.tauner(a)gmx.at) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1575 -gerrit commit 1a1217e09f7b7216c414ebf104895f933623ff7a Author: Stefan Tauner <stefan.tauner(a)gmx.at> Date: Fri Oct 12 10:36:49 2012 +0200 inteltool: improve the libpci test in the Makefile Use the verbatim variable method to define and export test code and the actual libpci test from flashrom. This improves readability and will work with stricter compiler (settings). Change-Id: Iace7d53b0b992c4fde596ce1d606ad715d6dfc2a Signed-off-by: Stefan Tauner <stefan.tauner(a)gmx.at> --- util/inteltool/Makefile | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/util/inteltool/Makefile b/util/inteltool/Makefile index af79b1e..6c94460 100644 --- a/util/inteltool/Makefile +++ b/util/inteltool/Makefile @@ -53,12 +53,24 @@ distclean: clean dep: @$(CC) $(CFLAGS) -MM *.c > .dependencies +define LIBPCI_TEST +/* Avoid a failing test due to libpci header symbol shadowing breakage */ +#define index shadow_workaround_index +#include <pci/pci.h> +struct pci_access *pacc; +int main(int argc, char **argv) +{ + (void) argc; + (void) argv; + pacc = pci_alloc(); + return 0; +} +endef +export LIBPCI_TEST + pciutils: @printf "\nChecking for pciutils and zlib... " - @$(shell ( printf "#include <pci/pci.h>\n"; \ - printf "struct pci_access *pacc;\n"; \ - printf "int main(int argc, char **argv)\n"; \ - printf "{ pacc = pci_alloc(); return 0; }\n"; ) > .test.c ) + @echo "$$LIBPCI_TEST" > .test.c @$(CC) $(CFLAGS) .test.c -o .test $(LDFLAGS) >/dev/null 2>&1 && \ printf "found.\n" || ( printf "not found.\n\n"; \ printf "Please install pciutils-devel and zlib-devel.\n"; \

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Patch set updated for coreboot: b6f05be inteltool: remove bashism form Makefile
by Stefan Tauner 13 Oct '12

13 Oct '12

Stefan Tauner (stefan.tauner(a)gmx.at) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1573 -gerrit commit b6f05be0736490492b31bb8d7b0ffed4a86e116c Author: Stefan Tauner <stefan.tauner(a)gmx.at> Date: Sat Oct 13 02:33:35 2012 +0200 inteltool: remove bashism form Makefile &> is a bashism to redirect both outward streams (stdout and stderr), but with other shells this introduces a race condition with the rm command afterwards, because the compiler execution is done in the background/ in parallel. Change-Id: I08516494828c9f7af168f954f2df027372657867 Signed-off-by: Stefan Tauner <stefan.tauner(a)gmx.at> --- util/inteltool/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/inteltool/Makefile b/util/inteltool/Makefile index d754005..af79b1e 100644 --- a/util/inteltool/Makefile +++ b/util/inteltool/Makefile @@ -59,7 +59,7 @@ pciutils: printf "struct pci_access *pacc;\n"; \ printf "int main(int argc, char **argv)\n"; \ printf "{ pacc = pci_alloc(); return 0; }\n"; ) > .test.c ) - @$(CC) $(CFLAGS) .test.c -o .test $(LDFLAGS) &>/dev/null && \ + @$(CC) $(CFLAGS) .test.c -o .test $(LDFLAGS) >/dev/null 2>&1 && \ printf "found.\n" || ( printf "not found.\n\n"; \ printf "Please install pciutils-devel and zlib-devel.\n"; \ printf "See README for more information.\n\n"; \

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New patch to review for coreboot: 293fa38 inteltool: fix Makefile
by Stefan Tauner 13 Oct '12

13 Oct '12

Stefan Tauner (stefan.tauner(a)gmx.at) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1575 -gerrit commit 293fa38f467b4f8fe4a51857e141bd3b1719c8b1 Author: Stefan Tauner <stefan.tauner(a)gmx.at> Date: Fri Oct 12 10:36:49 2012 +0200 inteltool: fix Makefile Use the verbatim variable method to define and export test code and the actual libpci test from flashrom. This improves readability and will work with stricter compiler (settings). Change-Id: Iace7d53b0b992c4fde596ce1d606ad715d6dfc2a Signed-off-by: Stefan Tauner <stefan.tauner(a)gmx.at> --- util/inteltool/Makefile | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/util/inteltool/Makefile b/util/inteltool/Makefile index af79b1e..6c94460 100644 --- a/util/inteltool/Makefile +++ b/util/inteltool/Makefile @@ -53,12 +53,24 @@ distclean: clean dep: @$(CC) $(CFLAGS) -MM *.c > .dependencies +define LIBPCI_TEST +/* Avoid a failing test due to libpci header symbol shadowing breakage */ +#define index shadow_workaround_index +#include <pci/pci.h> +struct pci_access *pacc; +int main(int argc, char **argv) +{ + (void) argc; + (void) argv; + pacc = pci_alloc(); + return 0; +} +endef +export LIBPCI_TEST + pciutils: @printf "\nChecking for pciutils and zlib... " - @$(shell ( printf "#include <pci/pci.h>\n"; \ - printf "struct pci_access *pacc;\n"; \ - printf "int main(int argc, char **argv)\n"; \ - printf "{ pacc = pci_alloc(); return 0; }\n"; ) > .test.c ) + @echo "$$LIBPCI_TEST" > .test.c @$(CC) $(CFLAGS) .test.c -o .test $(LDFLAGS) >/dev/null 2>&1 && \ printf "found.\n" || ( printf "not found.\n\n"; \ printf "Please install pciutils-devel and zlib-devel.\n"; \

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Patch set updated for coreboot: e23f859 inteltool: new definitions and cleanup
by Stefan Tauner 13 Oct '12

13 Oct '12

Stefan Tauner (stefan.tauner(a)gmx.at) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1574 -gerrit commit e23f859c861ae9f5e686485e76446e4beef2140b Author: Stefan Tauner <stefan.tauner(a)gmx.at> Date: Sat Oct 13 02:19:30 2012 +0200 inteltool: new definitions and cleanup - Separate host bridges/DRAM controllers from LPC controllers in supported_chips_list[]. - Refine some names and macros. - Clean up some whitespace errors. - Add IDs and names of 5, 6 and 7 Series southbridges and the three latest Core CPU families with integrated memory controllers but do not implement any pretty printing routines for them yet. The first generation Core family is already supported, although it was wrongly named after the PCH and used the wrong ID. Also, the BAR values have been mangled to 32b instead of 64b. Both errors have been fixed and most basic support for the other two generations was added. Change-Id: Ief81e57f7c065cafac52e48b6364b57c72fcdf95 Signed-off-by: Stefan Tauner <stefan.tauner(a)gmx.at> --- util/inteltool/inteltool.c | 128 +++++++++++++++++++++++++++++++++------------ util/inteltool/inteltool.h | 28 +++++----- util/inteltool/memory.c | 62 +++++++++++++--------- util/inteltool/pcie.c | 75 ++++++++++++++------------ 4 files changed, 189 insertions(+), 104 deletions(-) diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 56bbc4a..2d99863 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -30,36 +30,54 @@ #include <unistd.h> #endif +/* + * http://pci-ids.ucw.cz/read/PC/8086 + * http://en.wikipedia.org/wiki/Intel_Tick-Tock + * http://en.wikipedia.org/wiki/List_of_Intel_chipsets + * http://en.wikipedia.org/wiki/Intel_Xeon_chipsets + */ static const struct { uint16_t vendor_id, device_id; char *name; } supported_chips_list[] = { - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX, "82443LX" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX, "82443BX" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_NO_AGP, "82443BX without AGP" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810, "i810" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810DC, "i810-DC100" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810E_MC, "i810E DC-133" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82830M, "i830M" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845, "i845" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865, "i865" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915, "82915G/P/GV/GL/PL/910GL" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945P, "i945P" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GM, "i945GM" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GSE, "i945GSE" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PM965, "PM965" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q965, "Q963/965" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82975X, "i975X" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q35, "Q35" }, + /* Host bridges/DRAM controllers (Northbridges) */ + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX, "443LX" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX, "443BX" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_NO_AGP, "443BX without AGP" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810, "810" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_DC, "810-DC100" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810E_DC, "810E DC-133" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82830M, "830M" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845, "845" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865, "865" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915, "915G/P/GV/GL/PL/910GL" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945P, "945P" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GM, "945GM" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GSE, "945GSE" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82965PM, "965PM" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q965, "Q963/82Q965" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82975X, "975X" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82G33, "P35/G33/G31/P31" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q33, "Q33" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58, "X58" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM65E, "HM65 Express" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GS45, "GS45ME" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q35, "Q35" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82X38, "X38/X48" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_32X0, "3200/3210" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82X4X, "GL40/GS40/GM45/GS45/PM45" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82X58, "X58" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000P, "Intel i5000P Memory Controller Hub" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000X, "Intel i5000X Memory Controller Hub" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000Z, "Intel i5000Z Memory Controller Hub" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000V, "Intel i5000V Memory Controller Hub" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_POULSBO, "SCH Poulsbo" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ATOM_DXXX, "Atom D400/500 Series" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ATOM_NXXX, "Atom N400 Series" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_POULSBO, "SCH Poulsbo" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC, "SCH Poulsbo" }, + /* Host bridges /DRAM controllers integrated in CPUs */ + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_1ST_GEN, "1st generation (Westmere family) Core Processor" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_2ND_GEN, "2nd generation (Sandy Bridge family) Core Processor" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_3RD_GEN, "3rd generation (Ivy Bridge family) Core Processor" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_4TH_GEN, "4th generation (Haswell family) Core Processor" }, + /* Southbridges (LPC controllers) */ + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "371AB/EB/MB" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10R, "ICH10R" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9DH, "ICH9DH" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9DO, "ICH9DO" }, @@ -81,14 +99,58 @@ static const struct { { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH2, "ICH2" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH0, "ICH0" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH, "ICH" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "82371AB/EB/MB" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X44, "82X38/X48" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_32X0, "3200/3210" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I63XX, "Intel 63xx I/O Controller Hub" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000P, "Intel i5000P Memory Controller Hub" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000X, "Intel i5000X Memory Controller Hub" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000Z, "Intel i5000Z Memory Controller Hub" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000V, "Intel i5000V Memory Controller Hub" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I63XX, "631xESB/632xESB/3100" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC, "SCH Poulsbo" }, + { PCI_VENDOR_ID_INTEL, 0x3b00, "3400 Desktop" }, + { PCI_VENDOR_ID_INTEL, 0x3b01, "3400 Mobile" }, + { PCI_VENDOR_ID_INTEL, 0x3b02, "P55" }, + { PCI_VENDOR_ID_INTEL, 0x3b03, "PM55" }, + { PCI_VENDOR_ID_INTEL, 0x3b06, "H55" }, + { PCI_VENDOR_ID_INTEL, 0x3b07, "QM57" }, + { PCI_VENDOR_ID_INTEL, 0x3b08, "H57" }, + { PCI_VENDOR_ID_INTEL, 0x3b09, "HM55" }, + { PCI_VENDOR_ID_INTEL, 0x3b0a, "Q57" }, + { PCI_VENDOR_ID_INTEL, 0x3b0b, "HM57" }, + { PCI_VENDOR_ID_INTEL, 0x3b0d, "3400 Mobile SFF" }, + { PCI_VENDOR_ID_INTEL, 0x3b0e, "B55" }, + { PCI_VENDOR_ID_INTEL, 0x3b0f, "QS57" }, + { PCI_VENDOR_ID_INTEL, 0x3b12, "3400" }, + { PCI_VENDOR_ID_INTEL, 0x3b14, "3420" }, + { PCI_VENDOR_ID_INTEL, 0x3b16, "3450" }, + { PCI_VENDOR_ID_INTEL, 0x3b1e, "B55" }, + { PCI_VENDOR_ID_INTEL, 0x1c44, "Z68" }, + { PCI_VENDOR_ID_INTEL, 0x1c46, "P67" }, + { PCI_VENDOR_ID_INTEL, 0x1c47, "UM67" }, + { PCI_VENDOR_ID_INTEL, 0x1c49, "HM65" }, + { PCI_VENDOR_ID_INTEL, 0x1c4a, "H67" }, + { PCI_VENDOR_ID_INTEL, 0x1c4b, "HM67" }, + { PCI_VENDOR_ID_INTEL, 0x1c4c, "Q65" }, + { PCI_VENDOR_ID_INTEL, 0x1c4d, "QS67" }, + { PCI_VENDOR_ID_INTEL, 0x1c4e, "Q67" }, + { PCI_VENDOR_ID_INTEL, 0x1c4f, "QM67" }, + { PCI_VENDOR_ID_INTEL, 0x1c50, "B65" }, + { PCI_VENDOR_ID_INTEL, 0x1c52, "C202" }, + { PCI_VENDOR_ID_INTEL, 0x1c54, "C204" }, + { PCI_VENDOR_ID_INTEL, 0x1c56, "C206" }, + { PCI_VENDOR_ID_INTEL, 0x1c5c, "H61" }, + { PCI_VENDOR_ID_INTEL, 0x1d40, "X79" }, + { PCI_VENDOR_ID_INTEL, 0x1d41, "X79" }, + { PCI_VENDOR_ID_INTEL, 0x1e44, "Z77" }, + { PCI_VENDOR_ID_INTEL, 0x1e46, "Z75" }, + { PCI_VENDOR_ID_INTEL, 0x1e47, "Q77" }, + { PCI_VENDOR_ID_INTEL, 0x1e48, "Q75" }, + { PCI_VENDOR_ID_INTEL, 0x1e49, "B75" }, + { PCI_VENDOR_ID_INTEL, 0x1e4a, "H77" }, + { PCI_VENDOR_ID_INTEL, 0x1e53, "C216" }, + { PCI_VENDOR_ID_INTEL, 0x1e55, "QM77" }, + { PCI_VENDOR_ID_INTEL, 0x1e56, "QS77" }, + { PCI_VENDOR_ID_INTEL, 0x1e57, "HM77" }, + { PCI_VENDOR_ID_INTEL, 0x1e58, "UM77" }, + { PCI_VENDOR_ID_INTEL, 0x1e59, "HM76" }, + { PCI_VENDOR_ID_INTEL, 0x1e5d, "HM75" }, + { PCI_VENDOR_ID_INTEL, 0x1e5e, "HM70" }, + { PCI_VENDOR_ID_INTEL, 0x1e5f, "NM70" }, + { PCI_VENDOR_ID_INTEL, 0x2310, "DH89xxCC" }, }; #ifndef __DARWIN__ @@ -309,7 +371,7 @@ int main(int argc, char *argv[]) * left-shifted "Extended Model" fields. * http://download.intel.com/design/processor/applnots/24161832.pdf */ - printf("Intel CPU: Processor Type: %x, Family %x, Model %x, Stepping %x\n", + printf("CPU: Processor Type: %x, Family %x, Model %x, Stepping %x\n", (id >> 12) & 0x3, ((id >> 8) & 0xf) + ((id >> 20) & 0xff), ((id >> 12) & 0xf0) + ((id >> 4) & 0xf), (id & 0xf)); @@ -321,10 +383,10 @@ int main(int argc, char *argv[]) if (sb->device_id == supported_chips_list[i].device_id) sbname = supported_chips_list[i].name; - printf("Intel Northbridge: %04x:%04x (%s)\n", + printf("Northbridge: %04x:%04x (%s)\n", nb->vendor_id, nb->device_id, nbname); - printf("Intel Southbridge: %04x:%04x (%s)\n", + printf("Southbridge: %04x:%04x (%s)\n", sb->vendor_id, sb->device_id, sbname); /* Now do the deed */ diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index aa8a292..7ef2d8d 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -63,27 +63,27 @@ #define PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC 0x8119 #define PCI_DEVICE_ID_INTEL_82810 0x7120 -#define PCI_DEVICE_ID_INTEL_82810DC 0x7122 -#define PCI_DEVICE_ID_INTEL_82810E_MC 0x7124 +#define PCI_DEVICE_ID_INTEL_82810_DC 0x7122 +#define PCI_DEVICE_ID_INTEL_82810E_DC 0x7124 #define PCI_DEVICE_ID_INTEL_82830M 0x3575 #define PCI_DEVICE_ID_INTEL_82845 0x1a30 #define PCI_DEVICE_ID_INTEL_82865 0x2570 #define PCI_DEVICE_ID_INTEL_82915 0x2580 #define PCI_DEVICE_ID_INTEL_82945P 0x2770 #define PCI_DEVICE_ID_INTEL_82945GM 0x27a0 -#define PCI_DEVICE_ID_INTEL_82945GSE 0x27ac -#define PCI_DEVICE_ID_INTEL_PM965 0x2a00 -#define PCI_DEVICE_ID_INTEL_Q965 0x2990 +#define PCI_DEVICE_ID_INTEL_82945GSE 0x27ac +#define PCI_DEVICE_ID_INTEL_82965PM 0x2a00 +#define PCI_DEVICE_ID_INTEL_82Q965 0x2990 #define PCI_DEVICE_ID_INTEL_82975X 0x277c #define PCI_DEVICE_ID_INTEL_82Q35 0x29b0 #define PCI_DEVICE_ID_INTEL_82G33 0x29c0 #define PCI_DEVICE_ID_INTEL_82Q33 0x29d0 -#define PCI_DEVICE_ID_INTEL_X44 0x29e0 +#define PCI_DEVICE_ID_INTEL_82X38 0x29e0 #define PCI_DEVICE_ID_INTEL_32X0 0x29f0 -#define PCI_DEVICE_ID_INTEL_GS45 0x2a40 -#define PCI_DEVICE_ID_INTEL_X58 0x3405 -#define PCI_DEVICE_ID_INTEL_SCH_POULSBO 0x8100 -#define PCI_DEVICE_ID_INTEL_ATOM_DXXX 0xa000 +#define PCI_DEVICE_ID_INTEL_82X4X 0x2a40 +#define PCI_DEVICE_ID_INTEL_82X58 0x3405 +#define PCI_DEVICE_ID_INTEL_SCH_POULSBO 0x8100 +#define PCI_DEVICE_ID_INTEL_ATOM_DXXX 0xa000 #define PCI_DEVICE_ID_INTEL_I63XX 0x2670 #define PCI_DEVICE_ID_INTEL_I5000X 0x25c0 @@ -92,7 +92,7 @@ #define PCI_DEVICE_ID_INTEL_I5000P 0x25d8 /* untested, but almost identical to D-series */ -#define PCI_DEVICE_ID_INTEL_ATOM_NXXX 0xa010 +#define PCI_DEVICE_ID_INTEL_ATOM_NXXX 0xa010 #define PCI_DEVICE_ID_INTEL_82443LX 0x7180 /* 82443BX has a different device ID if AGP is disabled (hardware-wise). */ @@ -102,7 +102,11 @@ /* 82371AB/EB/MB use the same device ID value. */ #define PCI_DEVICE_ID_INTEL_82371XX 0x7110 -#define PCI_DEVICE_ID_INTEL_HM65E 0x0104 +/* Intel starts counting these generations with the integration of the DRAM controller */ +#define PCI_DEVICE_ID_INTEL_CORE_1ST_GEN 0x0044 /* Westmere */ +#define PCI_DEVICE_ID_INTEL_CORE_2ND_GEN 0x0104 /* Sandy Bridge */ +#define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN 0x0154 /* Ivy Bridge */ +#define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN 0x0c04 /* Haswell */ #define ARRAY_SIZE(a) ((int)(sizeof(a) / sizeof((a)[0]))) diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c index d66ee48..62d7217 100644 --- a/util/inteltool/memory.c +++ b/util/inteltool/memory.c @@ -108,20 +108,20 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc) case PCI_DEVICE_ID_INTEL_82945GM: case PCI_DEVICE_ID_INTEL_82945GSE: case PCI_DEVICE_ID_INTEL_82945P: - case PCI_DEVICE_ID_INTEL_82975X: + case PCI_DEVICE_ID_INTEL_82975X: mchbar_phys = pci_read_long(nb, 0x44) & 0xfffffffe; break; - case PCI_DEVICE_ID_INTEL_PM965: - case PCI_DEVICE_ID_INTEL_82Q35: - case PCI_DEVICE_ID_INTEL_82G33: - case PCI_DEVICE_ID_INTEL_82Q33: - mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe; - mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; - break; - case PCI_DEVICE_ID_INTEL_Q965: + case PCI_DEVICE_ID_INTEL_82965PM: + case PCI_DEVICE_ID_INTEL_82Q35: + case PCI_DEVICE_ID_INTEL_82G33: + case PCI_DEVICE_ID_INTEL_82Q33: + mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe; + mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; + break; + case PCI_DEVICE_ID_INTEL_82Q965: case PCI_DEVICE_ID_INTEL_ATOM_DXXX: case PCI_DEVICE_ID_INTEL_ATOM_NXXX: - mchbar_phys = pci_read_long(nb, 0x48); + mchbar_phys = pci_read_long(nb, 0x48); /* Test if bit 0 of the MCHBAR reg is 1 to enable memory reads. * If it isn't, try to set it. This may fail, because there is @@ -131,36 +131,45 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc) if(!(mchbar_phys & 1)) { - printf("Access to the MCHBAR is currently disabled, "\ - "attempting to enable.\n"); + printf("Access to the MCHBAR is currently disabled, " + "attempting to enable.\n"); mchbar_phys |= 0x1; pci_write_long(nb, 0x48, mchbar_phys); - if(pci_read_long(nb, 0x48) & 1) + if(pci_read_long(nb, 0x48) & 1) printf("Enabled successfully.\n"); else printf("Enable FAILED!\n"); } mchbar_phys &= 0xfffffffe; - mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; - break; + mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; + break; case PCI_DEVICE_ID_INTEL_82443LX: case PCI_DEVICE_ID_INTEL_82443BX: case PCI_DEVICE_ID_INTEL_82810: - case PCI_DEVICE_ID_INTEL_82810E_MC: - case PCI_DEVICE_ID_INTEL_82810DC: + case PCI_DEVICE_ID_INTEL_82810E_DC: + case PCI_DEVICE_ID_INTEL_82810_DC: case PCI_DEVICE_ID_INTEL_82830M: printf("This northbridge does not have MCHBAR.\n"); return 1; - case PCI_DEVICE_ID_INTEL_GS45: - case PCI_DEVICE_ID_INTEL_X44: + case PCI_DEVICE_ID_INTEL_82X4X: + case PCI_DEVICE_ID_INTEL_82X38: case PCI_DEVICE_ID_INTEL_32X0: mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe; mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; - break; - case PCI_DEVICE_ID_INTEL_HM65E: - mchbar_phys = pci_read_long(nb, 0x48) & 0xffff8000; + break; + case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN: + mchbar_phys = pci_read_long(nb, 0x48); + mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; + mchbar_phys &= 0x0000000fffffc000UL; /* 35:14 */ + mch_registers = NULL; /* No public documentation */ + break; + case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN: mch_registers = sandybridge_mch_registers; size = ARRAY_SIZE(sandybridge_mch_registers); + case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN: /* pretty printing not implemented yet */ + mchbar_phys = pci_read_long(nb, 0x48); + mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; + mchbar_phys &= 0x0000007fffff8000UL; /* 38:15 */ break; default: printf("Error: Dumping MCHBAR on this northbridge is not (yet) supported.\n"); @@ -183,28 +192,29 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc) printf("MCHBAR = 0x%08" PRIx64 " (MEM)\n\n", mchbar_phys); if (mch_registers != NULL) { + printf("%d registers:\n", size); for (i = 0; i < size; i++) { switch (mch_registers[i].size) { case 8: - printf("mchbase+0x%04x: 0x%08lx (%s)\n", + printf("mchbase+0x%04x: 0x%016lx (%s)\n", mch_registers[i].addr, *(uint64_t *)(mchbar+mch_registers[i].addr), mch_registers[i].name); break; case 4: - printf("mchbase+0x%04x: 0x%08x (%s)\n", + printf("mchbase+0x%04x: 0x%08x (%s)\n", mch_registers[i].addr, *(uint32_t *)(mchbar+mch_registers[i].addr), mch_registers[i].name); break; case 2: - printf("mchbase+0x%04x: 0x%04x (%s)\n", + printf("mchbase+0x%04x: 0x%04x (%s)\n", mch_registers[i].addr, *(uint16_t *)(mchbar+mch_registers[i].addr), mch_registers[i].name); break; case 1: - printf("mchbase+0x%04x: 0x%02x (%s)\n", + printf("mchbase+0x%04x: 0x%02x (%s)\n", mch_registers[i].addr, *(uint8_t *)(mchbar+mch_registers[i].addr), mch_registers[i].name); diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c index a7429a0..e454f44 100644 --- a/util/inteltool/pcie.c +++ b/util/inteltool/pcie.c @@ -94,22 +94,22 @@ int print_epbar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_82975X: epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; break; - case PCI_DEVICE_ID_INTEL_PM965: - case PCI_DEVICE_ID_INTEL_Q965: - case PCI_DEVICE_ID_INTEL_82Q35: - case PCI_DEVICE_ID_INTEL_82G33: - case PCI_DEVICE_ID_INTEL_82Q33: - case PCI_DEVICE_ID_INTEL_X44: + case PCI_DEVICE_ID_INTEL_82965PM: + case PCI_DEVICE_ID_INTEL_82Q965: + case PCI_DEVICE_ID_INTEL_82Q35: + case PCI_DEVICE_ID_INTEL_82G33: + case PCI_DEVICE_ID_INTEL_82Q33: + case PCI_DEVICE_ID_INTEL_82X38: case PCI_DEVICE_ID_INTEL_32X0: - case PCI_DEVICE_ID_INTEL_GS45: + case PCI_DEVICE_ID_INTEL_82X4X: case PCI_DEVICE_ID_INTEL_ATOM_DXXX: case PCI_DEVICE_ID_INTEL_ATOM_NXXX: - epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; - epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32; - break; + epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; + epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32; + break; case PCI_DEVICE_ID_INTEL_82810: - case PCI_DEVICE_ID_INTEL_82810DC: - case PCI_DEVICE_ID_INTEL_82810E_MC: + case PCI_DEVICE_ID_INTEL_82810_DC: + case PCI_DEVICE_ID_INTEL_82810E_DC: case PCI_DEVICE_ID_INTEL_82830M: case PCI_DEVICE_ID_INTEL_82865: printf("This northbridge does not have EPBAR.\n"); @@ -156,32 +156,41 @@ int print_dmibar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_82975X: dmibar_phys = pci_read_long(nb, 0x4c) & 0xfffffffe; break; - case PCI_DEVICE_ID_INTEL_PM965: - case PCI_DEVICE_ID_INTEL_Q965: + case PCI_DEVICE_ID_INTEL_82965PM: + case PCI_DEVICE_ID_INTEL_82Q965: case PCI_DEVICE_ID_INTEL_82Q35: case PCI_DEVICE_ID_INTEL_82G33: case PCI_DEVICE_ID_INTEL_82Q33: - case PCI_DEVICE_ID_INTEL_X44: + case PCI_DEVICE_ID_INTEL_82X38: case PCI_DEVICE_ID_INTEL_32X0: - case PCI_DEVICE_ID_INTEL_GS45: + case PCI_DEVICE_ID_INTEL_82X4X: case PCI_DEVICE_ID_INTEL_ATOM_DXXX: case PCI_DEVICE_ID_INTEL_ATOM_NXXX: dmibar_phys = pci_read_long(nb, 0x68) & 0xfffffffe; dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32; break; case PCI_DEVICE_ID_INTEL_82810: - case PCI_DEVICE_ID_INTEL_82810DC: - case PCI_DEVICE_ID_INTEL_82810E_MC: + case PCI_DEVICE_ID_INTEL_82810_DC: + case PCI_DEVICE_ID_INTEL_82810E_DC: case PCI_DEVICE_ID_INTEL_82865: printf("This northbridge does not have DMIBAR.\n"); return 1; - case PCI_DEVICE_ID_INTEL_X58: + case PCI_DEVICE_ID_INTEL_82X58: dmibar_phys = pci_read_long(nb, 0x50) & 0xfffff000; break; - case PCI_DEVICE_ID_INTEL_HM65E: - dmibar_phys = pci_read_long(nb, 0x68) & 0xfffff000; + case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN: + dmibar_phys = pci_read_long(nb, 0x68); + dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32; + dmibar_phys &= 0x0000000ffffff000UL; /* 35:12 */ + dmi_registers = NULL; /* No public documentation */ + break; + case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN: dmi_registers = sandybridge_dmi_registers; size = ARRAY_SIZE(sandybridge_dmi_registers); + case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN: /* pretty printing not implemented yet */ + dmibar_phys = pci_read_long(nb, 0x68); + dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32; + dmibar_phys &= 0x0000007ffffff000UL; /* 38:12 */ break; default: printf("Error: Dumping DMIBAR on this northbridge is not (yet) supported.\n"); @@ -251,22 +260,22 @@ int print_pciexbar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_82975X: pciexbar_reg = pci_read_long(nb, 0x48); break; - case PCI_DEVICE_ID_INTEL_PM965: - case PCI_DEVICE_ID_INTEL_Q965: - case PCI_DEVICE_ID_INTEL_82Q35: - case PCI_DEVICE_ID_INTEL_82G33: - case PCI_DEVICE_ID_INTEL_82Q33: - case PCI_DEVICE_ID_INTEL_X44: + case PCI_DEVICE_ID_INTEL_82965PM: + case PCI_DEVICE_ID_INTEL_82Q965: + case PCI_DEVICE_ID_INTEL_82Q35: + case PCI_DEVICE_ID_INTEL_82G33: + case PCI_DEVICE_ID_INTEL_82Q33: + case PCI_DEVICE_ID_INTEL_82X38: case PCI_DEVICE_ID_INTEL_32X0: - case PCI_DEVICE_ID_INTEL_GS45: + case PCI_DEVICE_ID_INTEL_82X4X: case PCI_DEVICE_ID_INTEL_ATOM_DXXX: case PCI_DEVICE_ID_INTEL_ATOM_NXXX: - pciexbar_reg = pci_read_long(nb, 0x60); - pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32; - break; + pciexbar_reg = pci_read_long(nb, 0x60); + pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32; + break; case PCI_DEVICE_ID_INTEL_82810: - case PCI_DEVICE_ID_INTEL_82810DC: - case PCI_DEVICE_ID_INTEL_82810E_MC: + case PCI_DEVICE_ID_INTEL_82810_DC: + case PCI_DEVICE_ID_INTEL_82810E_DC: case PCI_DEVICE_ID_INTEL_82865: printf("Error: This northbridge does not have PCIEXBAR.\n"); return 1;

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Status of Intel Poulsbo US15W
by Sebastian Andrzej Siewior 12 Oct '12

12 Oct '12

Does anyone have an idea what the status of Intel's poulsbou in current coreboot is? - cmc contained no mem config. So I dumped the registers from the running system (sch, port1, reg0..2) from the running system and filled out sysinfo->ranks, cl, trcd, trp, device_density, data_width based on those values. - I noticed that my FSB runs at 533MHz. So I set the lower bit in SCH_MSG_DUNIT_REG_DCO (the orignial code sets BIT 0 if FSB is 533 but then throwes it away and writes 0x006911c). Now: - The SCH register 2, 8 is set to 0x40000000 (1GiB). The original BIOS sets this to 0x80000000 (2GiB) which would also match the magic with data_width, ranks & device_density which result is overwritten. Is this correct? What is the purpose of this value? - In sch_shadow_CMC(). I have no idea why cpuid_eax(0x80000008) should be written in that register. I haven't found any documentation claiming that it should be done. The system hangs after executing a wbinvd like the manual says. That is probably why the cmc code is copied twice and the wbinvd is commented out. It hangs mostlikely due to the CAR setup. So maybe it could be moved to southbridge setup somewhere. - in src/northbridge/intel/sch/northbridge.c, pci_domain_set_resources() is using PCI device (0,0) register 0x9c is used to figure out how much memory is available. I read 0x0 here in original bios and coreboot. I assigned 1 GiB here for the variable. Is this a BIOS set variable? This file / function looks like a copy of src/northbridge/intel/i945/northbridge.c. For TOM it could be SCH (2, 8) because this is written by sdram_initialize() (with the wrong value in my setup however). It is just a guess however. The next part reads GGC register and I belive from wrong device as it should be PCI_DEVFN(2, 0). Atlteast it is written in iWRainbowG6's romstage.c TSEG is read from pci dev (0,0) register 0x9e. I'm not sure this is correct, I don't see any place that this is written. - I extraced the VGA ROM from the BIOS. After attaching it I see three unhandled INT15 calls with AX=0x5f35, AX=0x5f40, AX=0x5f35. After that coreboot continues, display remains blank. Is it possible to emulate these calls to get some output? Linux somehow des not do anything right now… - After booting I get errors from the ehci controller after attaching a highspeed device. Attaching a keyboard seems to works. Is there something I have to tweak to get highspeed USB working? I could send patches for some of things but I am not always sure what I do :) Sebastian

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Patch set updated for coreboot: 29c014c inteltool: new definitions and cleanup
by Stefan Tauner 12 Oct '12

12 Oct '12

Stefan Tauner (stefan.tauner(a)gmx.at) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1574 -gerrit commit 29c014c27749caf9074de223150ac173e93b7ff9 Author: Stefan Tauner <stefan.tauner(a)gmx.at> Date: Fri Oct 12 12:27:21 2012 +0200 inteltool: new definitions and cleanup - Separate host bridges/DRAM controllers from LPC controllers in supported_chips_list[]. - Refine some names and macros. - Clean up some whitespace errors. - Add IDs and names of 5, 6 and 7 Series southbridges and the the three latest Core CPU families with integrated memory controllers but do not implement any pretty printing routines for them yet. The first generation Core family is already supported, although it was wrongly named after the PCH and used the wrong ID. Also, the BAR values have been mangled to 32b instead of 64b. Both errors have been fixed and most basic support for the other two generations were added. Change-Id: Ief81e57f7c065cafac52e48b6364b57c72fcdf95 Signed-off-by: Stefan Tauner <stefan.tauner(a)gmx.at> --- util/inteltool/inteltool.c | 128 +++++++++++++++++++++++++++++++++------------ util/inteltool/inteltool.h | 28 +++++----- util/inteltool/memory.c | 62 +++++++++++++--------- util/inteltool/pcie.c | 75 ++++++++++++++------------ 4 files changed, 189 insertions(+), 104 deletions(-) diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 56bbc4a..60e9630 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -30,36 +30,54 @@ #include <unistd.h> #endif +/* + * http://pci-ids.ucw.cz/read/PC/8086 + * http://en.wikipedia.org/wiki/Intel_Tick-Tock + * http://en.wikipedia.org/wiki/List_of_Intel_chipsets + * http://en.wikipedia.org/wiki/Intel_Xeon_chipsets + */ static const struct { uint16_t vendor_id, device_id; char *name; } supported_chips_list[] = { - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX, "82443LX" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX, "82443BX" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_NO_AGP, "82443BX without AGP" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810, "i810" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810DC, "i810-DC100" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810E_MC, "i810E DC-133" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82830M, "i830M" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845, "i845" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865, "i865" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915, "82915G/P/GV/GL/PL/910GL" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945P, "i945P" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GM, "i945GM" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GSE, "i945GSE" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PM965, "PM965" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q965, "Q963/965" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82975X, "i975X" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q35, "Q35" }, + /* Host bridges/DRAM controllers (Northbridges) */ + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX, "443LX" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX, "443BX" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_NO_AGP, "443BX without AGP" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810, "810" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_DC, "810-DC100" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810E_DC, "810E DC-133" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82830M, "830M" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845, "845" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865, "865" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915, "915G/P/GV/GL/PL/910GL" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945P, "945P" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GM, "945GM" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GSE, "945GSE" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82965PM, "965PM" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q965, "Q963/82Q965" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82975X, "975X" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82G33, "P35/G33/G31/P31" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q33, "Q33" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58, "X58" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM65E, "HM65 Express" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GS45, "GS45ME" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q35, "Q35" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82X38, "X38/X48" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_32X0, "3200/3210" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82X4X, "GL40/GS40/GM45/GS45/PM45" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82X58, "X58" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000P, "Intel i5000P Memory Controller Hub" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000X, "Intel i5000X Memory Controller Hub" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000Z, "Intel i5000Z Memory Controller Hub" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000V, "Intel i5000V Memory Controller Hub" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_POULSBO, "SCH Poulsbo" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ATOM_DXXX, "Atom D400/500 Series" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ATOM_NXXX, "Atom N400 Series" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_POULSBO, "SCH Poulsbo" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC, "SCH Poulsbo" }, + /* Host bridges /DRAM controllers integrated in CPUs */ + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_1ST_GEN, "1st generation (Westmere family) Core Processor" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_2ND_GEN, "2nd generation (Sandy family) Core Processor" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_3RD_GEN, "3rd generation (Ivy Bridge family) Core Processor" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_4TH_GEN, "4th generation (Haswell family) Core Processor" }, + /* Southbridges (LPC controllers) */ + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "371AB/EB/MB" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10R, "ICH10R" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9DH, "ICH9DH" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9DO, "ICH9DO" }, @@ -81,14 +99,58 @@ static const struct { { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH2, "ICH2" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH0, "ICH0" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH, "ICH" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "82371AB/EB/MB" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X44, "82X38/X48" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_32X0, "3200/3210" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I63XX, "Intel 63xx I/O Controller Hub" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000P, "Intel i5000P Memory Controller Hub" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000X, "Intel i5000X Memory Controller Hub" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000Z, "Intel i5000Z Memory Controller Hub" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000V, "Intel i5000V Memory Controller Hub" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I63XX, "631xESB/632xESB/3100" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC, "SCH Poulsbo" }, + { PCI_VENDOR_ID_INTEL, 0x3b00, "3400 Desktop" }, + { PCI_VENDOR_ID_INTEL, 0x3b01, "3400 Mobile" }, + { PCI_VENDOR_ID_INTEL, 0x3b02, "P55" }, + { PCI_VENDOR_ID_INTEL, 0x3b03, "PM55" }, + { PCI_VENDOR_ID_INTEL, 0x3b06, "H55" }, + { PCI_VENDOR_ID_INTEL, 0x3b07, "QM57" }, + { PCI_VENDOR_ID_INTEL, 0x3b08, "H57" }, + { PCI_VENDOR_ID_INTEL, 0x3b09, "HM55" }, + { PCI_VENDOR_ID_INTEL, 0x3b0a, "Q57" }, + { PCI_VENDOR_ID_INTEL, 0x3b0b, "HM57" }, + { PCI_VENDOR_ID_INTEL, 0x3b0d, "3400 Mobile SFF" }, + { PCI_VENDOR_ID_INTEL, 0x3b0e, "B55" }, + { PCI_VENDOR_ID_INTEL, 0x3b0f, "QS57" }, + { PCI_VENDOR_ID_INTEL, 0x3b12, "3400" }, + { PCI_VENDOR_ID_INTEL, 0x3b14, "3420" }, + { PCI_VENDOR_ID_INTEL, 0x3b16, "3450" }, + { PCI_VENDOR_ID_INTEL, 0x3b1e, "B55" }, + { PCI_VENDOR_ID_INTEL, 0x1c44, "Z68" }, + { PCI_VENDOR_ID_INTEL, 0x1c46, "P67" }, + { PCI_VENDOR_ID_INTEL, 0x1c47, "UM67" }, + { PCI_VENDOR_ID_INTEL, 0x1c49, "HM65" }, + { PCI_VENDOR_ID_INTEL, 0x1c4a, "H67" }, + { PCI_VENDOR_ID_INTEL, 0x1c4b, "HM67" }, + { PCI_VENDOR_ID_INTEL, 0x1c4c, "Q65" }, + { PCI_VENDOR_ID_INTEL, 0x1c4d, "QS67" }, + { PCI_VENDOR_ID_INTEL, 0x1c4e, "Q67" }, + { PCI_VENDOR_ID_INTEL, 0x1c4f, "QM67" }, + { PCI_VENDOR_ID_INTEL, 0x1c50, "B65" }, + { PCI_VENDOR_ID_INTEL, 0x1c52, "C202" }, + { PCI_VENDOR_ID_INTEL, 0x1c54, "C204" }, + { PCI_VENDOR_ID_INTEL, 0x1c56, "C206" }, + { PCI_VENDOR_ID_INTEL, 0x1c5c, "H61" }, + { PCI_VENDOR_ID_INTEL, 0x1d40, "X79" }, + { PCI_VENDOR_ID_INTEL, 0x1d41, "X79" }, + { PCI_VENDOR_ID_INTEL, 0x1e44, "Z77" }, + { PCI_VENDOR_ID_INTEL, 0x1e46, "Z75" }, + { PCI_VENDOR_ID_INTEL, 0x1e47, "Q77" }, + { PCI_VENDOR_ID_INTEL, 0x1e48, "Q75" }, + { PCI_VENDOR_ID_INTEL, 0x1e49, "B75" }, + { PCI_VENDOR_ID_INTEL, 0x1e4a, "H77" }, + { PCI_VENDOR_ID_INTEL, 0x1e53, "C216" }, + { PCI_VENDOR_ID_INTEL, 0x1e55, "QM77" }, + { PCI_VENDOR_ID_INTEL, 0x1e56, "QS77" }, + { PCI_VENDOR_ID_INTEL, 0x1e57, "HM77" }, + { PCI_VENDOR_ID_INTEL, 0x1e58, "UM77" }, + { PCI_VENDOR_ID_INTEL, 0x1e59, "HM76" }, + { PCI_VENDOR_ID_INTEL, 0x1e5d, "HM75" }, + { PCI_VENDOR_ID_INTEL, 0x1e5e, "HM70" }, + { PCI_VENDOR_ID_INTEL, 0x1e5f, "NM70" }, + { PCI_VENDOR_ID_INTEL, 0x2310, "DH89xxCC" }, }; #ifndef __DARWIN__ @@ -309,7 +371,7 @@ int main(int argc, char *argv[]) * left-shifted "Extended Model" fields. * http://download.intel.com/design/processor/applnots/24161832.pdf */ - printf("Intel CPU: Processor Type: %x, Family %x, Model %x, Stepping %x\n", + printf("CPU: Processor Type: %x, Family %x, Model %x, Stepping %x\n", (id >> 12) & 0x3, ((id >> 8) & 0xf) + ((id >> 20) & 0xff), ((id >> 12) & 0xf0) + ((id >> 4) & 0xf), (id & 0xf)); @@ -321,10 +383,10 @@ int main(int argc, char *argv[]) if (sb->device_id == supported_chips_list[i].device_id) sbname = supported_chips_list[i].name; - printf("Intel Northbridge: %04x:%04x (%s)\n", + printf("Northbridge: %04x:%04x (%s)\n", nb->vendor_id, nb->device_id, nbname); - printf("Intel Southbridge: %04x:%04x (%s)\n", + printf("Southbridge: %04x:%04x (%s)\n", sb->vendor_id, sb->device_id, sbname); /* Now do the deed */ diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index aa8a292..7ef2d8d 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -63,27 +63,27 @@ #define PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC 0x8119 #define PCI_DEVICE_ID_INTEL_82810 0x7120 -#define PCI_DEVICE_ID_INTEL_82810DC 0x7122 -#define PCI_DEVICE_ID_INTEL_82810E_MC 0x7124 +#define PCI_DEVICE_ID_INTEL_82810_DC 0x7122 +#define PCI_DEVICE_ID_INTEL_82810E_DC 0x7124 #define PCI_DEVICE_ID_INTEL_82830M 0x3575 #define PCI_DEVICE_ID_INTEL_82845 0x1a30 #define PCI_DEVICE_ID_INTEL_82865 0x2570 #define PCI_DEVICE_ID_INTEL_82915 0x2580 #define PCI_DEVICE_ID_INTEL_82945P 0x2770 #define PCI_DEVICE_ID_INTEL_82945GM 0x27a0 -#define PCI_DEVICE_ID_INTEL_82945GSE 0x27ac -#define PCI_DEVICE_ID_INTEL_PM965 0x2a00 -#define PCI_DEVICE_ID_INTEL_Q965 0x2990 +#define PCI_DEVICE_ID_INTEL_82945GSE 0x27ac +#define PCI_DEVICE_ID_INTEL_82965PM 0x2a00 +#define PCI_DEVICE_ID_INTEL_82Q965 0x2990 #define PCI_DEVICE_ID_INTEL_82975X 0x277c #define PCI_DEVICE_ID_INTEL_82Q35 0x29b0 #define PCI_DEVICE_ID_INTEL_82G33 0x29c0 #define PCI_DEVICE_ID_INTEL_82Q33 0x29d0 -#define PCI_DEVICE_ID_INTEL_X44 0x29e0 +#define PCI_DEVICE_ID_INTEL_82X38 0x29e0 #define PCI_DEVICE_ID_INTEL_32X0 0x29f0 -#define PCI_DEVICE_ID_INTEL_GS45 0x2a40 -#define PCI_DEVICE_ID_INTEL_X58 0x3405 -#define PCI_DEVICE_ID_INTEL_SCH_POULSBO 0x8100 -#define PCI_DEVICE_ID_INTEL_ATOM_DXXX 0xa000 +#define PCI_DEVICE_ID_INTEL_82X4X 0x2a40 +#define PCI_DEVICE_ID_INTEL_82X58 0x3405 +#define PCI_DEVICE_ID_INTEL_SCH_POULSBO 0x8100 +#define PCI_DEVICE_ID_INTEL_ATOM_DXXX 0xa000 #define PCI_DEVICE_ID_INTEL_I63XX 0x2670 #define PCI_DEVICE_ID_INTEL_I5000X 0x25c0 @@ -92,7 +92,7 @@ #define PCI_DEVICE_ID_INTEL_I5000P 0x25d8 /* untested, but almost identical to D-series */ -#define PCI_DEVICE_ID_INTEL_ATOM_NXXX 0xa010 +#define PCI_DEVICE_ID_INTEL_ATOM_NXXX 0xa010 #define PCI_DEVICE_ID_INTEL_82443LX 0x7180 /* 82443BX has a different device ID if AGP is disabled (hardware-wise). */ @@ -102,7 +102,11 @@ /* 82371AB/EB/MB use the same device ID value. */ #define PCI_DEVICE_ID_INTEL_82371XX 0x7110 -#define PCI_DEVICE_ID_INTEL_HM65E 0x0104 +/* Intel starts counting these generations with the integration of the DRAM controller */ +#define PCI_DEVICE_ID_INTEL_CORE_1ST_GEN 0x0044 /* Westmere */ +#define PCI_DEVICE_ID_INTEL_CORE_2ND_GEN 0x0104 /* Sandy Bridge */ +#define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN 0x0154 /* Ivy Bridge */ +#define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN 0x0c04 /* Haswell */ #define ARRAY_SIZE(a) ((int)(sizeof(a) / sizeof((a)[0]))) diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c index d66ee48..62d7217 100644 --- a/util/inteltool/memory.c +++ b/util/inteltool/memory.c @@ -108,20 +108,20 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc) case PCI_DEVICE_ID_INTEL_82945GM: case PCI_DEVICE_ID_INTEL_82945GSE: case PCI_DEVICE_ID_INTEL_82945P: - case PCI_DEVICE_ID_INTEL_82975X: + case PCI_DEVICE_ID_INTEL_82975X: mchbar_phys = pci_read_long(nb, 0x44) & 0xfffffffe; break; - case PCI_DEVICE_ID_INTEL_PM965: - case PCI_DEVICE_ID_INTEL_82Q35: - case PCI_DEVICE_ID_INTEL_82G33: - case PCI_DEVICE_ID_INTEL_82Q33: - mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe; - mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; - break; - case PCI_DEVICE_ID_INTEL_Q965: + case PCI_DEVICE_ID_INTEL_82965PM: + case PCI_DEVICE_ID_INTEL_82Q35: + case PCI_DEVICE_ID_INTEL_82G33: + case PCI_DEVICE_ID_INTEL_82Q33: + mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe; + mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; + break; + case PCI_DEVICE_ID_INTEL_82Q965: case PCI_DEVICE_ID_INTEL_ATOM_DXXX: case PCI_DEVICE_ID_INTEL_ATOM_NXXX: - mchbar_phys = pci_read_long(nb, 0x48); + mchbar_phys = pci_read_long(nb, 0x48); /* Test if bit 0 of the MCHBAR reg is 1 to enable memory reads. * If it isn't, try to set it. This may fail, because there is @@ -131,36 +131,45 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc) if(!(mchbar_phys & 1)) { - printf("Access to the MCHBAR is currently disabled, "\ - "attempting to enable.\n"); + printf("Access to the MCHBAR is currently disabled, " + "attempting to enable.\n"); mchbar_phys |= 0x1; pci_write_long(nb, 0x48, mchbar_phys); - if(pci_read_long(nb, 0x48) & 1) + if(pci_read_long(nb, 0x48) & 1) printf("Enabled successfully.\n"); else printf("Enable FAILED!\n"); } mchbar_phys &= 0xfffffffe; - mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; - break; + mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; + break; case PCI_DEVICE_ID_INTEL_82443LX: case PCI_DEVICE_ID_INTEL_82443BX: case PCI_DEVICE_ID_INTEL_82810: - case PCI_DEVICE_ID_INTEL_82810E_MC: - case PCI_DEVICE_ID_INTEL_82810DC: + case PCI_DEVICE_ID_INTEL_82810E_DC: + case PCI_DEVICE_ID_INTEL_82810_DC: case PCI_DEVICE_ID_INTEL_82830M: printf("This northbridge does not have MCHBAR.\n"); return 1; - case PCI_DEVICE_ID_INTEL_GS45: - case PCI_DEVICE_ID_INTEL_X44: + case PCI_DEVICE_ID_INTEL_82X4X: + case PCI_DEVICE_ID_INTEL_82X38: case PCI_DEVICE_ID_INTEL_32X0: mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe; mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; - break; - case PCI_DEVICE_ID_INTEL_HM65E: - mchbar_phys = pci_read_long(nb, 0x48) & 0xffff8000; + break; + case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN: + mchbar_phys = pci_read_long(nb, 0x48); + mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; + mchbar_phys &= 0x0000000fffffc000UL; /* 35:14 */ + mch_registers = NULL; /* No public documentation */ + break; + case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN: mch_registers = sandybridge_mch_registers; size = ARRAY_SIZE(sandybridge_mch_registers); + case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN: /* pretty printing not implemented yet */ + mchbar_phys = pci_read_long(nb, 0x48); + mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; + mchbar_phys &= 0x0000007fffff8000UL; /* 38:15 */ break; default: printf("Error: Dumping MCHBAR on this northbridge is not (yet) supported.\n"); @@ -183,28 +192,29 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc) printf("MCHBAR = 0x%08" PRIx64 " (MEM)\n\n", mchbar_phys); if (mch_registers != NULL) { + printf("%d registers:\n", size); for (i = 0; i < size; i++) { switch (mch_registers[i].size) { case 8: - printf("mchbase+0x%04x: 0x%08lx (%s)\n", + printf("mchbase+0x%04x: 0x%016lx (%s)\n", mch_registers[i].addr, *(uint64_t *)(mchbar+mch_registers[i].addr), mch_registers[i].name); break; case 4: - printf("mchbase+0x%04x: 0x%08x (%s)\n", + printf("mchbase+0x%04x: 0x%08x (%s)\n", mch_registers[i].addr, *(uint32_t *)(mchbar+mch_registers[i].addr), mch_registers[i].name); break; case 2: - printf("mchbase+0x%04x: 0x%04x (%s)\n", + printf("mchbase+0x%04x: 0x%04x (%s)\n", mch_registers[i].addr, *(uint16_t *)(mchbar+mch_registers[i].addr), mch_registers[i].name); break; case 1: - printf("mchbase+0x%04x: 0x%02x (%s)\n", + printf("mchbase+0x%04x: 0x%02x (%s)\n", mch_registers[i].addr, *(uint8_t *)(mchbar+mch_registers[i].addr), mch_registers[i].name); diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c index a7429a0..e454f44 100644 --- a/util/inteltool/pcie.c +++ b/util/inteltool/pcie.c @@ -94,22 +94,22 @@ int print_epbar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_82975X: epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; break; - case PCI_DEVICE_ID_INTEL_PM965: - case PCI_DEVICE_ID_INTEL_Q965: - case PCI_DEVICE_ID_INTEL_82Q35: - case PCI_DEVICE_ID_INTEL_82G33: - case PCI_DEVICE_ID_INTEL_82Q33: - case PCI_DEVICE_ID_INTEL_X44: + case PCI_DEVICE_ID_INTEL_82965PM: + case PCI_DEVICE_ID_INTEL_82Q965: + case PCI_DEVICE_ID_INTEL_82Q35: + case PCI_DEVICE_ID_INTEL_82G33: + case PCI_DEVICE_ID_INTEL_82Q33: + case PCI_DEVICE_ID_INTEL_82X38: case PCI_DEVICE_ID_INTEL_32X0: - case PCI_DEVICE_ID_INTEL_GS45: + case PCI_DEVICE_ID_INTEL_82X4X: case PCI_DEVICE_ID_INTEL_ATOM_DXXX: case PCI_DEVICE_ID_INTEL_ATOM_NXXX: - epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; - epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32; - break; + epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; + epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32; + break; case PCI_DEVICE_ID_INTEL_82810: - case PCI_DEVICE_ID_INTEL_82810DC: - case PCI_DEVICE_ID_INTEL_82810E_MC: + case PCI_DEVICE_ID_INTEL_82810_DC: + case PCI_DEVICE_ID_INTEL_82810E_DC: case PCI_DEVICE_ID_INTEL_82830M: case PCI_DEVICE_ID_INTEL_82865: printf("This northbridge does not have EPBAR.\n"); @@ -156,32 +156,41 @@ int print_dmibar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_82975X: dmibar_phys = pci_read_long(nb, 0x4c) & 0xfffffffe; break; - case PCI_DEVICE_ID_INTEL_PM965: - case PCI_DEVICE_ID_INTEL_Q965: + case PCI_DEVICE_ID_INTEL_82965PM: + case PCI_DEVICE_ID_INTEL_82Q965: case PCI_DEVICE_ID_INTEL_82Q35: case PCI_DEVICE_ID_INTEL_82G33: case PCI_DEVICE_ID_INTEL_82Q33: - case PCI_DEVICE_ID_INTEL_X44: + case PCI_DEVICE_ID_INTEL_82X38: case PCI_DEVICE_ID_INTEL_32X0: - case PCI_DEVICE_ID_INTEL_GS45: + case PCI_DEVICE_ID_INTEL_82X4X: case PCI_DEVICE_ID_INTEL_ATOM_DXXX: case PCI_DEVICE_ID_INTEL_ATOM_NXXX: dmibar_phys = pci_read_long(nb, 0x68) & 0xfffffffe; dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32; break; case PCI_DEVICE_ID_INTEL_82810: - case PCI_DEVICE_ID_INTEL_82810DC: - case PCI_DEVICE_ID_INTEL_82810E_MC: + case PCI_DEVICE_ID_INTEL_82810_DC: + case PCI_DEVICE_ID_INTEL_82810E_DC: case PCI_DEVICE_ID_INTEL_82865: printf("This northbridge does not have DMIBAR.\n"); return 1; - case PCI_DEVICE_ID_INTEL_X58: + case PCI_DEVICE_ID_INTEL_82X58: dmibar_phys = pci_read_long(nb, 0x50) & 0xfffff000; break; - case PCI_DEVICE_ID_INTEL_HM65E: - dmibar_phys = pci_read_long(nb, 0x68) & 0xfffff000; + case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN: + dmibar_phys = pci_read_long(nb, 0x68); + dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32; + dmibar_phys &= 0x0000000ffffff000UL; /* 35:12 */ + dmi_registers = NULL; /* No public documentation */ + break; + case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN: dmi_registers = sandybridge_dmi_registers; size = ARRAY_SIZE(sandybridge_dmi_registers); + case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN: /* pretty printing not implemented yet */ + dmibar_phys = pci_read_long(nb, 0x68); + dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32; + dmibar_phys &= 0x0000007ffffff000UL; /* 38:12 */ break; default: printf("Error: Dumping DMIBAR on this northbridge is not (yet) supported.\n"); @@ -251,22 +260,22 @@ int print_pciexbar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_82975X: pciexbar_reg = pci_read_long(nb, 0x48); break; - case PCI_DEVICE_ID_INTEL_PM965: - case PCI_DEVICE_ID_INTEL_Q965: - case PCI_DEVICE_ID_INTEL_82Q35: - case PCI_DEVICE_ID_INTEL_82G33: - case PCI_DEVICE_ID_INTEL_82Q33: - case PCI_DEVICE_ID_INTEL_X44: + case PCI_DEVICE_ID_INTEL_82965PM: + case PCI_DEVICE_ID_INTEL_82Q965: + case PCI_DEVICE_ID_INTEL_82Q35: + case PCI_DEVICE_ID_INTEL_82G33: + case PCI_DEVICE_ID_INTEL_82Q33: + case PCI_DEVICE_ID_INTEL_82X38: case PCI_DEVICE_ID_INTEL_32X0: - case PCI_DEVICE_ID_INTEL_GS45: + case PCI_DEVICE_ID_INTEL_82X4X: case PCI_DEVICE_ID_INTEL_ATOM_DXXX: case PCI_DEVICE_ID_INTEL_ATOM_NXXX: - pciexbar_reg = pci_read_long(nb, 0x60); - pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32; - break; + pciexbar_reg = pci_read_long(nb, 0x60); + pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32; + break; case PCI_DEVICE_ID_INTEL_82810: - case PCI_DEVICE_ID_INTEL_82810DC: - case PCI_DEVICE_ID_INTEL_82810E_MC: + case PCI_DEVICE_ID_INTEL_82810_DC: + case PCI_DEVICE_ID_INTEL_82810E_DC: case PCI_DEVICE_ID_INTEL_82865: printf("Error: This northbridge does not have PCIEXBAR.\n"); return 1;

1 0

Patch set updated for coreboot: 1771098 inteltool: fix Makefile
by Stefan Tauner 12 Oct '12

12 Oct '12

Stefan Tauner (stefan.tauner(a)gmx.at) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1573 -gerrit commit 1771098e2837083f3ecf5d0263ff567ccb223a3d Author: Stefan Tauner <stefan.tauner(a)gmx.at> Date: Fri Oct 12 10:36:49 2012 +0200 inteltool: fix Makefile Note the changed redirection in the CC call. &> is a bashism to redirect both streams (stdout and stderr), but with other shells this introduces a race condition with the rm command afterwards, because the compiler execution is done in the background/in parallel. This patch also adds the verbatim variable method to define and export test code and the actual libpci test as it is used in flashrom. Change-Id: I08516494828c9f7af168f954f2df027372657867 Signed-off-by: Stefan Tauner <stefan.tauner(a)gmx.at> --- util/inteltool/Makefile | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/util/inteltool/Makefile b/util/inteltool/Makefile index d754005..6c94460 100644 --- a/util/inteltool/Makefile +++ b/util/inteltool/Makefile @@ -53,13 +53,25 @@ distclean: clean dep: @$(CC) $(CFLAGS) -MM *.c > .dependencies +define LIBPCI_TEST +/* Avoid a failing test due to libpci header symbol shadowing breakage */ +#define index shadow_workaround_index +#include <pci/pci.h> +struct pci_access *pacc; +int main(int argc, char **argv) +{ + (void) argc; + (void) argv; + pacc = pci_alloc(); + return 0; +} +endef +export LIBPCI_TEST + pciutils: @printf "\nChecking for pciutils and zlib... " - @$(shell ( printf "#include <pci/pci.h>\n"; \ - printf "struct pci_access *pacc;\n"; \ - printf "int main(int argc, char **argv)\n"; \ - printf "{ pacc = pci_alloc(); return 0; }\n"; ) > .test.c ) - @$(CC) $(CFLAGS) .test.c -o .test $(LDFLAGS) &>/dev/null && \ + @echo "$$LIBPCI_TEST" > .test.c + @$(CC) $(CFLAGS) .test.c -o .test $(LDFLAGS) >/dev/null 2>&1 && \ printf "found.\n" || ( printf "not found.\n\n"; \ printf "Please install pciutils-devel and zlib-devel.\n"; \ printf "See README for more information.\n\n"; \

1 0

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coreboot October 2012