coreboot October 2012

coreboot@coreboot.org

34 participants
312 discussions

New patch to review for coreboot: e045c00 lenovo/t60 lenovo/x60: Override SMBIOS vendor name to all upper case
by Peter Stuge 04 Oct '12

04 Oct '12

Peter Stuge (peter(a)stuge.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1557 -gerrit commit e045c0099dc92929935fbe5e1cae2c2cf14e3258 Author: Peter Stuge <peter(a)stuge.se> Date: Thu Oct 4 21:25:18 2012 +0200 lenovo/t60 lenovo/x60: Override SMBIOS vendor name to all upper case This allows the Linux thinkpad_acpi.ko module understand that a ThinkPad is a ThinkPad also when it runs coreboot. Change-Id: I85c948b9a772ac878708d72012e522e87c49c2b2 Signed-off-by: Peter Stuge <peter(a)stuge.se> --- src/mainboard/lenovo/t60/Kconfig | 4 ++++ src/mainboard/lenovo/x60/Kconfig | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig index 062a459..6f86394 100644 --- a/src/mainboard/lenovo/t60/Kconfig +++ b/src/mainboard/lenovo/t60/Kconfig @@ -40,6 +40,10 @@ config MAINBOARD_PART_NUMBER string default "ThinkPad T60 / T60p" +config MAINBOARD_SMBIOS_VENDOR + string + default "LENOVO" + config MMCONF_BASE_ADDRESS hex default 0xf0000000 diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index e77fac6..928fbf7 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -42,6 +42,10 @@ config MAINBOARD_PART_NUMBER string default "ThinkPad X60 / X60s" +config MAINBOARD_SMBIOS_VENDOR + string + default "LENOVO" + config MMCONF_BASE_ADDRESS hex default 0xf0000000

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New patch to review for coreboot: 4807892 Allow mainboard vendor name and part number override in SMBIOS tables
by Peter Stuge 04 Oct '12

04 Oct '12

Peter Stuge (peter(a)stuge.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1556 -gerrit commit 4807892bfcd8f4562d0abd0a43cef28f625625d8 Author: Peter Stuge <peter(a)stuge.se> Date: Thu Oct 4 21:18:13 2012 +0200 Allow mainboard vendor name and part number override in SMBIOS tables Change-Id: I0dfe38b9f6f99b3376f1547412ecc97c2f7aff2b Signed-off-by: Peter Stuge <peter(a)stuge.se> --- src/arch/x86/boot/smbios.c | 6 +++--- src/mainboard/Kconfig | 13 +++++++++++++ 2 files changed, 16 insertions(+), 3 deletions(-) diff --git a/src/arch/x86/boot/smbios.c b/src/arch/x86/boot/smbios.c index 8877f60..209c14f 100644 --- a/src/arch/x86/boot/smbios.c +++ b/src/arch/x86/boot/smbios.c @@ -182,8 +182,8 @@ static int smbios_write_type1(unsigned long *current, int handle) t->type = SMBIOS_SYSTEM_INFORMATION; t->handle = handle; t->length = len - 2; - t->manufacturer = smbios_add_string(t->eos, CONFIG_MAINBOARD_VENDOR); - t->product_name = smbios_add_string(t->eos, CONFIG_MAINBOARD_PART_NUMBER); + t->manufacturer = smbios_add_string(t->eos, CONFIG_MAINBOARD_SMBIOS_VENDOR); + t->product_name = smbios_add_string(t->eos, CONFIG_MAINBOARD_SMBIOS_PART_NUMBER); t->serial_number = smbios_add_string(t->eos, smbios_mainboard_serial_number()); t->version = smbios_add_string(t->eos, smbios_mainboard_version()); len = t->length + smbios_string_table_len(t->eos); @@ -200,7 +200,7 @@ static int smbios_write_type3(unsigned long *current, int handle) t->type = SMBIOS_SYSTEM_ENCLOSURE; t->handle = handle; t->length = len - 2; - t->manufacturer = smbios_add_string(t->eos, CONFIG_MAINBOARD_VENDOR); + t->manufacturer = smbios_add_string(t->eos, CONFIG_MAINBOARD_SMBIOS_VENDOR); t->bootup_state = SMBIOS_STATE_SAFE; t->power_supply_state = SMBIOS_STATE_SAFE; t->thermal_state = SMBIOS_STATE_SAFE; diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index 779e061..520f2f4 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -339,4 +339,17 @@ config MAINBOARD_VERSION default "1.0" help Define the used version number which will be used by SMBIOS tables. + +config MAINBOARD_SMBIOS_VENDOR + string "BIOS table vendor string" + default MAINBOARD_VENDOR + help + Override the default mainboard vendor string used by SMBIOS tables. + +config MAINBOARD_SMBIOS_PART_NUMBER + string "BIOS table vendor string" + default MAINBOARD_PART_NUMBER + help + Override the default mainboard part number string used by SMBIOS tables. + endmenu

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i915tool
by Denis 'GNUtoo' Carikli 04 Oct '12

04 Oct '12

Hi, I had some difficulties getting started with the i915tool: first I did that: export LINUX=/home/gnutoo/x86/linux-libre/linux-3.0.0 I installed that PPA: https://launchpad.net/~npalix/+archive/coccinelle and coccinelle. Then I created the following directories(and deleted the files with the same name if any): inputs/ per-file-changes/ final/ tmp/ then I made plusplusplus executable and then I ran transform like that: sh transform Then I ran make which ended with: final/intel_bios.c:123:5: error: ‘uint8_t’ undeclared (first use in this function) I patched intel_bios.c by adding #include <stdint.h> on top of the file... Then I ran make again and I've that: final/intel_bios.c:594:24: error: ‘intel_no_opregion_vbt’ undeclared (first use in this function) I'll continue to try to make it "work" (not sure if it does work at all since you have to "make broken" according to the git commit). However I see that you have a much updated version according to a comment in http://review.coreboot.org/#/c/1003/ Denis.

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Patch merged into coreboot/master: e0449bb add tyan s8226: add a new mainboard
by gerrit＠coreboot.org 04 Oct '12

04 Oct '12

the following patch was just integrated into master: commit e0449bb3914a7e8751f7966677d8a4f37f680d5e Author: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> Date: Fri Sep 7 19:20:02 2012 +0800 add tyan s8226: add a new mainboard our code supports tyan s8226 now, which has two cpus on the board the cpu socket is C32. The details of tyan s8226 is: http://www.tyan.com/product_SKU_spec.aspx?ProductType=MB&pid=679&SKU=600000… the test result of this mainboard is: 1) boot Ubunbu 11.10, kernel 3.0.9. there is no err and warnings in dmesg. 2) boot windows7 x64 successfully. 3) use fwts to test the bios, there are 268 pass and 14 failed 4) pcie and usb slots are ok. 5) all network interfaces are ok. Change-Id: I7d8534f20b4f3c16322a5c5ba2e3fba4b4f3e608 Signed-off-by: Siyuan Wang <SiYuan.Wang(a)amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> Build-Tested: build bot (Jenkins) at Fri Sep 14 10:07:15 2012, giving +1 Reviewed-By: Marc Jones <marcj303(a)gmail.com> at Tue Oct 2 23:41:02 2012, giving +2 See http://review.coreboot.org/1495 for details. -gerrit

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Reading resources failed on MS-6159
by christian.suehs＠online.de 04 Oct '12

04 Oct '12

Hello, a few months ago, i tried to get work a MSI Motherboard with coreboot. It is a MS-6159 with i440lx northbridge and onboard Ati VGA adapted to the AGP-Bus Now I start again with the same trouble as before :( After many changes for RAM configuration and other NB registers which don't work or comes up with the same result. I think that writing to the PCI Configuration failed by enumerating the buses and a hard reset follows Datasheet says that 0xCF8 have to access by DWORD, if not the call is bypassed to CPU IO and there 0xCF9 inits a hard reset. Could that be the problem? I have enabled the tracing and get this at last lines: /home/chris/coreboot/src/devices/pci_device.c:102 calls /home/chris/coreboot/src/devices/pci_ops.c:100 /home/chris/coreboot/src/devices/pci_ops.c:101 calls /home/chris/coreboot/src/devices/pci_ops.c:33 /home/chris/coreboot/src/devices/pci_ops.c:41 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:57 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:57 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:57 this is a pci_conf1_write_config32 call for 3 months it was a pci_conf1_write_config8 call and the mobo resets no idea what I have changed. I have also hardcoded many registers near lspci output from factory bios with no sucess Also change the aperture size to 64MB the current coreboot code for i44olx can't do this because of a failure. Is there anybody who have get work a mobo with i440lx northbridge? How can I easily debug the pci enumerating stuff of coreboot. Why are there 3 calls to PCI there is no loop in the code? Thanks for any hints chris

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Re: [coreboot] [SeaBIOS] VideoBios question
by Kevin O'Connor 04 Oct '12

04 Oct '12

On Wed, Oct 03, 2012 at 04:16:59PM +0200, Christian Gmeiner wrote: > Hi all. > > As you may noticed I am working on the SeaVideoBios (Geode part). And > I am running into > a simple question: > > What is the default state/video mode the VideoBios should enter > during/after init? > > In general I need to set the wanted mode via int10 AH=00h > Would it be okay to have no mode set during init and trust that the > mode is set before > using it? SeaBIOS will always set the mode (to AH=03h) immiediately after initializing the vgabios. I've observed this behaviour in other off the shelf BIOS implementation as well. -Kevin

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Patch merged into coreboot/master: f2bb3c7 lint: Stop searching when one GNUmake is found
by gerrit＠coreboot.org 04 Oct '12

04 Oct '12

the following patch was just integrated into master: commit f2bb3c7142612b41919f999974d1352309bcf8e5 Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Fri Sep 28 20:13:19 2012 +0800 lint: Stop searching when one GNUmake is found After make 3.81 is copied to /usr/local/bin, the old make 3.80, which doesn't work for coreboot, will replace $MAKE with gnumake. That is not we want. Change-Id: I87fbe95c70228a22f2c233ff071df29639b63726 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Thu Oct 4 11:02:02 2012, giving +2 See http://review.coreboot.org/1550 for details. -gerrit

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Patch merged into coreboot/master: 95acbc4 pirq_routing: Allow routing with more than 4 PIRQ links
by gerrit＠coreboot.org 04 Oct '12

04 Oct '12

the following patch was just integrated into master: commit 95acbc47a70d04d13f1165fdb89a6f54fc06d90e Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Thu Aug 23 02:32:58 2012 -0500 pirq_routing: Allow routing with more than 4 PIRQ links pirq_routing_irqs assumed that only four links are available for PIRQ routing, INTA to INTD. Some chipsets provide more, up to INTH. When pirq_routing_irqs found a link number greater than 4 in the pirq table, it would not assign that IRQ. This is a shame, as it limits the flexibility of routing IRQs. Make the maximum number of links a Kconfig variable, and modify the code to respect it. This works beatifully on the VX900, which provides 8 routable interrupts. While we're at it, also refactor pirq_routing_irqs, and add some much needed comments. Rename pirq_routing_irqs to pirq_route_irqs to demistify the role of this function. The copyrights added were determined from git log filename. Change-Id: I4b565315404c65b871406f616474e2cc9e6e013e Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Build-Tested: build bot (Jenkins) at Thu Oct 4 04:26:30 2012, giving +1 Reviewed-By: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> at Thu Oct 4 04:27:29 2012, giving +2 See http://review.coreboot.org/1482 for details. -gerrit

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Patch set updated for coreboot: 95acbc4 pirq_routing: Allow routing with more than 4 PIRQ links
by Alexandru Gagniuc 04 Oct '12

04 Oct '12

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1482 -gerrit commit 95acbc47a70d04d13f1165fdb89a6f54fc06d90e Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Thu Aug 23 02:32:58 2012 -0500 pirq_routing: Allow routing with more than 4 PIRQ links pirq_routing_irqs assumed that only four links are available for PIRQ routing, INTA to INTD. Some chipsets provide more, up to INTH. When pirq_routing_irqs found a link number greater than 4 in the pirq table, it would not assign that IRQ. This is a shame, as it limits the flexibility of routing IRQs. Make the maximum number of links a Kconfig variable, and modify the code to respect it. This works beatifully on the VX900, which provides 8 routable interrupts. While we're at it, also refactor pirq_routing_irqs, and add some much needed comments. Rename pirq_routing_irqs to pirq_route_irqs to demistify the role of this function. The copyrights added were determined from git log filename. Change-Id: I4b565315404c65b871406f616474e2cc9e6e013e Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/Kconfig | 12 ++++ src/arch/x86/boot/pirq_routing.c | 98 ++++++++++++++++++++++---------- src/arch/x86/include/arch/pirq_routing.h | 35 +++++++++++- 3 files changed, 112 insertions(+), 33 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 469266d..e0062dd 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1,6 +1,7 @@ ## ## This file is part of the coreboot project. ## +## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> ## Copyright (C) 2009-2010 coresystems GmbH ## ## This program is free software; you can redistribute it and/or modify @@ -374,6 +375,17 @@ config HAVE_PIRQ_TABLE Whether or not the PIRQ table is actually generated by coreboot is configurable by the user via GENERATE_PIRQ_TABLE. +config MAX_PIRQ_LINKS + int + default 4 + help + This variable specifies the number of PIRQ interrupt links which are + routable. On most chipsets, this is 4, INTA through INTD. Some + chipsets offer more than four links, commonly up to INTH. They may + also have a separate link for ATA or IOAPIC interrupts. When the PIRQ + table specifies links greater than 4, pirq_route_irqs will not + function properly, unless this variable is correctly set. + #These Options are here to avoid "undefined" warnings. #The actual selection and help texts are in the following menu. diff --git a/src/arch/x86/boot/pirq_routing.c b/src/arch/x86/boot/pirq_routing.c index bb8a7b6..357500c 100644 --- a/src/arch/x86/boot/pirq_routing.c +++ b/src/arch/x86/boot/pirq_routing.c @@ -1,3 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Copyright (C) 2010 Stefan Reinauer <stepan(a)coreboot.org> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ #include <console/console.h> #include <arch/pirq_routing.h> #include <string.h> @@ -92,18 +111,50 @@ unsigned long copy_pirq_routing_table(unsigned long addr) #if CONFIG_DEBUG_PIRQ verify_copy_pirq_routing_table(addr); #endif - pirq_routing_irqs(addr); + pirq_route_irqs(addr); return addr + intel_irq_routing_table.size; } #if CONFIG_PIRQ_ROUTE -void pirq_routing_irqs(unsigned long addr) +static u8 pirq_get_next_free_irq(u8* pirq, u16 bitmap) { - int i, j, k, num_entries; - unsigned char irq_slot[4]; - unsigned char pirq[4] = {0, 0, 0, 0}; + int i, link; + u8 irq = 0; + for (i = 2; i <= 15; i++) + { + /* Can we assign this IRQ ? */ + if (!((bitmap >> i) & 1)) + continue; + /* We can, Now let's assume we can use this IRQ */ + irq = i; + /* And assume we have not yet routed it */ + int already_routed = 0; + /* Have we already routed it ? */ + for(link = 0; link < CONFIG_MAX_PIRQ_LINKS; link++) { + if (pirq[link] == irq) { + already_routed = 1; + break; + } + } + /* If it's not yet routed, use it */ + if(!already_routed) + break; + /* But if it was already routed, try the next one */ + continue; + } + /* Now we got our IRQ */ + return irq; +} + +void pirq_route_irqs(unsigned long addr) +{ + int i, intx, num_entries; + unsigned char irq_slot[MAX_INTX_ENTRIES]; + unsigned char pirq[CONFIG_MAX_PIRQ_LINKS]; struct irq_routing_table *pirq_tbl; + memset(pirq, 0, CONFIG_MAX_PIRQ_LINKS); + pirq_tbl = (struct irq_routing_table *)(addr); num_entries = (pirq_tbl->size - 32) / 16; @@ -113,37 +164,26 @@ void pirq_routing_irqs(unsigned long addr) printk(BIOS_DEBUG, "PIRQ Entry %d Dev/Fn: %X Slot: %d\n", i, pirq_tbl->slots[i].devfn >> 3, pirq_tbl->slots[i].slot); - for (j = 0; j < 4; j++) { + for (intx = 0; intx < MAX_INTX_ENTRIES; intx++) { - int link = pirq_tbl->slots[i].irq[j].link; - int bitmap = pirq_tbl->slots[i].irq[j].bitmap; + int link = pirq_tbl->slots[i].irq[intx].link; + int bitmap = pirq_tbl->slots[i].irq[intx].bitmap; int irq = 0; printk(BIOS_DEBUG, "INT: %c link: %x bitmap: %x ", - 'A' + j, link, bitmap); + 'A' + intx, link, bitmap); - if (!bitmap|| !link || link > 4) { + if (!bitmap|| !link || link > CONFIG_MAX_PIRQ_LINKS) { printk(BIOS_DEBUG, "not routed\n"); - irq_slot[j] = irq; + irq_slot[intx] = irq; continue; } /* yet not routed */ - if (!pirq[link - 1]) { - - for (k = 2; k <= 15; k++) { - - if (!((bitmap >> k) & 1)) - continue; - - irq = k; - - /* yet not routed */ - if (pirq[0] != irq && pirq[1] != irq && pirq[2] != irq && pirq[3] != irq) - break; - } - + if (!pirq[link - 1]) + { + irq = pirq_get_next_free_irq(pirq, bitmap); if (irq) pirq[link - 1] = irq; } @@ -151,7 +191,7 @@ void pirq_routing_irqs(unsigned long addr) irq = pirq[link - 1]; printk(BIOS_DEBUG, "IRQ: %d\n", irq); - irq_slot[j] = irq; + irq_slot[intx] = irq; } /* Bus, device, slots IRQs for {A,B,C,D}. */ @@ -159,10 +199,8 @@ void pirq_routing_irqs(unsigned long addr) pirq_tbl->slots[i].devfn >> 3, irq_slot); } - printk(BIOS_DEBUG, "PIRQ1: %d\n", pirq[0]); - printk(BIOS_DEBUG, "PIRQ2: %d\n", pirq[1]); - printk(BIOS_DEBUG, "PIRQ3: %d\n", pirq[2]); - printk(BIOS_DEBUG, "PIRQ4: %d\n", pirq[3]); + for(i = 0; i < CONFIG_MAX_PIRQ_LINKS; i++) + printk(BIOS_DEBUG, "PIRQ%c: %d\n", i + 'A', pirq[i]); pirq_assign_irqs(pirq); } diff --git a/src/arch/x86/include/arch/pirq_routing.h b/src/arch/x86/include/arch/pirq_routing.h index 08ba535..c5be5f4 100644 --- a/src/arch/x86/include/arch/pirq_routing.h +++ b/src/arch/x86/include/arch/pirq_routing.h @@ -1,6 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Copyright (C) 2012 Patrick Georgi <patrick(a)georgi-clan.de> + * Copyright (C) 2010 Stefan Reinauer <stepan(a)coreboot.org> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ #ifndef ARCH_PIRQ_ROUTING_H #define ARCH_PIRQ_ROUTING_H +/* This is the maximum number on interrupt entries that a PCI device may have. + * This is NOT the number of slots or devices in the system + * This is NOT the number of entries in the PIRQ table + * This tells us that in the PIRQ table, we are going to have 4 link-bitmap + * entries per PCI device + * It is fixed at 4: INTA, INTB, INTC, and INTD + * CAUTION: If you change this, pirq_routing will not work correctly*/ +#define MAX_INTX_ENTRIES 4 + #if CONFIG_GENERATE_PIRQ_TABLE #include <stdint.h> @@ -40,10 +69,10 @@ unsigned long copy_pirq_routing_table(unsigned long start); unsigned long write_pirq_routing_table(unsigned long start); #if CONFIG_PIRQ_ROUTE -void pirq_routing_irqs(unsigned long start); -void pirq_assign_irqs(const unsigned char pIntAtoD[4]); +void pirq_route_irqs(unsigned long start); +void pirq_assign_irqs(const unsigned char pirq[CONFIG_MAX_PIRQ_LINKS]); #else -#define pirq_routing_irqs(start) {} +#define pirq_route_irqs(start) {} #endif #else

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Google I/O Chromebox
by Chris Bobrowitz 03 Oct '12

03 Oct '12

Hello! I was at Google I/O this past summer and have finally had time to sit down with the chromebox. My version has the Intel i5 processor and am looking to flash a custom BIOS for the reason of flashing linux to the machine. What is the current supported version of coreboot or is this even possible. Sincerely, Chris -- *Chris Bobrowitz* FCB IT Help-Desk Technician FCB Information Technology Dpt.

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coreboot October 2012