coreboot January 2011

coreboot@coreboot.org

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299 discussions

[PATCH]Remove warnings in nvramtool
by Patrick Georgi 14 Jan '11

14 Jan '11

Hi, there are some strict aliasing related warnings in nvramtool. This patch fixes them. Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com>

2 1

[patch] AMD MCT DDR3 for register DIMMs
by Bao, Zheng 14 Jan '11

14 Jan '11

The code is tested on my board with register DIMMs. More tests need to be done. Please send the testing report. Note: The pDCTstat->PresetmaxFreq in mctGet_MaxLoadFreq() should be set to a higher limit, otherwise the frequnce will be set as 400MHz. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Index: src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c =================================================================== --- src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c (revision 6244) +++ src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c (working copy) @@ -86,7 +86,7 @@ procConifg(pMCTData,pDCTData, dimm, pass); /* 5. Begin write levelization training: * Program F2x[1, 0]9C_x08[WrtLevelTrEn]=1. */ - if (pDCTData->LogicalCPUID & AMD_DR_Cx) + if (pDCTData->LogicalCPUID & (AMD_DR_Cx | AMD_DR_Dx)) set_DCT_ADDR_Bits(pDCTData, pDCTData->DctTrain, pDCTData->NodeId, FUN_DCT, DRAM_ADD_DCT_PHY_CONTROL_REG, WrtLvTrEn, WrtLvTrEn, 1); else @@ -656,9 +656,9 @@ programODT(pMCTData, pDCTData, dimm); /* Program F2x[1,0]9C_x08[WrLvOdtEn]=1 */ - if (pDCTData->LogicalCPUID & AMD_DR_Cx) + if (pDCTData->LogicalCPUID & (AMD_DR_Cx | AMD_DR_Dx)) set_DCT_ADDR_Bits(pDCTData, pDCTData->DctTrain, pDCTData->NodeId, FUN_DCT, - DRAM_ADD_DCT_PHY_CONTROL_REG, WrLvOdtEn, WrLvOdtEn,(u32) 1); + DRAM_ADD_DCT_PHY_CONTROL_REG, WrLvOdtEn, WrLvOdtEn, (u32)1); else { /* Program WrLvOdtEn=1 through set bit 12 of D3CSODT reg offset 0 for Rev.B*/ @@ -722,7 +722,36 @@ pDCTData->WLFineDelay[MAX_BYTE_LANES*dimm+ByteLane] = Seed_Fine; ByteLane++; } + } else if (pDCTData->Status[DCT_STATUS_REGISTERED]) { /* For Pass 2 */ + /* From BKDG, Write Leveling Seed Value. */ + /* TODO: The unbuffered DIMMs are unstable on the code below. So temporarily it is + * only for registered DIMMs. */ + u32 RegisterDelay, SeedTotal; + u8 MemClkFreq; + u16 freq_tab[] = {400, 533, 667, 800}; + while(ByteLane < MAX_BYTE_LANES) + { + MemClkFreq = get_Bits(pDCTData, pDCTData->CurrDct, pDCTData->NodeId, + FUN_DCT, DRAM_CONFIG_HIGH, 0, 2); + if (pDCTData->Status[DCT_STATUS_REGISTERED]) + RegisterDelay = 0x20; /* TODO: ((RCW2 & BIT0) == 0) ? 0x20 : 0x30; */ + else + RegisterDelay = 0; + SeedTotal = (pDCTData->WLFineDelay[MAX_BYTE_LANES*dimm+ByteLane] & 0x1F) | + pDCTData->WLGrossDelay[MAX_BYTE_LANES*dimm+ByteLane] << 5; + /* SeedTotalPreScaling = (the total delay value in F2x[1, 0]9C_x[4A:30] from pass 1 of write levelization + training) - RegisterDelay. */ + /* MemClkFreq: 3: 400Mhz; 4: 533Mhz; 5: 667Mhz; 6: 800Mhz */ + SeedTotal = (u16) (RegisterDelay + ((((u32) SeedTotal - RegisterDelay) * + freq_tab[MemClkFreq-3]) / 400)); + Seed_Gross = (SeedTotal & 0x20) != 0 ? 1 : 2; + Seed_Fine = SeedTotal & 0x1F; + pDCTData->WLGrossDelay[MAX_BYTE_LANES*dimm+ByteLane] = Seed_Gross; + pDCTData->WLFineDelay[MAX_BYTE_LANES*dimm+ByteLane] = Seed_Fine; + ByteLane ++; + } } + setWLByteDelay(pDCTData, ByteLane, dimm, 0); } Index: src/northbridge/amd/amdmct/mct_ddr3/mctwl.c =================================================================== --- src/northbridge/amd/amdmct/mct_ddr3/mctwl.c (revision 6246) +++ src/northbridge/amd/amdmct/mct_ddr3/mctwl.c (working copy) @@ -342,7 +342,21 @@ mct_Wait(250); if (pDCTstat->Status & (1 << SB_Registered)) { - /* TODO: Assuming the dct==0. The agesa here is confusing. */ + u8 DCT0Present, DCT1Present; + + DCT0Present = pDCTstat->DIMMValidDCT[0]; + if (pDCTstat->GangedMode) + DCT1Present = 0; + else + DCT1Present = pDCTstat->DIMMValidDCT[1]; + + if (!DCT1Present) + pDCTstat->CSPresent = pDCTstat->CSPresent_DCT[0]; + else if (pDCTstat->GangedMode) { + pDCTstat->CSPresent = 0; + } else + pDCTstat->CSPresent = pDCTstat->CSPresent_DCT[1]; + FreqChgCtrlWrd(pMCTstat, pDCTstat); } }

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[PATCH]Improve YABEL compatibility
by Patrick Georgi 14 Jan '11

14 Jan '11

Hi, attached patch improves compatibility of YABEL with realmode execution of the VGA BIOS by passing through access to IVT, BDA and option ROM area directly, instead of copying them from the emulated memory to real memory after initialization is done. Some VGA BIOSes seem to map hardware registers into the option ROM area, so routing accesses to these into emulated RAM will lead to all kinds of unexpected behaviour. The intent of YABEL in coreboot is to provide improved security by isolating hardware access - this patch doesn't improve or degrade security as the memory regions in question were already copied back after emulation before this patch. Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com>

3 2

build service results for r6255
by repository service 14 Jan '11

14 Jan '11

Dear coreboot readers! This is the automatic build system of coreboot. The developer "oxygene" checked in revision 6255 to the coreboot repository. This caused the following changes: Change Log: Disable CMOS recovery code for ROMCC boards as the CBFS code used for that feature is not ROMCC compatible. Fixes build errors introduced in r6253. Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Acked-by: Patrick Georgi <patrick.georgi(a)secunet.com> Build Log: Compilation of advantech:pcm-5820 has been fixed Compilation of asi:mb_5blgp has been fixed Compilation of asi:mb_5blmp has been fixed Compilation of axus:tc320 has been fixed Compilation of bcom:winnet100 has been fixed Compilation of dell:s1850 has been fixed Compilation of digitallogic:msm586seg has been fixed Compilation of eaglelion:5bcm has been fixed Compilation of emulation:qemu-x86 has been fixed Compilation of iei:juki-511p has been fixed Compilation of iei:nova4899r has been fixed Compilation of intel:jarrell has been fixed Compilation of intel:truxton has been fixed Compilation of intel:xe7501devkit has been fixed Compilation of supermicro:x6dai_g has been fixed Compilation of supermicro:x6dhe_g has been fixed Compilation of supermicro:x6dhe_g2 has been fixed Compilation of supermicro:x6dhr_ig has been fixed Compilation of supermicro:x6dhr_ig2 has been fixed Compilation of technologic:ts5300 has been fixed Compilation of televideo:tc7020 has been fixed Compilation of via:epia has been fixed Compilation of via:epia-m has been fixed Compilation of via:epia-n has been fixed If something broke during this checkin please be a pain in oxygene's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r6255 - in trunk/src: arch/x86 pc80
by repository service 14 Jan '11

14 Jan '11

Author: oxygene Date: Fri Jan 14 09:36:34 2011 New Revision: 6255 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6255 Log: Disable CMOS recovery code for ROMCC boards as the CBFS code used for that feature is not ROMCC compatible. Fixes build errors introduced in r6253. Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Acked-by: Patrick Georgi <patrick.georgi(a)secunet.com> Modified: trunk/src/arch/x86/Kconfig trunk/src/pc80/mc146818rtc_early.c Modified: trunk/src/arch/x86/Kconfig ============================================================================== --- trunk/src/arch/x86/Kconfig Fri Jan 14 08:41:42 2011 (r6254) +++ trunk/src/arch/x86/Kconfig Fri Jan 14 09:36:34 2011 (r6255) @@ -91,8 +91,14 @@ config BOOTBLOCK_NORTHBRIDGE_INIT string +config USE_CMOS_RECOVERY + bool + default n if ROMCC + default y + config HAVE_CMOS_DEFAULT def_bool n + depends on USE_CMOS_RECOVERY config CMOS_DEFAULT_FILE string Modified: trunk/src/pc80/mc146818rtc_early.c ============================================================================== --- trunk/src/pc80/mc146818rtc_early.c Fri Jan 14 08:41:42 2011 (r6254) +++ trunk/src/pc80/mc146818rtc_early.c Fri Jan 14 09:36:34 2011 (r6255) @@ -1,6 +1,5 @@ #include <pc80/mc146818rtc.h> #include <fallback.h> -#include <cbfs.h> #if CONFIG_USE_OPTION_TABLE #include "option_table.h" #endif @@ -12,18 +11,20 @@ #error "CONFIG_MAX_REBOOT_CNT too high" #endif +#if CONFIG_USE_CMOS_RECOVERY +#include <cbfs.h> #include <console/loglevel.h> int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3))); #define printk_warning(fmt, arg...) do_printk(BIOS_WARNING ,fmt, ##arg) #define printk_debug(fmt, arg...) do_printk(BIOS_DEBUG ,fmt, ##arg) +#endif static int cmos_error(void) { unsigned char reg_d; /* See if the cmos error condition has been flagged */ reg_d = cmos_read(RTC_REG_D); - printk_debug("CMOS_REG_D(VRT): %x\n", reg_d & RTC_VRT); return (reg_d & RTC_VRT) == 0; } @@ -43,7 +44,6 @@ old_sum = cmos_read(LB_CKS_LOC) << 8; old_sum |= cmos_read(LB_CKS_LOC+1); - printk_debug("CMOS checksum: old = %lx, new=%lx\n", old_sum, sum); return sum == old_sum; #else return 0; @@ -60,11 +60,12 @@ static inline int do_normal_boot(void) { - char *cmos_default = cbfs_find_file("cmos.default", 0xaa); unsigned char byte; int i; if (cmos_error() || !cmos_chksum_valid()) { +#if CONFIG_USE_CMOS_RECOVERY + char *cmos_default = cbfs_find_file("cmos.default", 0xaa); if (cmos_default) { printk_warning("WARNING - CMOS CORRUPTED. RESTORING DEFAULTS.\n"); /* First 14 bytes are reserved for @@ -79,6 +80,7 @@ outb(0x06, 0xcf9); for (;;) asm("hlt"); /* Wait for reset! */ } +#endif /* There are no impossible values, no checksums so just * trust whatever value we have in the the cmos,

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build service results for r6254
by repository service 14 Jan '11

14 Jan '11

Dear coreboot readers! This is the automatic build system of coreboot. The developer "oxygene" checked in revision 6254 to the coreboot repository. This caused the following changes: Change Log: Improved GPIO setup for roda/rk886ex, and some documentation on what the GPIOs are used for. Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Acked-by: Stefan Reinauer <stepan(a)coreboot.org> Build Log: Compilation of advantech:pcm-5820 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6254&device=pcm-5820&vendo… Compilation of asi:mb_5blgp is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6254&device=mb_5blgp&vendo… Compilation of asi:mb_5blmp is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6254&device=mb_5blmp&vendo… Compilation of axus:tc320 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6254&device=tc320&vendor=a… Compilation of bcom:winnet100 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6254&device=winnet100&vend… Compilation of dell:s1850 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6254&device=s1850&vendor=d… Compilation of digitallogic:msm586seg is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6254&device=msm586seg&vend… Compilation of eaglelion:5bcm is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6254&device=5bcm&vendor=ea… Compilation of emulation:qemu-x86 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6254&device=qemu-x86&vendo… Compilation of iei:juki-511p is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6254&device=juki-511p&vend… Compilation of iei:nova4899r is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6254&device=nova4899r&vend… Compilation of intel:jarrell is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6254&device=jarrell&vendor… Compilation of intel:truxton is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6254&device=truxton&vendor… Compilation of intel:xe7501devkit is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6254&device=xe7501devkit&v… Compilation of supermicro:x6dai_g is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6254&device=x6dai_g&vendor… Compilation of supermicro:x6dhe_g is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6254&device=x6dhe_g&vendor… Compilation of supermicro:x6dhe_g2 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6254&device=x6dhe_g2&vendo… Compilation of supermicro:x6dhr_ig is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6254&device=x6dhr_ig&vendo… Compilation of supermicro:x6dhr_ig2 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6254&device=x6dhr_ig2&vend… Compilation of technologic:ts5300 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6254&device=ts5300&vendor=… Compilation of televideo:tc7020 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6254&device=tc7020&vendor=… Compilation of via:epia is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6254&device=epia&vendor=vi… Compilation of via:epia-m is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6254&device=epia-m&vendor=… Compilation of via:epia-n is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6254&device=epia-n&vendor=… If something broke during this checkin please be a pain in oxygene's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

build service results for r6253
by repository service 14 Jan '11

14 Jan '11

Dear coreboot readers! This is the automatic build system of coreboot. The developer "oxygene" checked in revision 6253 to the coreboot repository. This caused the following changes: Change Log: Allow coreboot to initialize CMOS if checksum is invalid. If a file "cmos.default", type "cmos default"(0xaa) is in CBFS, a wrong checksum leads to coreboot rewriting the first 128 bytes (except for clock data) with the data in cmos.default, then reboots the system so every component of coreboot works with the same set of values. Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Acked-by: Stefan Reinauer <stepan(a)coreboot.org> Build Log: Compilation of advantech:pcm-5820 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6253&device=pcm-5820&vendo… Compilation of asi:mb_5blgp has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6253&device=mb_5blgp&vendo… Compilation of asi:mb_5blmp has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6253&device=mb_5blmp&vendo… Compilation of axus:tc320 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6253&device=tc320&vendor=a… Compilation of bcom:winnet100 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6253&device=winnet100&vend… Compilation of dell:s1850 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6253&device=s1850&vendor=d… Compilation of digitallogic:msm586seg has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6253&device=msm586seg&vend… Compilation of eaglelion:5bcm has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6253&device=5bcm&vendor=ea… Compilation of emulation:qemu-x86 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6253&device=qemu-x86&vendo… Compilation of iei:juki-511p has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6253&device=juki-511p&vend… Compilation of iei:nova4899r has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6253&device=nova4899r&vend… Compilation of intel:jarrell has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6253&device=jarrell&vendor… Compilation of intel:truxton has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6253&device=truxton&vendor… Compilation of intel:xe7501devkit has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6253&device=xe7501devkit&v… Compilation of supermicro:x6dai_g has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6253&device=x6dai_g&vendor… Compilation of supermicro:x6dhe_g has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6253&device=x6dhe_g&vendor… Compilation of supermicro:x6dhe_g2 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6253&device=x6dhe_g2&vendo… Compilation of supermicro:x6dhr_ig has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6253&device=x6dhr_ig&vendo… Compilation of supermicro:x6dhr_ig2 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6253&device=x6dhr_ig2&vend… Compilation of technologic:ts5300 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6253&device=ts5300&vendor=… Compilation of televideo:tc7020 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6253&device=tc7020&vendor=… Compilation of via:epia has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6253&device=epia&vendor=vi… Compilation of via:epia-m has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6253&device=epia-m&vendor=… Compilation of via:epia-n has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6253&device=epia-n&vendor=… If something broke during this checkin please be a pain in oxygene's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

[commit] r6254 - trunk/src/mainboard/roda/rk886ex
by repository service 14 Jan '11

14 Jan '11

Author: oxygene Date: Fri Jan 14 08:41:42 2011 New Revision: 6254 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6254 Log: Improved GPIO setup for roda/rk886ex, and some documentation on what the GPIOs are used for. Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Acked-by: Stefan Reinauer <stepan(a)coreboot.org> Modified: trunk/src/mainboard/roda/rk886ex/romstage.c Modified: trunk/src/mainboard/roda/rk886ex/romstage.c ============================================================================== --- trunk/src/mainboard/roda/rk886ex/romstage.c Fri Jan 14 08:40:24 2011 (r6253) +++ trunk/src/mainboard/roda/rk886ex/romstage.c Fri Jan 14 08:41:42 2011 (r6254) @@ -43,14 +43,27 @@ /* General Registers */ outl(0xbfc0f7c0, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ outl(0x70a87d83, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ - outl(0x7dc07f83, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ + // ------------------------------------------------------------ + // 0 - GPO6 - Enable power of SATA channel 0 + // 0 - GPO9 - Wireless LAN power on + // 0 - GPO15 - FAN on + // 1 - GPO22 - FWH WP + // 1 - GPO24 - GPS on + // 0 - GPO25 - External Antenna Mux on + // 0 - GPO26 - BT on + // 0 - GPO27 - GSM on + outl(0x01400000, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ + // ------------------------------------------------------------ /* Output Control Registers */ outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */ /* Input Control Registers */ outl(0x00002180, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ outl(0x000100e8, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ outl(0x00000030, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ - outl(0x00010030, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */ + // ------------------------------------------------------------ + // 1 - GPO48 - FWH TBL# + outl(0x00010000, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */ + // ------------------------------------------------------------ } static void ich7_enable_lpc(void)

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abuild error
by Nils 14 Jan '11

14 Jan '11

I did a abuild run on r6252 and got the following error: Building technologic/ts5300; i386: ok Creating config file... ok; Compiling image on 1 cpu .. FAILED after 19s! Log excerpt: /bin/sh: -Wa,--divide: not found CBFS coreboot.rom PAYLOAD SeaBIOS (internal, compression: LZMA) Could not add the file to CBFS, it's probably too big. File size: 46723 bytes (45 KB). make: *** [coreboot-builds/technologic_ts5300/coreboot.rom] Fout 1 Is this a known problem? Thanks, Nils.

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Re: [coreboot] Here is my new board. Can coreboot be implemented on it?
by Neo The User 14 Jan '11

14 Jan '11

> From: Neo The User <neotheuser(a)ymail.com> > Subject: Re: [coreboot] Here is my new board. Can coreboot be implemented on it? > To: coreboot(a)coreboot.org > Specifically the GIGABYTE GA-MA785GM-US2H, as its > only $70 ($85 when not on sale) USD which isn't exactly that > much for a relatively good motherboard. Sorry I forgot to add, that this price is listed on newegg. Also this board has 2 BIOS chips, M BIOS (main BIOS) and B BIOS (back-up) so in case coreboot bricks your motherboard, you can simply turn it on, and hold (or quickly tap) the reset button down for 10 seconds right after you let go of the power button, and B BIOS will start up and reflash M BIOS. You can also bridge pins 4 (GND) and 7 (#HOLD) and this will force the re-flash. -Alec

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coreboot January 2011