coreboot January 2011

coreboot@coreboot.org

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299 discussions

[commit] r6261 - trunk/src/vendorcode
by repository service 18 Jan '11

18 Jan '11

Author: zbao Date: Tue Jan 18 10:29:19 2011 New Revision: 6261 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6261 Log: remove the code which is not ready to release. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Acked-by: Zheng Bao <zheng.bao(a)amd.com> Deleted: trunk/src/vendorcode/

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Re: [coreboot] Jetw. J8F9 support
by Cristian Craciunescu 18 Jan '11

18 Jan '11

I'm sure the problem is coming from PIRQ map; needs some fine tuning. The board has four serials and all of them are connected the 81216DG super IO chip so I'm using the first serial port, the onchip uarts are disabled. There is an additional hwmon chip(f71858) which I did not touched yet. Attached the patch with j8 dir in mainboard and f81216DG superio added. Regards, Cristian On Tue, Jan 18, 2011 at 10:01 AM, Cristian Craciunescu <ccristian(a)gmail.com>wrote: > Cristian Craciunescu wrote: > > I've compiled suport for j8f9 board from jetw. using as template other LX > > mainboard. The system is booting with coreboot/seabios however the serial > > does not seam to work in kernel. GRUB bootloader works ok over serial but > as > > soon as the linux kernel finish booting it does not respond over serial > but > > it can send messages to serial. Although the IRQs are detected correctly > > when the serial has input I can not see any irq messages incrementing in > > /proc/interrupts. Any hint? > > Something is wrong with the interrupt setup in coreboot if they are > not being delivered to the kernel. > > Are you using the internal UART in CS5536 or do you have a superio? > Which board did you use as template? > Can you post a patch with your code so far? > > > //Peter >

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[commit] r5902 - in trunk/src: cpu/amd/car cpu/intel/car cpu/intel/model_106cx cpu/intel/model_6ex cpu/intel/model_6fx cpu/via/car include/cpu/x86
by repository service 17 Jan '11

17 Jan '11

Author: uwe Date: Fri Oct 1 23:46:04 2010 New Revision: 5902 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5902 Log: Factor out common CAR asm snippets. This makes the CAR implementations a lot more readable, shorter and easier to follow, and also reduces the amount of uselessly duplicated code. For example there are more than 12 open-coded "enable cache" instances spread all over the place (and 12 "disable cache" ones), multiple "enable mtrr", "save BIST", "restore BIST", etc. etc. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Peter Stuge <peter(a)stuge.se> Added: trunk/src/include/cpu/x86/car.h Modified: trunk/src/cpu/amd/car/cache_as_ram.inc trunk/src/cpu/intel/car/cache_as_ram.inc trunk/src/cpu/intel/model_106cx/cache_as_ram.inc trunk/src/cpu/intel/model_6ex/cache_as_ram.inc trunk/src/cpu/intel/model_6fx/cache_as_ram.inc trunk/src/cpu/via/car/cache_as_ram.inc Modified: trunk/src/cpu/amd/car/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/amd/car/cache_as_ram.inc Fri Oct 1 19:37:45 2010 (r5901) +++ trunk/src/cpu/amd/car/cache_as_ram.inc Fri Oct 1 23:46:04 2010 (r5902) @@ -18,6 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <cpu/x86/car.h> #include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h> @@ -45,8 +46,7 @@ * xmm3: Backup EBX */ - /* Save the BIST result. */ - movl %eax, %ebp + save_bist_result() /* * For normal part %ebx already contain cpu_init_detected @@ -56,10 +56,7 @@ cache_as_ram_setup: post_code(0xa0) - /* Enable SSE. */ - movl %cr4, %eax - orl $(3 << 9), %eax - movl %eax, %cr4 + enable_sse() /* Figure out the CPU family. */ cvtsi2sd %ebx, %xmm3 @@ -299,10 +296,7 @@ post_code(0xa1) - /* Enable cache. */ - movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax - movl %eax, %cr0 + enable_cache() jmp_if_k8(fam10_end_part1) @@ -384,13 +378,9 @@ post_code(0xa5) - /* Disable SSE. */ - movl %cr4, %eax - andl $~(3 << 9), %eax - movl %eax, %cr4 + disable_sse() - /* Restore the BIST result. */ - movl %ebp, %eax + restore_bist_result() /* We need to set EBP? No need. */ movl %esp, %ebp Modified: trunk/src/cpu/intel/car/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/car/cache_as_ram.inc Fri Oct 1 19:37:45 2010 (r5901) +++ trunk/src/cpu/intel/car/cache_as_ram.inc Fri Oct 1 23:46:04 2010 (r5902) @@ -21,6 +21,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <cpu/x86/car.h> #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/lapic_def.h> @@ -28,8 +29,7 @@ #define CacheSize CONFIG_DCACHE_RAM_SIZE #define CacheBase (0xd0000 - CacheSize) - /* Save the BIST result. */ - movl %eax, %ebp + save_bist_result() CacheAsRam: /* Check whether the processor has HT capability. */ @@ -231,10 +231,7 @@ wrmsr #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ - /* Enable cache. */ - movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax - movl %eax, %cr0 + enable_cache() /* Read the range with lodsl. */ movl $CacheBase, %esi @@ -295,8 +292,7 @@ movl $(CacheBase + CacheSize - 4), %eax movl %eax, %esp lout: - /* Restore the BIST result. */ - movl %ebp, %eax + restore_bist_result() /* We need to set EBP? No need. */ movl %esp, %ebp @@ -305,10 +301,7 @@ /* We don't need CAR from now on. */ - /* Disable cache. */ - movl %cr0, %eax - orl $(1 << 30), %eax - movl %eax, %cr0 + disable_cache() /* Clear sth. */ movl $MTRRfix4K_C8000_MSR, %ecx @@ -330,10 +323,7 @@ movl $0x00000800, %eax /* Enable variable and disable fixed MTRRs. */ wrmsr - /* Enable cache. */ - movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax - movl %eax, %cr0 + enable_cache(); /* Clear boot_complete flag. */ xorl %ebp, %ebp Modified: trunk/src/cpu/intel/model_106cx/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/model_106cx/cache_as_ram.inc Fri Oct 1 19:37:45 2010 (r5901) +++ trunk/src/cpu/intel/model_106cx/cache_as_ram.inc Fri Oct 1 23:46:04 2010 (r5902) @@ -18,14 +18,14 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <cpu/x86/car.h> #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE - /* Save the BIST result. */ - movl %eax, %ebp + save_bist_result() cache_as_ram: post_code(0x20) @@ -66,19 +66,12 @@ xorl %edx, %edx wrmsr - /* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - orl $(1 << 11), %eax - wrmsr + enable_mtrr() - /* Enable L2 cache. */ - movl $0x11e, %ecx - rdmsr - orl $(1 << 8), %eax - wrmsr + enable_l2_cache() /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ + /* TODO: enable_cache()? But that doesn't have "invd". */ movl %cr0, %eax andl $(~((1 << 30) | (1 << 29))), %eax invd @@ -93,9 +86,7 @@ rep stosl /* Enable Cache-as-RAM mode by disabling cache. */ - movl %cr0, %eax - orl $(1 << 30), %eax - movl %eax, %cr0 + disable_cache() #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) /* Enable cache for our code in Flash because we do XIP here */ @@ -116,10 +107,7 @@ wrmsr #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ - /* Enable cache. */ - movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax - movl %eax, %cr0 + enable_cache() /* Set up the stack pointer. */ #if defined(CONFIG_USBDEBUG) && (CONFIG_USBDEBUG == 1) @@ -130,8 +118,8 @@ #endif movl %eax, %esp - /* Restore the BIST result. */ - movl %ebp, %eax + restore_bist_result() + movl %esp, %ebp pushl %eax @@ -144,18 +132,11 @@ post_code(0x30) - /* Disable cache. */ - movl %cr0, %eax - orl $(1 << 30), %eax - movl %eax, %cr0 + disable_cache() post_code(0x31) - /* Disable MTRR. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - andl $(~(1 << 11)), %eax - wrmsr + disable_mtrr() post_code(0x31) @@ -175,17 +156,11 @@ post_code(0x33) - /* Enable cache. */ - movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax - movl %eax, %cr0 + enable_cache() post_code(0x36) - /* Disable cache. */ - movl %cr0, %eax - orl $(1 << 30), %eax - movl %eax, %cr0 + disable_cache() post_code(0x38) @@ -202,17 +177,11 @@ post_code(0x39) /* And enable cache again after setting MTRRs. */ - movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax - movl %eax, %cr0 + enable_cache() post_code(0x3a) - /* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - orl $(1 << 11), %eax - wrmsr + enable_mtrr() post_code(0x3b) Modified: trunk/src/cpu/intel/model_6ex/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/model_6ex/cache_as_ram.inc Fri Oct 1 19:37:45 2010 (r5901) +++ trunk/src/cpu/intel/model_6ex/cache_as_ram.inc Fri Oct 1 23:46:04 2010 (r5902) @@ -18,14 +18,14 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <cpu/x86/car.h> #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE - /* Save the BIST result. */ - movl %eax, %ebp + save_bist_result() cache_as_ram: post_code(0x20) @@ -66,19 +66,12 @@ movl $0x0000000f, %edx wrmsr - /* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - orl $(1 << 11), %eax - wrmsr + enable_mtrr() - /* Enable L2 cache. */ - movl $0x11e, %ecx - rdmsr - orl $(1 << 8), %eax - wrmsr + enable_l2_cache() /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ + /* TODO: enable_cache()? But that doesn't have "invd". */ movl %cr0, %eax andl $(~((1 << 30) | (1 << 29))), %eax invd @@ -93,9 +86,7 @@ rep stosl /* Enable Cache-as-RAM mode by disabling cache. */ - movl %cr0, %eax - orl $(1 << 30), %eax - movl %eax, %cr0 + disable_cache() #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) /* Enable cache for our code in Flash because we do XIP here */ @@ -116,10 +107,7 @@ wrmsr #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ - /* Enable cache. */ - movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax - movl %eax, %cr0 + enable_cache() /* Set up the stack pointer. */ #if defined(CONFIG_USBDEBUG) && (CONFIG_USBDEBUG == 1) @@ -130,8 +118,8 @@ #endif movl %eax, %esp - /* Restore the BIST result. */ - movl %ebp, %eax + restore_bist_result() + movl %esp, %ebp pushl %eax @@ -144,18 +132,11 @@ post_code(0x30) - /* Disable cache. */ - movl %cr0, %eax - orl $(1 << 30), %eax - movl %eax, %cr0 + disable_cache() post_code(0x31) - /* Disable MTRR. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - andl $(~(1 << 11)), %eax - wrmsr + disable_mtrr() post_code(0x31) @@ -175,17 +156,11 @@ post_code(0x33) - /* Enable cache. */ - movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax - movl %eax, %cr0 + enable_cache() post_code(0x36) - /* Disable cache. */ - movl %cr0, %eax - orl $(1 << 30), %eax - movl %eax, %cr0 + disable_cache() post_code(0x38) @@ -202,17 +177,11 @@ post_code(0x39) /* And enable cache again after setting MTRRs. */ - movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax - movl %eax, %cr0 + enable_cache() post_code(0x3a) - /* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - orl $(1 << 11), %eax - wrmsr + enable_mtrr() post_code(0x3b) Modified: trunk/src/cpu/intel/model_6fx/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/model_6fx/cache_as_ram.inc Fri Oct 1 19:37:45 2010 (r5901) +++ trunk/src/cpu/intel/model_6fx/cache_as_ram.inc Fri Oct 1 23:46:04 2010 (r5902) @@ -18,14 +18,14 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <cpu/x86/car.h> #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE - /* Save the BIST result. */ - movl %eax, %ebp + save_bist_result() cache_as_ram: post_code(0x20) @@ -73,19 +73,12 @@ movl $0x0000000f, %edx wrmsr - /* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - orl $(1 << 11), %eax - wrmsr + enable_mtrr() - /* Enable L2 cache. */ - movl $0x11e, %ecx - rdmsr - orl $(1 << 8), %eax - wrmsr + enable_l2_cache() /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ + /* TODO: enable_cache()? But that doesn't have "invd". */ movl %cr0, %eax andl $(~((1 << 30) | (1 << 29))), %eax invd @@ -100,9 +93,7 @@ rep stosl /* Enable Cache-as-RAM mode by disabling cache. */ - movl %cr0, %eax - orl $(1 << 30), %eax - movl %eax, %cr0 + disable_cache() #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) /* Enable cache for our code in Flash because we do XIP here */ @@ -123,10 +114,7 @@ wrmsr #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ - /* Enable cache. */ - movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax - movl %eax, %cr0 + enable_cache() /* Set up the stack pointer. */ #if defined(CONFIG_USBDEBUG) && (CONFIG_USBDEBUG == 1) @@ -137,8 +125,8 @@ #endif movl %eax, %esp - /* Restore the BIST result. */ - movl %ebp, %eax + restore_bist_result() + movl %esp, %ebp pushl %eax @@ -151,18 +139,11 @@ post_code(0x30) - /* Disable cache. */ - movl %cr0, %eax - orl $(1 << 30), %eax - movl %eax, %cr0 + disable_cache() post_code(0x31) - /* Disable MTRR. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - andl $(~(1 << 11)), %eax - wrmsr + disable_mtrr() post_code(0x31) @@ -182,17 +163,11 @@ post_code(0x33) - /* Enable cache. */ - movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax - movl %eax, %cr0 + enable_cache() post_code(0x36) - /* Disable cache. */ - movl %cr0, %eax - orl $(1 << 30), %eax - movl %eax, %cr0 + disable_cache() post_code(0x38) @@ -209,17 +184,11 @@ post_code(0x39) /* And enable cache again after setting MTRRs. */ - movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax - movl %eax, %cr0 + enable_cache() post_code(0x3a) - /* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - orl $(1 << 11), %eax - wrmsr + enable_mtrr() post_code(0x3b) Modified: trunk/src/cpu/via/car/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/via/car/cache_as_ram.inc Fri Oct 1 19:37:45 2010 (r5901) +++ trunk/src/cpu/via/car/cache_as_ram.inc Fri Oct 1 23:46:04 2010 (r5902) @@ -25,21 +25,18 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <cpu/x86/car.h> #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> #define CacheSize CONFIG_DCACHE_RAM_SIZE #define CacheBase CONFIG_DCACHE_RAM_BASE - /* Save the BIST result. */ - movl %eax, %ebp + save_bist_result() CacheAsRam: - /* Disable cache. */ - movl %cr0, %eax - orl $(1 << 30), %eax - movl %eax, %cr0 + disable_cache() invd /* Set the default memory type and enable fixed and variable MTRRs. */ @@ -116,10 +113,7 @@ movl $(MTRRdefTypeEn), %eax wrmsr - /* Enable cache. */ - movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax - movl %eax, %cr0 + enable_cache() /* Read the range with lodsl. */ cld @@ -175,8 +169,7 @@ jne stackerr #endif - /* Restore the BIST result. */ - movl %ebp, %eax + restore_bist_result() /* We need to set EBP? No need. */ movl %esp, %ebp @@ -191,10 +184,7 @@ /* We don't need CAR from now on. */ - /* Disable cache. */ - movl %cr0, %eax - orl $(1 << 30), %eax - movl %eax, %cr0 + disable_cache() /* Set the default memory type and enable variable MTRRs. */ /* TODO: Or also enable fixed MTRRs? Bug in the code? */ @@ -253,10 +243,7 @@ movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax wrmsr - /* Enable cache. */ - movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax - movl %eax, %cr0 + enable_cache() invd /* Clear boot_complete flag. */ Added: trunk/src/include/cpu/x86/car.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/include/cpu/x86/car.h Fri Oct 1 23:46:04 2010 (r5902) @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich(a)gmail.com> + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cpu/x86/mtrr.h> + +/* Save the BIST result. */ +#define save_bist_result() \ + movl %eax, %ebp + +/* Restore the BIST result. */ +#define restore_bist_result() \ + movl %ebp, %eax + +/* Enable cache. */ +#define enable_cache() \ + movl %cr0, %eax; \ + andl $(~((1 << 30) | (1 << 29))), %eax; \ + movl %eax, %cr0 + +/* Disable cache. */ +#define disable_cache() \ + movl %cr0, %eax; \ + orl $(1 << 30), %eax; \ + movl %eax, %cr0 + +/* Enable MTRR. */ +#define enable_mtrr() \ + movl $MTRRdefType_MSR, %ecx; \ + rdmsr; \ + orl $(1 << 11), %eax; \ + wrmsr + +/* Disable MTRR. */ +#define disable_mtrr() \ + movl $MTRRdefType_MSR, %ecx; \ + rdmsr; \ + andl $(~(1 << 11)), %eax; \ + wrmsr + +/* Enable L2 cache. */ +#define enable_l2_cache() \ + movl $0x11e, %ecx; \ + rdmsr; \ + orl $(1 << 8), %eax; \ + wrmsr + +/* Enable SSE. */ +#define enable_sse() \ + movl %cr4, %eax; \ + orl $(3 << 9), %eax; \ + movl %eax, %cr4 + +/* Disable SSE. */ +#define disable_sse() \ + movl %cr4, %eax; \ + andl $~(3 << 9), %eax; \ + movl %eax, %cr4 +

5 5

[PATCH] Fix compile failure when VGA_ROM_RUN disabled on epia-cn.
by Kevin O'Connor 17 Jan '11

17 Jan '11

The cn700.c code references mainboard_interrupt_handlers() which isn't defined if VGA_ROM_RUN is off. Define a dummy implementation of that function for this case. Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> --- src/arch/x86/include/arch/interrupt.h | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/src/arch/x86/include/arch/interrupt.h b/src/arch/x86/include/arch/interrupt.h index 2d2330b..c3cda30 100644 --- a/src/arch/x86/include/arch/interrupt.h +++ b/src/arch/x86/include/arch/interrupt.h @@ -22,4 +22,8 @@ #include "registers.h" /* setup interrupt handlers for mainboard */ +#if defined(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) && CONFIG_PCI_OPTION_ROM_RUN_REALMODE extern void mainboard_interrupt_handlers(int intXX, void *intXX_func); +#else +static inline void mainboard_interrupt_handlers(int intXX, void *intXX_func) { } +#endif -- 1.7.3.4

3 6

[PATCH] Via CAR code should cache CONFIG_RAMBASE..CONFIG_RAMTOP for ramstage.
by Kevin O'Connor 17 Jan '11

17 Jan '11

Now that the VIA code is run above 1Meg (like other boards), it should cache that range instead of the first 1Meg. This reduces boot time by about 1 second on epia-cn. This patch also adds a MTRRphysMaskValid bit definition. Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> --- src/cpu/via/car/cache_as_ram.inc | 43 +++++++------------------------------ src/cpu/x86/mtrr/mtrr.c | 4 +- src/include/cpu/x86/mtrr.h | 2 + 3 files changed, 12 insertions(+), 37 deletions(-) diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc index 1f0bed2..c3c1cb7 100644 --- a/src/cpu/via/car/cache_as_ram.inc +++ b/src/cpu/via/car/cache_as_ram.inc @@ -103,7 +103,7 @@ clear_fixed_var_mtrr_out: movl $MTRRphysMask_MSR(0), %ecx /* This assumes we never access addresses above 2^36 in CAR. */ movl $0x0000000f, %edx - movl $(~(CacheSize - 1) | 0x800), %eax + movl $(~(CacheSize - 1) | MTRRphysMaskValid), %eax wrmsr #if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK @@ -129,7 +129,7 @@ clear_fixed_var_mtrr_out: movl $MTRRphysMask_MSR(1), %ecx movl $0x0000000f, %edx - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax wrmsr /* Set the default memory type and enable fixed and variable MTRRs. */ @@ -219,54 +219,27 @@ testok: movl $(MTRRdefTypeEn), %eax wrmsr - /* Enable caching for first 1M using variable MTRR. */ + /* Enable caching for CONFIG_RAMBASE..CONFIG_RAMTOP. */ movl $MTRRphysBase_MSR(0), %ecx xorl %edx, %edx - movl $(0 | MTRR_TYPE_WRBACK), %eax + movl $(CONFIG_RAMBASE | MTRR_TYPE_WRBACK), %eax wrmsr - /* - * Enable cache for 0-7ffff, 80000-9ffff, e0000-fffff; - * If 1M cacheable, then when S3 resume, there is stange color on - * screen for 2 sec. Suppose problem of a0000-dfffff and cache. - * And in x86_setup_fixed_mtrrs()(mtrr.c), 0-256M is set cacheable. - */ - movl $MTRRphysMask_MSR(0), %ecx movl $0x0000000f, %edx /* AMD 40 bit 0xff */ - movl $((~((0 + 0x80000) - 1)) | 0x800), %eax - wrmsr - - movl $MTRRphysBase_MSR(1), %ecx - xorl %edx, %edx - movl $(0x80000 | MTRR_TYPE_WRBACK), %eax - wrmsr - - movl $MTRRphysMask_MSR(1), %ecx - movl $0x0000000f, %edx /* AMD 40 bit 0xff */ - movl $((~((0 + 0x20000) - 1)) | 0x800), %eax - wrmsr - - movl $MTRRphysBase_MSR(2), %ecx - xorl %edx, %edx - movl $(0xc0000 | MTRR_TYPE_WRBACK), %eax - wrmsr - - movl $MTRRphysMask_MSR(2), %ecx - movl $0x0000000f, %edx /* AMD 40 bit 0xff */ - movl $((~(( 0 + 0x40000) - 1)) | 0x800), %eax + movl $(~(CONFIG_RAMTOP - CONFIG_RAMBASE - 1) | MTRRphysMaskValid), %eax wrmsr /* Cache XIP_ROM_BASE-SIZE to speedup coreboot code. */ - movl $MTRRphysBase_MSR(3), %ecx + movl $MTRRphysBase_MSR(1), %ecx xorl %edx, %edx movl $REAL_XIP_ROM_BASE, %eax orl $MTRR_TYPE_WRBACK, %eax wrmsr - movl $MTRRphysMask_MSR(3), %ecx + movl $MTRRphysMask_MSR(1), %ecx xorl %edx, %edx - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax wrmsr enable_cache() diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 92d961d..1eda759 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -62,7 +62,7 @@ static void enable_var_mtrr(void) msr_t msr; msr = rdmsr(MTRRdefType_MSR); - msr.lo |= 0x800; + msr.lo |= MTRRdefTypeEn; wrmsr(MTRRdefType_MSR, msr); } @@ -115,7 +115,7 @@ static void set_var_mtrr( /* Bit 32-35 of MTRRphysMask should be set to 1 */ base.lo |= type; - mask.lo |= 0x800; + mask.lo |= MTRRphysMaskValid; wrmsr (MTRRphysBase_MSR(reg), base); wrmsr (MTRRphysMask_MSR(reg), mask); diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 164d79a..f9aadc5 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -21,6 +21,8 @@ #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg)) #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1) +#define MTRRphysMaskValid (1 << 11) + #define NUM_FIXED_RANGES 88 #define MTRRfix64K_00000_MSR 0x250 #define MTRRfix16K_80000_MSR 0x258 -- 1.7.3.4

2 2

Trac reminder: list of new ticket(s)
by coreboot tracker 17 Jan '11

17 Jan '11

1 0

[commit] r6260 - trunk/util/cbfstool
by repository service 17 Jan '11

17 Jan '11

Author: stuge Date: Mon Jan 17 06:08:32 2011 New Revision: 6260 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6260 Log: cbfstool: When extracting, refer to files in CBFS as file instead of payload Signed-off-by: Peter Stuge <peter(a)stuge.se> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/util/cbfstool/common.c Modified: trunk/util/cbfstool/common.c ============================================================================== --- trunk/util/cbfstool/common.c Mon Jan 17 06:02:09 2011 (r6259) +++ trunk/util/cbfstool/common.c Mon Jan 17 06:08:32 2011 (r6260) @@ -241,7 +241,7 @@ } // Else, it's our file. - printf("Found %.30s payload at 0x%x, type %.12s, size %d\n", fname, + printf("Found file %.30s at 0x%x, type %.12s, size %d\n", fname, current - phys_start, strfiletype(ntohl(thisfile->type)), length); @@ -262,7 +262,7 @@ + ntohl(thisfile->offset), length, 1, outfile); fclose(outfile); - printf("Successfully dumped the payload.\n"); + printf("Successfully dumped the file.\n"); // We'll only dump one file. return 0;

1 0

[commit] r6259 - trunk/util/cbfstool
by repository service 17 Jan '11

17 Jan '11

Author: stuge Date: Mon Jan 17 06:02:09 2011 New Revision: 6259 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6259 Log: cbfstool: Trivial move of newline after commands in usage Signed-off-by: Peter Stuge <peter(a)stuge.se> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/util/cbfstool/cbfstool.c Modified: trunk/util/cbfstool/cbfstool.c ============================================================================== --- trunk/util/cbfstool/cbfstool.c Mon Jan 17 03:20:33 2011 (r6258) +++ trunk/util/cbfstool/cbfstool.c Mon Jan 17 06:02:09 2011 (r6259) @@ -289,7 +289,8 @@ " create SIZE BOOTBLOCK [ALIGN] Create a ROM file\n" " locate FILE NAME ALIGN Find a place for a file of that size\n" " print Show the contents of the ROM\n" - " extract NAME FILE Extracts a raw payload from ROM\n\n" + " extract NAME FILE Extracts a raw payload from ROM\n" + "\n" "TYPEs:\n" ); print_supported_filetypes();

1 0

Jetw. J8F9 support
by Cristian Craciunescu 17 Jan '11

17 Jan '11

Hello, I've compiled suport for j8f9 board from jetw. using as template other LX mainboard. The system is booting with coreboot/seabios however the serial does not seam to work in kernel. GRUB bootloader works ok over serial but as soon as the linux kernel finish booting it does not respond over serial but it can send messages to serial. Although the IRQs are detected correctly when the serial has input I can not see any irq messages incrementing in /proc/interrupts. Any hint? Regards, Cristian

2 1

[commit] r6258 - trunk/src/northbridge/amd/amdmct/mct_ddr3
by repository service 17 Jan '11

17 Jan '11

Author: zbao Date: Mon Jan 17 03:20:33 2011 New Revision: 6258 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6258 Log: The code is tested on my board with register DIMMs. More tests need to be done. Please send the testing report. Note: The pDCTstat->PresetmaxFreq in mctGet_MaxLoadFreq() should be set to a higher limit, otherwise the frequnce will be set as 400MHz. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Acked-by: Scott Duplichan <scott(a)notabs.org> Modified: trunk/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c trunk/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c Modified: trunk/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c Sun Jan 16 18:15:36 2011 (r6257) +++ trunk/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c Mon Jan 17 03:20:33 2011 (r6258) @@ -342,7 +342,21 @@ mct_Wait(250); if (pDCTstat->Status & (1 << SB_Registered)) { - /* TODO: Assuming the dct==0. The agesa here is confusing. */ + u8 DCT0Present, DCT1Present; + + DCT0Present = pDCTstat->DIMMValidDCT[0]; + if (pDCTstat->GangedMode) + DCT1Present = 0; + else + DCT1Present = pDCTstat->DIMMValidDCT[1]; + + if (!DCT1Present) + pDCTstat->CSPresent = pDCTstat->CSPresent_DCT[0]; + else if (pDCTstat->GangedMode) { + pDCTstat->CSPresent = 0; + } else + pDCTstat->CSPresent = pDCTstat->CSPresent_DCT[1]; + FreqChgCtrlWrd(pMCTstat, pDCTstat); } } Modified: trunk/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c Sun Jan 16 18:15:36 2011 (r6257) +++ trunk/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c Mon Jan 17 03:20:33 2011 (r6258) @@ -86,7 +86,7 @@ procConifg(pMCTData,pDCTData, dimm, pass); /* 5. Begin write levelization training: * Program F2x[1, 0]9C_x08[WrtLevelTrEn]=1. */ - if (pDCTData->LogicalCPUID & AMD_DR_Cx) + if (pDCTData->LogicalCPUID & (AMD_DR_Cx | AMD_DR_Dx)) set_DCT_ADDR_Bits(pDCTData, pDCTData->DctTrain, pDCTData->NodeId, FUN_DCT, DRAM_ADD_DCT_PHY_CONTROL_REG, WrtLvTrEn, WrtLvTrEn, 1); else @@ -656,9 +656,9 @@ programODT(pMCTData, pDCTData, dimm); /* Program F2x[1,0]9C_x08[WrLvOdtEn]=1 */ - if (pDCTData->LogicalCPUID & AMD_DR_Cx) + if (pDCTData->LogicalCPUID & (AMD_DR_Cx | AMD_DR_Dx)) set_DCT_ADDR_Bits(pDCTData, pDCTData->DctTrain, pDCTData->NodeId, FUN_DCT, - DRAM_ADD_DCT_PHY_CONTROL_REG, WrLvOdtEn, WrLvOdtEn,(u32) 1); + DRAM_ADD_DCT_PHY_CONTROL_REG, WrLvOdtEn, WrLvOdtEn, (u32)1); else { /* Program WrLvOdtEn=1 through set bit 12 of D3CSODT reg offset 0 for Rev.B*/ @@ -722,7 +722,36 @@ pDCTData->WLFineDelay[MAX_BYTE_LANES*dimm+ByteLane] = Seed_Fine; ByteLane++; } + } else if (pDCTData->Status[DCT_STATUS_REGISTERED]) { /* For Pass 2 */ + /* From BKDG, Write Leveling Seed Value. */ + /* TODO: The unbuffered DIMMs are unstable on the code below. So temporarily it is + * only for registered DIMMs. */ + u32 RegisterDelay, SeedTotal; + u8 MemClkFreq; + u16 freq_tab[] = {400, 533, 667, 800}; + while(ByteLane < MAX_BYTE_LANES) + { + MemClkFreq = get_Bits(pDCTData, pDCTData->CurrDct, pDCTData->NodeId, + FUN_DCT, DRAM_CONFIG_HIGH, 0, 2); + if (pDCTData->Status[DCT_STATUS_REGISTERED]) + RegisterDelay = 0x20; /* TODO: ((RCW2 & BIT0) == 0) ? 0x20 : 0x30; */ + else + RegisterDelay = 0; + SeedTotal = (pDCTData->WLFineDelay[MAX_BYTE_LANES*dimm+ByteLane] & 0x1F) | + pDCTData->WLGrossDelay[MAX_BYTE_LANES*dimm+ByteLane] << 5; + /* SeedTotalPreScaling = (the total delay value in F2x[1, 0]9C_x[4A:30] from pass 1 of write levelization + training) - RegisterDelay. */ + /* MemClkFreq: 3: 400Mhz; 4: 533Mhz; 5: 667Mhz; 6: 800Mhz */ + SeedTotal = (u16) (RegisterDelay + ((((u32) SeedTotal - RegisterDelay) * + freq_tab[MemClkFreq-3]) / 400)); + Seed_Gross = (SeedTotal & 0x20) != 0 ? 1 : 2; + Seed_Fine = SeedTotal & 0x1F; + pDCTData->WLGrossDelay[MAX_BYTE_LANES*dimm+ByteLane] = Seed_Gross; + pDCTData->WLFineDelay[MAX_BYTE_LANES*dimm+ByteLane] = Seed_Fine; + ByteLane ++; + } } + setWLByteDelay(pDCTData, ByteLane, dimm, 0); }

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coreboot January 2011