coreboot January 2011

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[PATCH] Preliminary support for ASUS K8V-X SE with VIA K8T800 southbridge
by Alex G. 19 Jan '11

19 Jan '11

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Added preliminary support for the ASUS K8V-X SE and the VIA K8T800 chipset. Coreboot is able to finalize and load SeaBIOS, but not boot the system yet. /Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>/ - --- This patch should be considered a work in progress, as it adds very minimal changes to existing code. I hope the patch format is correct. Alex G. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Fedora - http://enigmail.mozdev.org/ iQIcBAEBAgAGBQJNL0VnAAoJEL0kPHNPXJJKVPYP/jazanKXpd39oXClBe2YxWN6 cjX3JZrRacoIWktMKqqOzguFccuAgPC6M+3n4kgWNH6gwQI+jadoE8kqsM/gH1EP toHrSYpK89blwubyNOszLprrJNuxGBBC3044b84FVah1+ISm81kD6GlDuGvX2GvC YhFCFe4epjq2ukYb7reLxZ6tdTOjwGVYdvdfIGnD6T7HH6kQB8adMNtsIAvtL4pa GbDAIx3IAfKOVZ6D2ettRXtC0BzGjkSmJzWA0yuGjmui+ds4B6Rhb+pcv6xMEJYP zKKrlFn2/WfMwXcpflAy1v8gH8LPwbZXE5NflD6zwtlbSPPnWT24YpGcDDycqJHX 3itkEj4z5DiOlgFN0X5T4gA4DNr4uvC72ZlJvFTMRyDSUSHKFvL5yvCAYk+CXmbZ sz1Olqpjq+NLFN0V8QtVVuVuHMXI0YWc2d7t/WtRMZKdD5swo/rrNSQOIKVVngTb Gytjm37YD9FSEXGLwroWYSg7yBIBZ10saDeHK0kwYQ8Ttaj/3TnfJT+5js9lfuYh TXL5I9oOPsrc7vmpzfuLKO9j/wDzSQsdcmd1slEPi+DKkGmzUOotNiXfR+nlF5+D dG8/dSoXPlAj2ix3hd2AwBmkrO6hyPpUEpTwSkXgkKuJCKSj6prAkJawUpUtzHq5 f3zNalHmznSLpGRfgbTy =gHyz -----END PGP SIGNATURE-----

2 2

[commit] r6274 - trunk/util/msrtool
by repository service 19 Jan '11

19 Jan '11

Author: stepan Date: Wed Jan 19 07:56:33 2011 New Revision: 6274 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6274 Log: Add Geode GX2 memmory descriptors. Add a simple README file. Signed-off-by: Nils Jacobs <njacobs8(a)hetnet.nl> Acked-by: Stefan Reinauer <stepan(a)coreboot.org> Added: trunk/util/msrtool/README Modified: trunk/util/msrtool/geodegx2.c Added: trunk/util/msrtool/README ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/util/msrtool/README Wed Jan 19 07:56:33 2011 (r6274) @@ -0,0 +1,36 @@ + +You need to be ROOT or use SUDO to execute MSRTOOL. + +Note that you need /dev/cpu/*/msr available to run msrtool in Linux. + + +syntax: msrtool [-hvqrkl] [-c cpu] [-m system] [-t target ...] + [-i addr=hi[:]lo] | [-s file] | [-d [:]file] | addr... + -h show this help text + -v be verbose + -q be quiet (overrides -v) + -r include [Reserved] values + -k list all known systems and targets + -l list MSRs and bit fields for current target(s) (-kl for ALL targets!) + -c access MSRs on the specified CPU, default=0 + -m force a system, e.g: -m linux + -t force a target, can be used multiple times, e.g: -t geodelx -t cs5536 + -i immediate mode + decode hex addr=hi:lo for the target without reading hw value + e.g: -i 4c00000f=f2f100ff56960004 + -s stream mode + read one MSR address per line and append current hw value to the line + use the filename - for stdin/stdout + using -l -s ignores input and will output all MSRs with values + -d diff mode + read one address and value per line and compare with current hw value, + printing differences to stdout. use the filename - to read from stdin + use :file or :- to reverse diff, normally hw values are considered new + addr.. direct mode, read and decode values for the given MSR address(es) + + +Examples: + +msrtool 0x20000018 + +./msrtool 0x200000{18,19,1a,1b,1c,1d} 0x4c0000{0f,14} Modified: trunk/util/msrtool/geodegx2.c ============================================================================== --- trunk/util/msrtool/geodegx2.c Wed Jan 19 07:54:42 2011 (r6273) +++ trunk/util/msrtool/geodegx2.c Wed Jan 19 07:56:33 2011 (r6274) @@ -26,6 +26,592 @@ } const struct msrdef geodegx2_msrs[] = { + { 0x10000020, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU0_P2D_BM0", "GLIU0 P2D Base Mask Descriptor 0", { + { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, { + { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, + { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, + { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, + { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, + { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, + { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, + { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, + { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, + { BITVAL_EOT } + }}, + { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { + { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, + { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, + { BITVAL_EOT } + }}, + { 59, 20, RESERVED }, + { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + { 0x10000021, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU0_P2D_BM1", "GLIU0 P2D Base Mask Descriptor 1", { + { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, { + { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, + { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, + { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, + { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, + { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, + { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, + { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, + { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, + { BITVAL_EOT } + }}, + { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { + { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, + { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, + { BITVAL_EOT } + }}, + { 59, 20, RESERVED }, + { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + { 0x10000022, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU0_P2D_BM2", "GLIU0 P2D Base Mask Descriptor 2", { + { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, { + { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, + { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, + { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, + { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, + { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, + { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, + { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, + { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, + { BITVAL_EOT } + }}, + { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { + { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, + { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, + { BITVAL_EOT } + }}, + { 59, 20, RESERVED }, + { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + { 0x10000023, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU0_P2D_BM3", "GLIU0 P2D Base Mask Descriptor 3", { + { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, { + { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, + { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, + { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, + { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, + { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, + { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, + { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, + { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, + { BITVAL_EOT } + }}, + { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { + { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, + { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, + { BITVAL_EOT } + }}, + { 59, 20, RESERVED }, + { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + { 0x10000024, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU0_P2D_BM4", "GLIU0 P2D Base Mask Descriptor 4", { + { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, { + { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, + { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, + { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, + { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, + { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, + { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, + { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, + { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, + { BITVAL_EOT } + }}, + { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { + { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, + { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, + { BITVAL_EOT } + }}, + { 59, 20, RESERVED }, + { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + { 0x10000025, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU0_P2D_BM5", "GLIU0 P2D Base Mask Descriptor 5", { + { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, { + { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, + { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, + { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, + { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, + { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, + { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, + { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, + { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, + { BITVAL_EOT } + }}, + { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { + { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, + { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, + { BITVAL_EOT } + }}, + { 59, 20, RESERVED }, + { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + { 0x10000026, MSRTYPE_RDWR, MSR2(0x00000FF0, 0xFFF00000), "GLIU0_P2D_BMO0", "GLIU0 P2D Base Mask Offset Descriptor 0", { + { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, { + { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, + { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, + { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, + { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, + { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, + { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, + { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, + { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, + { BITVAL_EOT } + }}, + { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { + { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, + { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, + { BITVAL_EOT } + }}, + { 59, 20, "POFFSET", "Physical Memory Address 2s Comp Offset", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + { 0x10000027, MSRTYPE_RDWR, MSR2(0x00000FF0, 0xFFF00000), "GLIU0_P2D_BMO1", "GLIU0 P2D Base Mask Offset Descriptor 1", { + { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, { + { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, + { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, + { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, + { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, + { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, + { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, + { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, + { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, + { BITVAL_EOT } + }}, + { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { + { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, + { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, + { BITVAL_EOT } + }}, + { 59, 20, "POFFSET", "Physical Memory Address 2s Comp Offset", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + { 0x10000028, MSRTYPE_RDWR, MSR2(0x00000000, 0x000FFFFF), "GLIU0_P2D_R0", "GLIU0 P2D Range Descriptor 0", { + { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, { + { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, + { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, + { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, + { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, + { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, + { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, + { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, + { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, + { BITVAL_EOT } + }}, + { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { + { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, + { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, + { BITVAL_EOT } + }}, + { 59, 20, RESERVED }, + { 39, 20, "PMAX", "Physical Memory Address Max.", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 19, 20, "PMIN", "Physical Memory Address Min.", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + { 0x10000029, MSRTYPE_RDWR, MSR2(0x00000000, 0x000FFFFF), "GLIU0_P2D_RO0", "GLIU0 P2D Range Offset Descriptor 0", { + { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, { + { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, + { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, + { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, + { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, + { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, + { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, + { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, + { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, + { BITVAL_EOT } + }}, + { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { + { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, + { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, + { BITVAL_EOT } + }}, + { 59, 20, "POFFSET", "Physical Memory Address 2s Comp Offset", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 39, 20, "PMAX", "Physical Memory Address Max.", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 19, 20, "PMIN", "Physical Memory Address Min.", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + { 0x1000002A, MSRTYPE_RDWR, MSR2(0x00000000, 0x000FFFFF), "GLIU0_P2D_RO1", "GLIU0 P2D Range Offset Descriptor 1", { + { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, { + { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, + { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, + { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, + { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, + { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, + { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, + { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, + { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, + { BITVAL_EOT } + }}, + { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { + { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, + { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, + { BITVAL_EOT } + }}, + { 59, 20, "POFFSET", "Physical Memory Address 2s Comp Offset", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 39, 20, "PMAX", "Physical Memory Address Max.", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 19, 20, "PMIN", "Physical Memory Address Min.", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + { 0x1000002B, MSRTYPE_RDWR, MSR2(0x00000000, 0x000FFFFF), "GLIU0_P2D_RO2", "GLIU0 P2D Range Offset Descriptor 2", { + { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, { + { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, + { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, + { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, + { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, + { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, + { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, + { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, + { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, + { BITVAL_EOT } + }}, + { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { + { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, + { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, + { BITVAL_EOT } + }}, + { 59, 20, "POFFSET", "Physical Memory Address 2s Comp Offset", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 39, 20, "PMAX", "Physical Memory Address Max.", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 19, 20, "PMIN", "Physical Memory Address Min.", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + { 0x1000002C, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU0_P2D_SC0", "GLIU0 P2D Swiss Cheese Descriptor 0", { + { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, { + { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, + { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, + { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, + { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, + { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, + { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, + { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, + { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, + { BITVAL_EOT } + }}, + { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { + { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, + { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, + { BITVAL_EOT } + }}, + { 59, 12, RESERVED }, + { 47, 16, "WEN", "Enable hits to the base for the ith 16K page for writes", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 31, 16, "REN", "Enable hits to the base for the ith 16K page for ", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 15, 2, RESERVED }, + { 13, 14, "PSCBASE", "Physical Memory Address Base for hit", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + { 0x100000E0, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU0_IOD_BM0", "GLIU0 IOD Base Mask Descriptor 0", { + { 63, 3, "IDID", "IO Descriptor Destination ID", PRESENT_BIN, { + { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, + { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, + { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, + { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, + { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, + { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, + { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, + { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, + { BITVAL_EOT } + }}, + { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { + { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, + { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, + { BITVAL_EOT } + }}, + { 59, 20, RESERVED }, + { 39, 20, "IBASE", "Physical IO Address Base", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 19, 20, "IMASK", "Physical IO Address Mask", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + { 0x100000E1, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU0_IOD_BM1", "GLIU0 IOD Base Mask Descriptor 1", { + { 63, 3, "IDID", "IO Descriptor Destination ID", PRESENT_BIN, { + { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, + { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, + { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, + { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, + { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, + { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, + { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, + { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, + { BITVAL_EOT } + }}, + { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { + { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, + { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, + { BITVAL_EOT } + }}, + { 59, 20, RESERVED }, + { 39, 20, "IBASE", "Physical IO Address Base", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 19, 20, "IMASK", "Physical IO Address Mask", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + { 0x100000E2, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU0_IOD_BM2", "GLIU0 IOD Base Mask Descriptor 2", { + { 63, 3, "IDID", "IO Descriptor Destination ID", PRESENT_BIN, { + { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, + { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, + { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, + { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, + { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, + { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, + { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, + { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, + { BITVAL_EOT } + }}, + { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { + { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, + { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, + { BITVAL_EOT } + }}, + { 59, 20, RESERVED }, + { 39, 20, "IBASE", "Physical IO Address Base", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 19, 20, "IMASK", "Physical IO Address Mask", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + { 0x100000E3, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU0_IOD_SC0", "GLIU0 IOD Swiss Cheese Descriptor 0", { + { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { + { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, + { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, + { BITVAL_EOT } + }}, + { 59, 28, RESERVED }, + { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 23, 2, RESERVED }, + { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 2, 3, RESERVED }, + { BITS_EOT } + }}, + { 0x100000E4, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU0_IOD_SC1", "GLIU0 IOD Swiss Cheese Descriptor 1", { + { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { + { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, + { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, + { BITVAL_EOT } + }}, + { 59, 28, RESERVED }, + { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 23, 2, RESERVED }, + { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 2, 3, RESERVED }, + { BITS_EOT } + }}, + { 0x100000E5, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU0_IOD_SC2", "GLIU0 IOD Swiss Cheese Descriptor 2", { + { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { + { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, + { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, + { BITVAL_EOT } + }}, + { 59, 28, RESERVED }, + { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 23, 2, RESERVED }, + { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 2, 3, RESERVED }, + { BITS_EOT } + }}, + { 0x100000E6, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU0_IOD_SC3", "GLIU0 IOD Swiss Cheese Descriptor 3", { + { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { + { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, + { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, + { BITVAL_EOT } + }}, + { 59, 28, RESERVED }, + { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 23, 2, RESERVED }, + { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 2, 3, RESERVED }, + { BITS_EOT } + }}, + { 0x100000E7, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU0_IOD_SC4", "GLIU0 IOD Swiss Cheese Descriptor 4", { + { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { + { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, + { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, + { BITVAL_EOT } + }}, + { 59, 28, RESERVED }, + { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 23, 2, RESERVED }, + { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 2, 3, RESERVED }, + { BITS_EOT } + }}, + { 0x100000E8, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU0_IOD_SC5", "GLIU0 IOD Swiss Cheese Descriptor 5", { + { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { + { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, + { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, + { BITVAL_EOT } + }}, + { 59, 28, RESERVED }, + { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 23, 2, RESERVED }, + { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 2, 3, RESERVED }, + { BITS_EOT } + }}, { 0x20000018, MSRTYPE_RDWR, MSR2(0x10071007, 0x40), "MC_CF07_DATA", "Refresh and SDRAM Program", { { 63, 4, "D1_SZ", "DIMM1 Size", PRESENT_BIN, { { MSR1(0), "Reserved" }, @@ -408,6 +994,608 @@ { 4, 5, RESERVED }, { BITS_EOT } }}, + { 0x40000020, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_P2D_BM0", "GLIU1 P2D Base Mask Descriptor 0", { + { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, { + { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, + { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, + { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, + { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, + { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, + { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, + { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, + { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, + { BITVAL_EOT } + }}, + { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { + { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, + { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, + { BITVAL_EOT } + }}, + { 59, 20, RESERVED }, + { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + { 0x40000021, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_P2D_BM1", "GLIU1 P2D Base Mask Descriptor 1", { + { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, { + { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, + { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, + { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, + { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, + { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, + { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, + { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, + { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, + { BITVAL_EOT } + }}, + { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { + { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, + { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, + { BITVAL_EOT } + }}, + { 59, 20, RESERVED }, + { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + { 0x40000022, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_P2D_BM2", "GLIU1 P2D Base Mask Descriptor 2", { + { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, { + { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, + { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, + { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, + { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, + { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, + { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, + { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, + { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, + { BITVAL_EOT } + }}, + { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { + { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, + { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, + { BITVAL_EOT } + }}, + { 59, 20, RESERVED }, + { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + { 0x40000023, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_P2D_BM3", "GLIU1 P2D Base Mask Descriptor 3", { + { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, { + { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, + { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, + { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, + { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, + { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, + { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, + { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, + { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, + { BITVAL_EOT } + }}, + { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { + { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, + { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, + { BITVAL_EOT } + }}, + { 59, 20, RESERVED }, + { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + { 0x40000024, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_P2D_BM4", "GLIU1 P2D Base Mask Descriptor 4", { + { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, { + { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, + { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, + { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, + { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, + { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, + { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, + { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, + { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, + { BITVAL_EOT } + }}, + { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { + { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, + { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, + { BITVAL_EOT } + }}, + { 59, 20, RESERVED }, + { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + { 0x40000025, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_P2D_BM5", "GLIU1 P2D Base Mask Descriptor 5", { + { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, { + { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, + { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, + { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, + { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, + { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, + { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, + { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, + { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, + { BITVAL_EOT } + }}, + { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { + { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, + { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, + { BITVAL_EOT } + }}, + { 59, 20, RESERVED }, + { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + { 0x40000026, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_P2D_BM6", "GLIU1 P2D Base Mask Descriptor 6", { + { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, { + { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, + { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, + { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, + { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, + { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, + { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, + { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, + { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, + { BITVAL_EOT } + }}, + { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { + { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, + { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, + { BITVAL_EOT } + }}, + { 59, 20, RESERVED }, + { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + { 0x40000027, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_P2D_BM7", "GLIU1 P2D Base Mask Descriptor 7", { + { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, { + { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, + { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, + { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, + { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, + { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, + { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, + { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, + { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, + { BITVAL_EOT } + }}, + { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { + { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, + { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, + { BITVAL_EOT } + }}, + { 59, 20, RESERVED }, + { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + { 0x40000028, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_P2D_BM8", "GLIU1 P2D Base Mask Descriptor 8", { + { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, { + { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, + { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, + { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, + { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, + { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, + { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, + { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, + { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, + { BITVAL_EOT } + }}, + { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { + { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, + { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, + { BITVAL_EOT } + }}, + { 59, 20, RESERVED }, + { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + { 0x40000029, MSRTYPE_RDWR, MSR2(0x00000000, 0x000FFFFF), "GLIU1_P2D_R0", "GLIU0 P2D Range Descriptor 0", { + { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, { + { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, + { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, + { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, + { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, + { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, + { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, + { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, + { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, + { BITVAL_EOT } + }}, + { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { + { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, + { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, + { BITVAL_EOT } + }}, + { 59, 20, RESERVED }, + { 39, 20, "PMAX", "Physical Memory Address Max.", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 19, 20, "PMIN", "Physical Memory Address Min.", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + { 0x4000002A, MSRTYPE_RDWR, MSR2(0x00000000, 0x000FFFFF), "GLIU1_P2D_R1", "GLIU0 P2D Range Descriptor 1", { + { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, { + { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, + { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, + { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, + { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, + { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, + { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, + { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, + { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, + { BITVAL_EOT } + }}, + { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { + { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, + { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, + { BITVAL_EOT } + }}, + { 59, 20, RESERVED }, + { 39, 20, "PMAX", "Physical Memory Address Max.", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 19, 20, "PMIN", "Physical Memory Address Min.", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + { 0x4000002B, MSRTYPE_RDWR, MSR2(0x00000000, 0x000FFFFF), "GLIU0_P2D_R2", "GLIU0 P2D Range Descriptor 2", { + { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, { + { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, + { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, + { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, + { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, + { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, + { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, + { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, + { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, + { BITVAL_EOT } + }}, + { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { + { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, + { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, + { BITVAL_EOT } + }}, + { 59, 20, RESERVED }, + { 39, 20, "PMAX", "Physical Memory Address Max.", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 19, 20, "PMIN", "Physical Memory Address Min.", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + { 0x4000002C, MSRTYPE_RDWR, MSR2(0x00000000, 0x000FFFFF), "GLIU0_P2D_R3", "GLIU0 P2D Range Descriptor 3", { + { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, { + { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, + { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, + { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, + { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, + { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, + { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, + { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, + { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, + { BITVAL_EOT } + }}, + { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { + { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, + { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, + { BITVAL_EOT } + }}, + { 59, 20, RESERVED }, + { 39, 20, "PMAX", "Physical Memory Address Max.", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 19, 20, "PMIN", "Physical Memory Address Min.", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + { 0x4000002D, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU1_P2D_SC0", "GLIU1 P2D Swiss Cheese Descriptor 0", { + { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, { + { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, + { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, + { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, + { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, + { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, + { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, + { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, + { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, + { BITVAL_EOT } + }}, + { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { + { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, + { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, + { BITVAL_EOT } + }}, + { 59, 12, RESERVED }, + { 47, 16, "WEN", "Enable hits to the base for the ith 16K page for writes", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 31, 16, "REN", "Enable hits to the base for the ith 16K page for ", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 15, 2, RESERVED }, + { 13, 14, "PSCBASE", "Physical Memory Address Base for hit", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + { 0x400000E0, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_IOD_BM0", "GLIU1 IOD Base Mask Descriptor 0", { + { 63, 3, "IDID", "IO Descriptor Destination ID", PRESENT_BIN, { + { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, + { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, + { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, + { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, + { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, + { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, + { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, + { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, + { BITVAL_EOT } + }}, + { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { + { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, + { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, + { BITVAL_EOT } + }}, + { 59, 20, RESERVED }, + { 39, 20, "IBASE", "Physical IO Address Base", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 19, 20, "IMASK", "Physical IO Address Mask", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + { 0x400000E1, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_IOD_BM1", "GLIU1 IOD Base Mask Descriptor 1", { + { 63, 3, "IDID", "IO Descriptor Destination ID", PRESENT_BIN, { + { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, + { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, + { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, + { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, + { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, + { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, + { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, + { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, + { BITVAL_EOT } + }}, + { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { + { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, + { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, + { BITVAL_EOT } + }}, + { 59, 20, RESERVED }, + { 39, 20, "IBASE", "Physical IO Address Base", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 19, 20, "IMASK", "Physical IO Address Mask", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + { 0x400000E2, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_IOD_BM2", "GLIU1 IOD Base Mask Descriptor 2", { + { 63, 3, "IDID", "IO Descriptor Destination ID", PRESENT_BIN, { + { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" }, + { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" }, + { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" }, + { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" }, + { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" }, + { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" }, + { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" }, + { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" }, + { BITVAL_EOT } + }}, + { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { + { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, + { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, + { BITVAL_EOT } + }}, + { 59, 20, RESERVED }, + { 39, 20, "IBASE", "Physical IO Address Base", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 19, 20, "IMASK", "Physical IO Address Mask", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + { 0x400000E3, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU1_IOD_SC0", "GLIU1 IOD Swiss Cheese Descriptor 0", { + { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { + { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, + { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, + { BITVAL_EOT } + }}, + { 59, 28, RESERVED }, + { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 23, 2, RESERVED }, + { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 2, 3, RESERVED }, + { BITS_EOT } + }}, + { 0x400000E4, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU1_IOD_SC1", "GLIU1 IOD Swiss Cheese Descriptor 1", { + { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { + { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, + { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, + { BITVAL_EOT } + }}, + { 59, 28, RESERVED }, + { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 23, 2, RESERVED }, + { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 2, 3, RESERVED }, + { BITS_EOT } + }}, + { 0x400000E5, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU1_IOD_SC2", "GLIU1 IOD Swiss Cheese Descriptor 2", { + { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { + { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, + { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, + { BITVAL_EOT } + }}, + { 59, 28, RESERVED }, + { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 23, 2, RESERVED }, + { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 2, 3, RESERVED }, + { BITS_EOT } + }}, + { 0x400000E6, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU1_IOD_SC3", "GLIU1 IOD Swiss Cheese Descriptor 3", { + { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { + { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, + { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, + { BITVAL_EOT } + }}, + { 59, 28, RESERVED }, + { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 23, 2, RESERVED }, + { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 2, 3, RESERVED }, + { BITS_EOT } + }}, + { 0x400000E7, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU1_IOD_SC4", "GLIU1 IOD Swiss Cheese Descriptor 4", { + { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { + { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, + { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, + { BITVAL_EOT } + }}, + { 59, 28, RESERVED }, + { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 23, 2, RESERVED }, + { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 2, 3, RESERVED }, + { BITS_EOT } + }}, + { 0x400000E8, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU1_IOD_SC5", "GLIU1 IOD Swiss Cheese Descriptor 5", { + { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, { + { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" }, + { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" }, + { BITVAL_EOT } + }}, + { 59, 28, RESERVED }, + { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 23, 2, RESERVED }, + { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 2, 3, RESERVED }, + { BITS_EOT } + }}, { 0x4c00000f, MSRTYPE_RDWR, MSR2(0, 0), "GLCP_DELAY_CONTROLS", "GLCP I/O Delay Controls", { { 63, 1, "EN", "Delay Settings Enable", PRESENT_DEC, { { MSR1(0), "Use default values" },

1 0

[commit] r6273 - in trunk/src: cpu/amd/car cpu/intel/car cpu/intel/model_106cx cpu/intel/model_6ex cpu/intel/model_6fx cpu/via/car include/cpu/x86
by repository service 19 Jan '11

19 Jan '11

Author: stepan Date: Wed Jan 19 07:54:42 2011 New Revision: 6273 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6273 Log: Revert r5902 to make code more readable again. At least three people like to have this go away again. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Kevin O'Connor <kevin(a)koconnor.net> Deleted: trunk/src/include/cpu/x86/car.h Modified: trunk/src/cpu/amd/car/cache_as_ram.inc trunk/src/cpu/intel/car/cache_as_ram.inc trunk/src/cpu/intel/model_106cx/cache_as_ram.inc trunk/src/cpu/intel/model_6ex/cache_as_ram.inc trunk/src/cpu/intel/model_6fx/cache_as_ram.inc trunk/src/cpu/via/car/cache_as_ram.inc Modified: trunk/src/cpu/amd/car/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/amd/car/cache_as_ram.inc Wed Jan 19 07:32:35 2011 (r6272) +++ trunk/src/cpu/amd/car/cache_as_ram.inc Wed Jan 19 07:54:42 2011 (r6273) @@ -18,7 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <cpu/x86/car.h> #include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h> @@ -46,7 +45,8 @@ * xmm3: Backup EBX */ - save_bist_result() + /* Save the BIST result. */ + movl %eax, %ebp /* * For normal part %ebx already contain cpu_init_detected @@ -56,7 +56,10 @@ cache_as_ram_setup: post_code(0xa0) - enable_sse() + /* Enable SSE. */ + movl %cr4, %eax + orl $(3 << 9), %eax + movl %eax, %cr4 /* Figure out the CPU family. */ cvtsi2sd %ebx, %xmm3 @@ -321,7 +324,10 @@ post_code(0xa1) - enable_cache() + /* Enable cache. */ + movl %cr0, %eax + andl $(~((1 << 30) | (1 << 29))), %eax + movl %eax, %cr0 jmp_if_k8(fam10_end_part1) @@ -403,9 +409,13 @@ post_code(0xa5) - disable_sse() + /* Disable SSE. */ + movl %cr4, %eax + andl $~(3 << 9), %eax + movl %eax, %cr4 - restore_bist_result() + /* Restore the BIST result. */ + movl %ebp, %eax /* We need to set EBP? No need. */ movl %esp, %ebp Modified: trunk/src/cpu/intel/car/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/car/cache_as_ram.inc Wed Jan 19 07:32:35 2011 (r6272) +++ trunk/src/cpu/intel/car/cache_as_ram.inc Wed Jan 19 07:54:42 2011 (r6273) @@ -21,7 +21,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <cpu/x86/car.h> #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/lapic_def.h> @@ -29,7 +28,8 @@ #define CacheSize CONFIG_DCACHE_RAM_SIZE #define CacheBase (0xd0000 - CacheSize) - save_bist_result() + /* Save the BIST result. */ + movl %eax, %ebp CacheAsRam: /* Check whether the processor has HT capability. */ @@ -257,7 +257,10 @@ wrmsr #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ - enable_cache() + /* Enable cache. */ + movl %cr0, %eax + andl $(~((1 << 30) | (1 << 29))), %eax + movl %eax, %cr0 /* Read the range with lodsl. */ movl $CacheBase, %esi @@ -318,7 +321,8 @@ movl $(CacheBase + CacheSize - 4), %eax movl %eax, %esp lout: - restore_bist_result() + /* Restore the BIST result. */ + movl %ebp, %eax /* We need to set EBP? No need. */ movl %esp, %ebp @@ -327,7 +331,10 @@ /* We don't need CAR from now on. */ - disable_cache() + /* Disable cache. */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 /* Clear sth. */ movl $MTRRfix4K_C8000_MSR, %ecx @@ -349,7 +356,10 @@ movl $0x00000800, %eax /* Enable variable and disable fixed MTRRs. */ wrmsr - enable_cache(); + /* Enable cache. */ + movl %cr0, %eax + andl $(~((1 << 30) | (1 << 29))), %eax + movl %eax, %cr0 /* Clear boot_complete flag. */ xorl %ebp, %ebp Modified: trunk/src/cpu/intel/model_106cx/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/model_106cx/cache_as_ram.inc Wed Jan 19 07:32:35 2011 (r6272) +++ trunk/src/cpu/intel/model_106cx/cache_as_ram.inc Wed Jan 19 07:54:42 2011 (r6273) @@ -18,14 +18,14 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <cpu/x86/car.h> #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE - save_bist_result() + /* Save the BIST result. */ + movl %eax, %ebp cache_as_ram: post_code(0x20) @@ -66,12 +66,19 @@ xorl %edx, %edx wrmsr - enable_mtrr() + /* Enable MTRR. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + orl $(1 << 11), %eax + wrmsr - enable_l2_cache() + /* Enable L2 cache. */ + movl $0x11e, %ecx + rdmsr + orl $(1 << 8), %eax + wrmsr /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ - /* TODO: enable_cache()? But that doesn't have "invd". */ movl %cr0, %eax andl $(~((1 << 30) | (1 << 29))), %eax invd @@ -86,7 +93,9 @@ rep stosl /* Enable Cache-as-RAM mode by disabling cache. */ - disable_cache() + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) /* Enable cache for our code in Flash because we do XIP here */ @@ -112,7 +121,10 @@ wrmsr #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ - enable_cache() + /* Enable cache. */ + movl %cr0, %eax + andl $(~((1 << 30) | (1 << 29))), %eax + movl %eax, %cr0 /* Set up the stack pointer. */ #if defined(CONFIG_USBDEBUG) && (CONFIG_USBDEBUG == 1) @@ -123,8 +135,8 @@ #endif movl %eax, %esp - restore_bist_result() - + /* Restore the BIST result. */ + movl %ebp, %eax movl %esp, %ebp pushl %eax @@ -137,11 +149,18 @@ post_code(0x30) - disable_cache() + /* Disable cache. */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 post_code(0x31) - disable_mtrr() + /* Disable MTRR. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + andl $(~(1 << 11)), %eax + wrmsr post_code(0x31) @@ -161,11 +180,17 @@ post_code(0x33) - enable_cache() + /* Enable cache. */ + movl %cr0, %eax + andl $~((1 << 30) | (1 << 29)), %eax + movl %eax, %cr0 post_code(0x36) - disable_cache() + /* Disable cache. */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 post_code(0x38) @@ -182,11 +207,17 @@ post_code(0x39) /* And enable cache again after setting MTRRs. */ - enable_cache() + movl %cr0, %eax + andl $~((1 << 30) | (1 << 29)), %eax + movl %eax, %cr0 post_code(0x3a) - enable_mtrr() + /* Enable MTRR. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + orl $(1 << 11), %eax + wrmsr post_code(0x3b) Modified: trunk/src/cpu/intel/model_6ex/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/model_6ex/cache_as_ram.inc Wed Jan 19 07:32:35 2011 (r6272) +++ trunk/src/cpu/intel/model_6ex/cache_as_ram.inc Wed Jan 19 07:54:42 2011 (r6273) @@ -18,14 +18,14 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <cpu/x86/car.h> #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE - save_bist_result() + /* Save the BIST result. */ + movl %eax, %ebp cache_as_ram: post_code(0x20) @@ -66,12 +66,19 @@ movl $0x0000000f, %edx wrmsr - enable_mtrr() + /* Enable MTRR. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + orl $(1 << 11), %eax + wrmsr - enable_l2_cache() + /* Enable L2 cache. */ + movl $0x11e, %ecx + rdmsr + orl $(1 << 8), %eax + wrmsr /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ - /* TODO: enable_cache()? But that doesn't have "invd". */ movl %cr0, %eax andl $(~((1 << 30) | (1 << 29))), %eax invd @@ -86,7 +93,9 @@ rep stosl /* Enable Cache-as-RAM mode by disabling cache. */ - disable_cache() + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) /* Enable cache for our code in Flash because we do XIP here */ @@ -112,7 +121,10 @@ wrmsr #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ - enable_cache() + /* Enable cache. */ + movl %cr0, %eax + andl $(~((1 << 30) | (1 << 29))), %eax + movl %eax, %cr0 /* Set up the stack pointer. */ #if defined(CONFIG_USBDEBUG) && (CONFIG_USBDEBUG == 1) @@ -123,8 +135,8 @@ #endif movl %eax, %esp - restore_bist_result() - + /* Restore the BIST result. */ + movl %ebp, %eax movl %esp, %ebp pushl %eax @@ -137,11 +149,18 @@ post_code(0x30) - disable_cache() + /* Disable cache. */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 post_code(0x31) - disable_mtrr() + /* Disable MTRR. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + andl $(~(1 << 11)), %eax + wrmsr post_code(0x31) @@ -161,11 +180,17 @@ post_code(0x33) - enable_cache() + /* Enable cache. */ + movl %cr0, %eax + andl $~((1 << 30) | (1 << 29)), %eax + movl %eax, %cr0 post_code(0x36) - disable_cache() + /* Disable cache. */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 post_code(0x38) @@ -182,11 +207,17 @@ post_code(0x39) /* And enable cache again after setting MTRRs. */ - enable_cache() + movl %cr0, %eax + andl $~((1 << 30) | (1 << 29)), %eax + movl %eax, %cr0 post_code(0x3a) - enable_mtrr() + /* Enable MTRR. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + orl $(1 << 11), %eax + wrmsr post_code(0x3b) Modified: trunk/src/cpu/intel/model_6fx/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/model_6fx/cache_as_ram.inc Wed Jan 19 07:32:35 2011 (r6272) +++ trunk/src/cpu/intel/model_6fx/cache_as_ram.inc Wed Jan 19 07:54:42 2011 (r6273) @@ -18,14 +18,14 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <cpu/x86/car.h> #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE - save_bist_result() + /* Save the BIST result. */ + movl %eax, %ebp cache_as_ram: post_code(0x20) @@ -73,12 +73,19 @@ movl $0x0000000f, %edx wrmsr - enable_mtrr() + /* Enable MTRR. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + orl $(1 << 11), %eax + wrmsr - enable_l2_cache() + /* Enable L2 cache. */ + movl $0x11e, %ecx + rdmsr + orl $(1 << 8), %eax + wrmsr /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ - /* TODO: enable_cache()? But that doesn't have "invd". */ movl %cr0, %eax andl $(~((1 << 30) | (1 << 29))), %eax invd @@ -93,7 +100,9 @@ rep stosl /* Enable Cache-as-RAM mode by disabling cache. */ - disable_cache() + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) /* Enable cache for our code in Flash because we do XIP here */ @@ -119,7 +128,10 @@ wrmsr #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ - enable_cache() + /* Enable cache. */ + movl %cr0, %eax + andl $(~((1 << 30) | (1 << 29))), %eax + movl %eax, %cr0 /* Set up the stack pointer. */ #if defined(CONFIG_USBDEBUG) && (CONFIG_USBDEBUG == 1) @@ -130,8 +142,8 @@ #endif movl %eax, %esp - restore_bist_result() - + /* Restore the BIST result. */ + movl %ebp, %eax movl %esp, %ebp pushl %eax @@ -144,11 +156,18 @@ post_code(0x30) - disable_cache() + /* Disable cache. */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 post_code(0x31) - disable_mtrr() + /* Disable MTRR. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + andl $(~(1 << 11)), %eax + wrmsr post_code(0x31) @@ -168,11 +187,17 @@ post_code(0x33) - enable_cache() + /* Enable cache. */ + movl %cr0, %eax + andl $~((1 << 30) | (1 << 29)), %eax + movl %eax, %cr0 post_code(0x36) - disable_cache() + /* Disable cache. */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 post_code(0x38) @@ -189,11 +214,17 @@ post_code(0x39) /* And enable cache again after setting MTRRs. */ - enable_cache() + movl %cr0, %eax + andl $~((1 << 30) | (1 << 29)), %eax + movl %eax, %cr0 post_code(0x3a) - enable_mtrr() + /* Enable MTRR. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + orl $(1 << 11), %eax + wrmsr post_code(0x3b) Modified: trunk/src/cpu/via/car/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/via/car/cache_as_ram.inc Wed Jan 19 07:32:35 2011 (r6272) +++ trunk/src/cpu/via/car/cache_as_ram.inc Wed Jan 19 07:54:42 2011 (r6273) @@ -25,18 +25,21 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <cpu/x86/car.h> #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> #define CacheSize CONFIG_DCACHE_RAM_SIZE #define CacheBase CONFIG_DCACHE_RAM_BASE - save_bist_result() + /* Save the BIST result. */ + movl %eax, %ebp CacheAsRam: - disable_cache() + /* Disable cache. */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 invd /* Set the default memory type and enable fixed and variable MTRRs. */ @@ -139,7 +142,10 @@ movl $(MTRRdefTypeEn), %eax wrmsr - enable_cache() + /* Enable cache. */ + movl %cr0, %eax + andl $(~((1 << 30) | (1 << 29))), %eax + movl %eax, %cr0 /* Read the range with lodsl. */ cld @@ -195,7 +201,8 @@ jne stackerr #endif - restore_bist_result() + /* Restore the BIST result. */ + movl %ebp, %eax /* We need to set EBP? No need. */ movl %esp, %ebp @@ -210,7 +217,10 @@ /* We don't need CAR from now on. */ - disable_cache() + /* Disable cache. */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 /* Set the default memory type and enable variable MTRRs. */ /* TODO: Or also enable fixed MTRRs? Bug in the code? */ @@ -242,7 +252,10 @@ movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax wrmsr - enable_cache() + /* Enable cache. */ + movl %cr0, %eax + andl $(~((1 << 30) | (1 << 29))), %eax + movl %eax, %cr0 invd /* Clear boot_complete flag. */

1 0

[commit] r6271 - trunk/src/arch/x86/include/arch
by repository service 19 Jan '11

19 Jan '11

Author: stepan Date: Wed Jan 19 07:31:24 2011 New Revision: 6271 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6271 Log: The cn700.c code references mainboard_interrupt_handlers() which isn't defined if VGA_ROM_RUN is off. Define a dummy implementation of that function for this case. Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> Acked-by: Stefan Reinauer <stepan(a)coreboot.org> Modified: trunk/src/arch/x86/include/arch/interrupt.h Modified: trunk/src/arch/x86/include/arch/interrupt.h ============================================================================== --- trunk/src/arch/x86/include/arch/interrupt.h Tue Jan 18 15:38:59 2011 (r6270) +++ trunk/src/arch/x86/include/arch/interrupt.h Wed Jan 19 07:31:24 2011 (r6271) @@ -22,4 +22,8 @@ #include "registers.h" /* setup interrupt handlers for mainboard */ +#if defined(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) && CONFIG_PCI_OPTION_ROM_RUN_REALMODE extern void mainboard_interrupt_handlers(int intXX, void *intXX_func); +#else +static inline void mainboard_interrupt_handlers(int intXX, void *intXX_func) { } +#endif

3 2

[commit] r6272 - in trunk/src: cpu/via/car cpu/x86/mtrr include/cpu/x86
by repository service 19 Jan '11

19 Jan '11

Author: stepan Date: Wed Jan 19 07:32:35 2011 New Revision: 6272 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6272 Log: Now that the VIA code is run above 1Meg (like other boards), it should cache that range instead of the first 1Meg. This reduces boot time by about 1 second on epia-cn. This patch also adds a MTRRphysMaskValid bit definition. Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> Acked-by: Stefan Reinauer <stepan(a)coreboot.org> Modified: trunk/src/cpu/via/car/cache_as_ram.inc trunk/src/cpu/x86/mtrr/mtrr.c trunk/src/include/cpu/x86/mtrr.h Modified: trunk/src/cpu/via/car/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/via/car/cache_as_ram.inc Wed Jan 19 07:31:24 2011 (r6271) +++ trunk/src/cpu/via/car/cache_as_ram.inc Wed Jan 19 07:32:35 2011 (r6272) @@ -103,7 +103,7 @@ movl $MTRRphysMask_MSR(0), %ecx /* This assumes we never access addresses above 2^36 in CAR. */ movl $0x0000000f, %edx - movl $(~(CacheSize - 1) | 0x800), %eax + movl $(~(CacheSize - 1) | MTRRphysMaskValid), %eax wrmsr #if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK @@ -129,7 +129,7 @@ movl $MTRRphysMask_MSR(1), %ecx movl $0x0000000f, %edx - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax wrmsr /* Set the default memory type and enable fixed and variable MTRRs. */ @@ -219,54 +219,27 @@ movl $(MTRRdefTypeEn), %eax wrmsr - /* Enable caching for first 1M using variable MTRR. */ + /* Enable caching for CONFIG_RAMBASE..CONFIG_RAMTOP. */ movl $MTRRphysBase_MSR(0), %ecx xorl %edx, %edx - movl $(0 | MTRR_TYPE_WRBACK), %eax + movl $(CONFIG_RAMBASE | MTRR_TYPE_WRBACK), %eax wrmsr - /* - * Enable cache for 0-7ffff, 80000-9ffff, e0000-fffff; - * If 1M cacheable, then when S3 resume, there is stange color on - * screen for 2 sec. Suppose problem of a0000-dfffff and cache. - * And in x86_setup_fixed_mtrrs()(mtrr.c), 0-256M is set cacheable. - */ - movl $MTRRphysMask_MSR(0), %ecx movl $0x0000000f, %edx /* AMD 40 bit 0xff */ - movl $((~((0 + 0x80000) - 1)) | 0x800), %eax - wrmsr - - movl $MTRRphysBase_MSR(1), %ecx - xorl %edx, %edx - movl $(0x80000 | MTRR_TYPE_WRBACK), %eax - wrmsr - - movl $MTRRphysMask_MSR(1), %ecx - movl $0x0000000f, %edx /* AMD 40 bit 0xff */ - movl $((~((0 + 0x20000) - 1)) | 0x800), %eax - wrmsr - - movl $MTRRphysBase_MSR(2), %ecx - xorl %edx, %edx - movl $(0xc0000 | MTRR_TYPE_WRBACK), %eax - wrmsr - - movl $MTRRphysMask_MSR(2), %ecx - movl $0x0000000f, %edx /* AMD 40 bit 0xff */ - movl $((~(( 0 + 0x40000) - 1)) | 0x800), %eax + movl $(~(CONFIG_RAMTOP - CONFIG_RAMBASE - 1) | MTRRphysMaskValid), %eax wrmsr /* Cache XIP_ROM_BASE-SIZE to speedup coreboot code. */ - movl $MTRRphysBase_MSR(3), %ecx + movl $MTRRphysBase_MSR(1), %ecx xorl %edx, %edx movl $REAL_XIP_ROM_BASE, %eax orl $MTRR_TYPE_WRBACK, %eax wrmsr - movl $MTRRphysMask_MSR(3), %ecx + movl $MTRRphysMask_MSR(1), %ecx xorl %edx, %edx - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax wrmsr enable_cache() Modified: trunk/src/cpu/x86/mtrr/mtrr.c ============================================================================== --- trunk/src/cpu/x86/mtrr/mtrr.c Wed Jan 19 07:31:24 2011 (r6271) +++ trunk/src/cpu/x86/mtrr/mtrr.c Wed Jan 19 07:32:35 2011 (r6272) @@ -62,7 +62,7 @@ msr_t msr; msr = rdmsr(MTRRdefType_MSR); - msr.lo |= 0x800; + msr.lo |= MTRRdefTypeEn; wrmsr(MTRRdefType_MSR, msr); } @@ -115,7 +115,7 @@ /* Bit 32-35 of MTRRphysMask should be set to 1 */ base.lo |= type; - mask.lo |= 0x800; + mask.lo |= MTRRphysMaskValid; wrmsr (MTRRphysBase_MSR(reg), base); wrmsr (MTRRphysMask_MSR(reg), mask); Modified: trunk/src/include/cpu/x86/mtrr.h ============================================================================== --- trunk/src/include/cpu/x86/mtrr.h Wed Jan 19 07:31:24 2011 (r6271) +++ trunk/src/include/cpu/x86/mtrr.h Wed Jan 19 07:32:35 2011 (r6272) @@ -21,6 +21,8 @@ #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg)) #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1) +#define MTRRphysMaskValid (1 << 11) + #define NUM_FIXED_RANGES 88 #define MTRRfix64K_00000_MSR 0x250 #define MTRRfix16K_80000_MSR 0x258

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Licensing question
by Vibrans, Frank 18 Jan '11

18 Jan '11

Hi All, The Open Source Review Board of AMD has decided the upcoming release of Agesa and the chipset CIM modules for our Family14h CPU will be under a dual license: GPLv2 and BSD. As the coreboot community, do you have any issue with this? If not, are there any specific coreboot requirements that must be met because of the dual license scheme? Thanks for your help. Frank Vibrans

7 8

[PATCH]Move option table to CBFS
by Patrick Georgi 18 Jan '11

18 Jan '11

Hi, currently the option table (which contains the metadata necessary to parse CMOS data properly) is stored in ramstage. This patch moves it to CBFS, making it available for inspection by utilities. The idea is to allow nvramtool to configure cmos defaults (which are stored in CBFS) by using the table (also stored in CBFS). This requires some changes to nvramtool, but this is the only necessary change in coreboot to allow this. The downside is that cmos_layout.bin is not compressed, while ramstage (and thus the layout information it contained) usually is. With layout data being 2kb or less that shouldn't be much of an issue. Right now, the table is copied into cbtable by coreboot, like it used to. It would be possible to just link it to the end of cbtable, making the chain run into flash space, but I didn't do that to minimize the impact of this patch. I'm not sure if reducing cbtable's RAM use by 2kb is worth the potential trouble. Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com>

4 7

[commit] r6270 - trunk/util/options
by repository service 18 Jan '11

18 Jan '11

Author: oxygene Date: Tue Jan 18 15:38:59 2011 New Revision: 6270 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6270 Log: Fix fwrite tests. Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Acked-by: Patrick Georgi <patrick.georgi(a)secunet.com> Modified: trunk/util/options/build_opt_tbl.c Modified: trunk/util/options/build_opt_tbl.c ============================================================================== --- trunk/util/options/build_opt_tbl.c Tue Jan 18 15:28:45 2011 (r6269) +++ trunk/util/options/build_opt_tbl.c Tue Jan 18 15:38:59 2011 (r6270) @@ -541,7 +541,7 @@ } /* write the header */ - if(!fwrite("unsigned char option_table[] = {",1,32,fp)) { + if(fwrite("unsigned char option_table[] = {",1,32,fp) != 32) { perror("Error - Could not write image file"); fclose(fp); unlink(tempfilename); @@ -549,14 +549,14 @@ } /* write the array values */ for(i=0; i<(int)(ct->size-1); i++) { - if(!(i%10) && !err) err=!fwrite("\n\t",1,2,fp); + if(!(i%10) && !err) err=(fwrite("\n\t",1,2,fp) != 2); sprintf(buf,"0x%02x,",cmos_table[i]); - if(!err) err=!fwrite(buf,1,5,fp); + if(!err) err=(fwrite(buf,1,5,fp) != 5); } /* write the end */ sprintf(buf,"0x%02x\n",cmos_table[i]); - if(!err) err=!fwrite(buf,1,4,fp); - if(!fwrite("};\n",1,3,fp)) { + if(!err) err=(fwrite(buf,1,4,fp) != 4); + if(fwrite("};\n",1,3,fp) != 3) { perror("Error - Could not write image file"); fclose(fp); unlink(tempfilename); @@ -590,7 +590,7 @@ } /* write the array values */ - if(!fwrite(cmos_table, (int)(ct->size-1), 1, fp)) { + if(fwrite(cmos_table, (int)(ct->size-1), 1, fp) != 1) { perror("Error - Could not write image file"); fclose(fp); unlink(tempfilename);

1 0

[commit] r6269 - in trunk/src: arch/x86/boot pc80
by repository service 18 Jan '11

18 Jan '11

Author: oxygene Date: Tue Jan 18 15:28:45 2011 New Revision: 6269 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6269 Log: Report if cmos_layout.bin can't be found when it should. Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Acked-by: Patrick Georgi <patrick.georgi(a)secunet.com> Modified: trunk/src/arch/x86/boot/coreboot_table.c trunk/src/pc80/mc146818rtc.c Modified: trunk/src/arch/x86/boot/coreboot_table.c ============================================================================== --- trunk/src/arch/x86/boot/coreboot_table.c Tue Jan 18 14:56:36 2011 (r6268) +++ trunk/src/arch/x86/boot/coreboot_table.c Tue Jan 18 15:28:45 2011 (r6269) @@ -549,6 +549,8 @@ memcpy(rec_dest, &option_table, option_table.size); /* Create cmos checksum entry in coreboot table */ lb_cmos_checksum(head); + } else { + printk(BIOS_ERR, "cmos_layout.bin could not be found!\n"); } } #endif Modified: trunk/src/pc80/mc146818rtc.c ============================================================================== --- trunk/src/pc80/mc146818rtc.c Tue Jan 18 14:56:36 2011 (r6268) +++ trunk/src/pc80/mc146818rtc.c Tue Jan 18 15:28:45 2011 (r6269) @@ -228,6 +228,10 @@ /* find the requested entry record */ ct=cbfs_find_file("cmos_layout.bin", CMOS_COMPONENT_CMOS_LAYOUT); + if (!ct) { + printk(BIOS_ERR, "cmos_layout.bin could not be found. Options are disabled\n"); + return(-2); + } ce=(struct cmos_entries*)((unsigned char *)ct + ct->header_length); for(;ce->tag==LB_TAG_OPTION; ce=(struct cmos_entries*)((unsigned char *)ce + ce->size)) {

1 0

[commit] r6268 - in trunk: src/arch/x86 src/arch/x86/boot src/arch/x86/include/arch src/include src/pc80 util/cbfstool util/options
by repository service 18 Jan '11

18 Jan '11

Author: oxygene Date: Tue Jan 18 14:56:36 2011 New Revision: 6268 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6268 Log: Move option table (cmos.layout's binary representation) to CBFS and adapt coreboot to use it. Comments by Stefan and Mathias taken into account (except for the build time failure if the table is missing when it should exist and the "memory leak" in build_opt_tbl) Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Acked-by: Stefan Reinauer <stepan(a)coreboot.org> Modified: trunk/src/arch/x86/Makefile.inc trunk/src/arch/x86/boot/coreboot_table.c trunk/src/arch/x86/include/arch/coreboot_tables.h trunk/src/include/cbfs.h trunk/src/pc80/mc146818rtc.c trunk/src/pc80/mc146818rtc_early.c trunk/util/cbfstool/cbfs.h trunk/util/options/build_opt_tbl.c Modified: trunk/src/arch/x86/Makefile.inc ============================================================================== --- trunk/src/arch/x86/Makefile.inc Tue Jan 18 13:14:08 2011 (r6267) +++ trunk/src/arch/x86/Makefile.inc Tue Jan 18 14:56:36 2011 (r6268) @@ -27,7 +27,10 @@ OPTION_TABLE_H:= ifeq ($(CONFIG_HAVE_OPTION_TABLE),y) -ramstage-srcs += $(obj)/option_table.c +cbfs-files-y += $(obj)/cmos_layout.bin +$(obj)/cmos_layout.bin-name = cmos_layout.bin +$(obj)/cmos_layout.bin-type = 0x01aa + OPTION_TABLE_H:=$(obj)/option_table.h endif @@ -64,7 +67,7 @@ $(CBFSTOOL) $@ add $(call extract_nth,1,$(file)) $(call extract_nth,2,$(file)) $(call extract_nth,3,$(file)) $(call extract_nth,4,$(file)); ) prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file))) -$(obj)/coreboot.pre1: $(obj)/coreboot.bootblock $(prebuilt-files) $(CBFSTOOL) +$(obj)/coreboot.pre1: $(obj)/coreboot.bootblock $$(prebuilt-files) $(CBFSTOOL) rm -f $@ $(CBFSTOOL) $@ create $(CONFIG_COREBOOT_ROMSIZE_KB)K $(obj)/coreboot.bootblock $(prebuild-files) @@ -121,9 +124,9 @@ @printf " OPTION $(subst $(obj)/,,$(@))\n" $(objutil)/options/build_opt_tbl --config $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout --header $@ -$(obj)/option_table.c: $(objutil)/options/build_opt_tbl $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout +$(obj)/cmos_layout.bin: $(objutil)/options/build_opt_tbl $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout @printf " OPTION $(subst $(obj)/,,$(@))\n" - $(objutil)/options/build_opt_tbl --config $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout --option $@ + $(objutil)/options/build_opt_tbl --config $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout --binary $@ $(objutil)/options/build_opt_tbl: $(top)/util/options/build_opt_tbl.c $(top)/src/include/pc80/mc146818rtc.h $(top)/src/include/boot/coreboot_tables.h @printf " HOSTCC $(subst $(obj)/,,$(@))\n" Modified: trunk/src/arch/x86/boot/coreboot_table.c ============================================================================== --- trunk/src/arch/x86/boot/coreboot_table.c Tue Jan 18 13:14:08 2011 (r6267) +++ trunk/src/arch/x86/boot/coreboot_table.c Tue Jan 18 14:56:36 2011 (r6268) @@ -542,11 +542,14 @@ #if (CONFIG_USE_OPTION_TABLE == 1) { - struct lb_record *rec_dest = lb_new_record(head); - /* Copy the option config table, it's already a lb_record... */ - memcpy(rec_dest, &option_table, option_table.size); - /* Create cmos checksum entry in coreboot table */ - lb_cmos_checksum(head); + struct cmos_option_table option_table = cbfs_find_file("cmos_layout.bin", 0x1aa); + if (option_table) { + struct lb_record *rec_dest = lb_new_record(head); + /* Copy the option config table, it's already a lb_record... */ + memcpy(rec_dest, &option_table, option_table.size); + /* Create cmos checksum entry in coreboot table */ + lb_cmos_checksum(head); + } } #endif /* Record where RAM is located */ Modified: trunk/src/arch/x86/include/arch/coreboot_tables.h ============================================================================== --- trunk/src/arch/x86/include/arch/coreboot_tables.h Tue Jan 18 13:14:08 2011 (r6267) +++ trunk/src/arch/x86/include/arch/coreboot_tables.h Tue Jan 18 14:56:36 2011 (r6268) @@ -16,8 +16,6 @@ */ struct lb_memory *get_lb_mem(void); -extern struct cmos_option_table option_table; - /* defined by mainboard.c if the mainboard requires extra resources */ int add_mainboard_resources(struct lb_memory *mem); int add_northbridge_resources(struct lb_memory *mem); Modified: trunk/src/include/cbfs.h ============================================================================== --- trunk/src/include/cbfs.h Tue Jan 18 13:14:08 2011 (r6267) +++ trunk/src/include/cbfs.h Tue Jan 18 14:56:36 2011 (r6268) @@ -71,6 +71,9 @@ #define CBFS_TYPE_VSA 0x51 #define CBFS_TYPE_MBI 0x52 #define CBFS_TYPE_MICROCODE 0x53 +#define CBFS_COMPONENT_CMOS_DEFAULT 0xaa +#define CBFS_COMPONENT_CMOS_LAYOUT 0x01aa + /** this is the master cbfs header - it need to be located somewhere in the bootblock. Where it Modified: trunk/src/pc80/mc146818rtc.c ============================================================================== --- trunk/src/pc80/mc146818rtc.c Tue Jan 18 13:14:08 2011 (r6267) +++ trunk/src/pc80/mc146818rtc.c Tue Jan 18 14:56:36 2011 (r6268) @@ -4,6 +4,7 @@ #include <string.h> #if CONFIG_USE_OPTION_TABLE #include "option_table.h" +#include <cbfs.h> #endif /* control registers - Moto names @@ -217,7 +218,6 @@ int get_option(void *dest, const char *name) { - extern struct cmos_option_table option_table; struct cmos_option_table *ct; struct cmos_entries *ce; size_t namelen; @@ -227,7 +227,7 @@ namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); /* find the requested entry record */ - ct=&option_table; + ct=cbfs_find_file("cmos_layout.bin", CMOS_COMPONENT_CMOS_LAYOUT); ce=(struct cmos_entries*)((unsigned char *)ct + ct->header_length); for(;ce->tag==LB_TAG_OPTION; ce=(struct cmos_entries*)((unsigned char *)ce + ce->size)) { Modified: trunk/src/pc80/mc146818rtc_early.c ============================================================================== --- trunk/src/pc80/mc146818rtc_early.c Tue Jan 18 13:14:08 2011 (r6267) +++ trunk/src/pc80/mc146818rtc_early.c Tue Jan 18 14:56:36 2011 (r6268) @@ -65,7 +65,7 @@ if (cmos_error() || !cmos_chksum_valid()) { #if CONFIG_USE_CMOS_RECOVERY - char *cmos_default = cbfs_find_file("cmos.default", 0xaa); + char *cmos_default = cbfs_find_file("cmos.default", CBFS_COMPONENT_CMOS_DEFAULT); if (cmos_default) { printk_warning("WARNING - CMOS CORRUPTED. RESTORING DEFAULTS.\n"); /* First 14 bytes are reserved for Modified: trunk/util/cbfstool/cbfs.h ============================================================================== --- trunk/util/cbfstool/cbfs.h Tue Jan 18 13:14:08 2011 (r6267) +++ trunk/util/cbfstool/cbfs.h Tue Jan 18 14:56:36 2011 (r6268) @@ -77,6 +77,7 @@ #define CBFS_COMPONENT_MBI 0x52 #define CBFS_COMPONENT_MICROCODE 0x53 #define CBFS_COMPONENT_CMOS_DEFAULT 0xaa +#define CBFS_COMPONENT_CMOS_LAYOUT 0x01aa /* The deleted type is chosen to be a value * that can be written in a FLASH from all other Modified: trunk/util/options/build_opt_tbl.c ============================================================================== --- trunk/util/options/build_opt_tbl.c Tue Jan 18 13:14:08 2011 (r6267) +++ trunk/util/options/build_opt_tbl.c Tue Jan 18 14:56:36 2011 (r6268) @@ -33,7 +33,7 @@ #define INPUT_LINE_MAX 256 #define MAX_VALUE_BYTE_LENGTH 64 -#define TMPFILE_LEN 256 +#define TMPFILE_LEN 25600 #define TMPFILE_TEMPLATE "/build_opt_tbl_XXXXXX" static unsigned char cmos_table[4096]; @@ -142,8 +142,9 @@ printf(" [--option filename]\n"); printf(" [--header filename]\n\n"); printf("--config = Build the definitions table from the given file.\n"); + printf("--binary = Output a binary file with the definitions.\n"); printf("--option = Output a C source file with the definitions.\n"); - printf("--header = Ouput a C header file with the definitions.\n"); + printf("--header = Output a C header file with the definitions.\n"); exit(1); } @@ -253,6 +254,7 @@ { int i; char *config=0; + char *binary=0; char *option=0; char *header=0; FILE *fp; @@ -288,6 +290,12 @@ } config=argv[++i]; break; + case 'b': /* Emit a binary file */ + if(strcmp(&argv[i][2],"binary")) { + display_usage(argv[0]); + } + binary=argv[++i]; + break; case 'o': /* use a cmos definitions table file */ if(strcmp(&argv[i][2],"option")) { display_usage(argv[0]); @@ -519,8 +527,7 @@ /* See if we want to output a C source file */ if(option) { int err=0; - strncpy(tempfilename, dirname(strdup(option)), TMPFILE_LEN); - strncat(tempfilename, TMPFILE_TEMPLATE, TMPFILE_LEN); + snprintf(tempfilename, TMPFILE_LEN, "%s%s", dirname(strdup(option)), TMPFILE_TEMPLATE); tempfile = mkstemp(tempfilename); if(tempfile == -1) { perror("Error - Could not create temporary file"); @@ -566,13 +573,46 @@ } } + /* See if we also want to output a binary file */ + if(binary) { + int err=0; + snprintf(tempfilename, TMPFILE_LEN, "%s%s", dirname(strdup(binary)), TMPFILE_TEMPLATE); + tempfile = mkstemp(tempfilename); + if(tempfile == -1) { + perror("Error - Could not create temporary file"); + exit(1); + } + + if((fp=fdopen(tempfile,"wb"))==NULL){ + perror("Error - Could not open temporary file"); + unlink(tempfilename); + exit(1); + } + + /* write the array values */ + if(!fwrite(cmos_table, (int)(ct->size-1), 1, fp)) { + perror("Error - Could not write image file"); + fclose(fp); + unlink(tempfilename); + exit(1); + } + + fclose(fp); + UNLINK_IF_NECESSARY(binary); + if (rename(tempfilename, binary)) { + fprintf(stderr, "Error - Could not write %s: ", binary); + perror(NULL); + unlink(tempfilename); + exit(1); + } + } + /* See if we also want to output a C header file */ if (header) { struct cmos_option_table *hdr; struct lb_record *ptr, *end; - strncpy(tempfilename, dirname(strdup(header)), TMPFILE_LEN); - strncat(tempfilename, TMPFILE_TEMPLATE, TMPFILE_LEN); + snprintf(tempfilename, TMPFILE_LEN, "%s%s", dirname(strdup(header)), TMPFILE_TEMPLATE); tempfile = mkstemp(tempfilename); if(tempfile == -1) { perror("Error - Could not create temporary file");

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coreboot January 2011