coreboot January 2011

coreboot@coreboot.org

65 participants
299 discussions

Re: [coreboot] [PATCH] Geode GX2 Kconfig framebuffer choice
by Nils 19 Jan '11

19 Jan '11

>> >But only on the condition that you send a followup patch to change >> >this option into a choice in the user interface. Please see e.g. how >> >src/southbridge/via/k8t890/Kconfig implements this. Thanks! > > > >Is the attached patch what you had in mind? > >Yup, thanks! r6275 Thanks for the review and committing. Nils.

1 0

[MSRTOOL] [PATCH] Add Geode GX2 memmory desriptor registers.
by Nils 19 Jan '11

19 Jan '11

Add Geode GX2 memmory descriptors. Add a simple README file. Signed-off-by: Nils Jacobs <njacobs8(a)hetnet.nl> Thanks, Nils.

2 2

Re: [coreboot] Jetw. J8F9 support
by Cristian Craciunescu 19 Jan '11

19 Jan '11

Patch bellow: Index: src/superio/fintek/Kconfig =================================================================== --- src/superio/fintek/Kconfig (revision 6237) +++ src/superio/fintek/Kconfig (working copy) @@ -27,3 +27,5 @@ bool config SUPERIO_FINTEK_F71889 bool +config SUPERIO_FINTEK_F81216 + bool Index: src/superio/fintek/Makefile.inc =================================================================== --- src/superio/fintek/Makefile.inc (revision 6237) +++ src/superio/fintek/Makefile.inc (working copy) @@ -22,3 +22,4 @@ subdirs-y += f71863fg subdirs-y += f71872 subdirs-y += f71889 +subdirs-y += f81216 Index: src/superio/fintek/f81216/Makefile.inc =================================================================== --- src/superio/fintek/f81216/Makefile.inc (revision 0) +++ src/superio/fintek/f81216/Makefile.inc (revision 0) @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 Corey Osgood <corey.osgood(a)gmail.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +ramstage-$(CONFIG_SUPERIO_FINTEK_F81216) += superio.c + Index: src/superio/fintek/f81216/superio.c =================================================================== --- src/superio/fintek/f81216/superio.c (revision 0) +++ src/superio/fintek/f81216/superio.c (revision 0) @@ -0,0 +1,116 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Corey Osgood <corey.osgood(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pnp.h> +#include <console/console.h> +#include <stdlib.h> +#include <uart8250.h> +#include "chip.h" +#include "f81216.h" + +static void pnp_enter_conf_state(device_t dev) +{ + outb(0x77, dev->path.pnp.port); + outb(0x77, dev->path.pnp.port); +} + +static void pnp_exit_conf_state(device_t dev) +{ + outb(0xaa, dev->path.pnp.port); +} + +static void f81216_init(device_t dev) +{ + struct superio_fintek_f81216_config *conf = dev->chip_info; + struct resource *res0; + + if (!dev->enabled) + return; + + switch(dev->path.pnp.device) { + /* TODO: Might potentially need code for HWM or FDC etc. */ + case F81216_SP1: + res0 = find_resource(dev, PNP_IDX_IO0); + init_uart8250(res0->base, &conf->com1); + break; + case F81216_SP2: + res0 = find_resource(dev, PNP_IDX_IO0); + init_uart8250(res0->base, &conf->com2); + break; + case F81216_SP3: + res0 = find_resource(dev, PNP_IDX_IO0); + init_uart8250(res0->base, &conf->com3); + break; + case F81216_SP4: + res0 = find_resource(dev, PNP_IDX_IO0); + init_uart8250(res0->base, &conf->com4); + break; + } +} + +static void f81216_pnp_set_resources(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_set_resources(dev); + pnp_exit_conf_state(dev); +} + +static void f81216_pnp_enable_resources(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_enable_resources(dev); + pnp_exit_conf_state(dev); +} + +static void f81216_pnp_enable(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + (dev->enabled) ? pnp_set_enable(dev, 1) : pnp_set_enable(dev, 0); + pnp_exit_conf_state(dev); +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = f81216_pnp_set_resources, + .enable_resources = f81216_pnp_enable_resources, + .enable = f81216_pnp_enable, + .init = f81216_init, +}; + +static struct pnp_info pnp_dev_info[] = { + /* TODO: Some of the 0x07f8 etc. values may not be correct. */ + { &ops, F81216_SP1, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, F81216_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, F81216_SP3, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, F81216_SP4, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, +}; + +static void enable_dev(device_t dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_fintek_f81216_ops = { + CHIP_NAME("Fintek F81216 Super I/O") + .enable_dev = enable_dev +}; Index: src/superio/fintek/f81216/chip.h =================================================================== --- src/superio/fintek/f81216/chip.h (revision 0) +++ src/superio/fintek/f81216/chip.h (revision 0) @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Corey Osgood <corey(a)slightlyhackish.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_FINTEK_F81216_CHIP_H +#define SUPERIO_FINTEK_F81216_CHIP_H + +#include <device/device.h> +#include <uart8250.h> + +/* This chip doesn't have keyboard and mouse support. */ + +extern struct chip_operations superio_fintek_f81216_ops; + +struct superio_fintek_f81216_config { + struct uart8250 com1, com2, com3, com4; +}; + +#endif Index: src/superio/fintek/f81216/early_serial.c =================================================================== --- src/superio/fintek/f81216/early_serial.c (revision 0) +++ src/superio/fintek/f81216/early_serial.c (revision 0) @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Corey Osgood <corey(a)slightlyhackish.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Pre-RAM driver for the Fintek F71805F/FG Super I/O chip. */ + +#include <arch/romcc_io.h> +#include "f81216.h" + +static void pnp_enter_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(0x77, port); + outb(0x77, port); +} + +/* + * Acording to documentation of Fintek device + * we must set the clock option first(we set 48Mhz) + */ +static void pnp_set_clock(device_t dev) +{ + u16 port = dev >> 8; + outb(0x25, port); + outb(0x01, port + 1); +} + +static void pnp_exit_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(0xaa, port); +} + +static void f81216_enable_serial(device_t dev, u16 iobase) +{ + pnp_enter_conf_state(dev); + pnp_set_clock(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_conf_state(dev); +} Index: src/superio/fintek/f81216/f81216.h =================================================================== --- src/superio/fintek/f81216/f81216.h (revision 0) +++ src/superio/fintek/f81216/f81216.h (revision 0) @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Corey Osgood <corey(a)slightlyhackish.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_FINTEK_F81216_H +#define SUPERIO_FINTEK_F81216_H + +/* + * Datasheet: + * - Name: F71805F/FG Super H/W Monitor + LPC IO + * - URL: http://www.fintek.com.tw/eng/products.asp?BID=1&SID=17 + * - PDF: http://www.fintek.com.tw/files/productfiles/F71805F_V025.pdf + * - Revision: V0.25P + */ + +/* Logical Device Numbers (LDN). */ +#define F81216_SP1 0x00 /* UART1 */ +#define F81216_SP2 0x01 /* UART2 */ +#define F81216_SP3 0x02 /* UART3 */ +#define F81216_SP4 0x03 /* UART4 */ + +#endif Index: src/mainboard/jetway/Kconfig =================================================================== --- src/mainboard/jetway/Kconfig (revision 6237) +++ src/mainboard/jetway/Kconfig (working copy) @@ -7,11 +7,14 @@ bool "J7F24" config BOARD_JETWAY_PA78VM5 bool "PA78VM5 (Fam10)" +config BOARD_JETWAY_J8 + bool "J8 Nano-ITX" endchoice source "src/mainboard/jetway/j7f24/Kconfig" source "src/mainboard/jetway/pa78vm5/Kconfig" +source "src/mainboard/jetway/j8/Kconfig" config MAINBOARD_VENDOR string Index: src/mainboard/jetway/j8/Kconfig =================================================================== --- src/mainboard/jetway/j8/Kconfig (revision 0) +++ src/mainboard/jetway/j8/Kconfig (revision 0) @@ -0,0 +1,28 @@ +if BOARD_JETWAY_J8 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_AMD_LX + select NORTHBRIDGE_AMD_LX + select SOUTHBRIDGE_AMD_CS5536 +# select SUPERIO_WINBOND_W83627HF + select SUPERIO_FINTEK_F81216 + select HAVE_PIRQ_TABLE + select PIRQ_ROUTE + select BOARD_ROMSIZE_KB_256 + select POWER_BUTTON_FORCE_ENABLE + +config MAINBOARD_DIR + string + default jetway/j8 + +config MAINBOARD_PART_NUMBER + string + default "PCISA-LX-800-R10" + +config IRQ_SLOT_COUNT + int + default 9 + +endif # BOARD_JETWAY_J8 Index: src/mainboard/jetway/j8/devicetree.cb =================================================================== --- src/mainboard/jetway/j8/devicetree.cb (revision 0) +++ src/mainboard/jetway/j8/devicetree.cb (revision 0) @@ -0,0 +1,58 @@ +chip northbridge/amd/lx + device pci_domain 0 on + device pci 1.0 on end # Northbridge + device pci 1.1 on end # Graphics + chip southbridge/amd/cs5536 + # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK + # SIRQ Mode = Active(Quiet) mode. Save power.... + # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK + register "lpc_serirq_enable" = "0x000011fa" + register "lpc_serirq_polarity" = "0x0000EF05" + register "lpc_serirq_mode" = "1" + register "enable_gpio_int_route" = "0x0D0C0700" + register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash + register "com1_enable" = "0" + register "com1_address" = "0x3F8" + register "com1_irq" = "4" + register "com2_enable" = "0" + register "com2_address" = "0x2F8" + register "com2_irq" = "3" + register "enable_USBP4_device" = "1" # 0: host, 1:device + register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) + register "unwanted_vpci[0]" = "0" # End of list has a zero + device pci d.0 on end # Ethernet 1 + device pci f.0 on # ISA Bridge + chip superio/fintek/f81216 + device pnp 4e.0 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 3 + end + device pnp 4e.1 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 4 + end + device pnp 4e.2 on # Com3 + io 0x60 = 0x3e8 + irq 0x70 = 5 + end + device pnp 4e.3 on # Com4 + io 0x60 = 0x2e8 + irq 0x70 = 7 + end + end + end + + device pci f.2 on end # IDE Controller + device pci f.3 on end # Audio + device pci f.4 on end # OHCI + device pci f.5 on end # EHCI + end + end + # APIC cluster is late CPU init. + device lapic_cluster 0 on + chip cpu/amd/model_lx + device lapic 0 on end + end + end +end + Index: src/mainboard/jetway/j8/romstage.c =================================================================== --- src/mainboard/jetway/j8/romstage.c (revision 0) +++ src/mainboard/jetway/j8/romstage.c (revision 0) @@ -0,0 +1,98 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <stdlib.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/hlt.h> +#include <console/console.h> +#include "cpu/x86/bist.h" +#include "cpu/x86/msr.h" +#include <cpu/amd/lxdef.h> +#include <cpu/amd/geode_post_code.h> +#include "southbridge/amd/cs5536/cs5536.h" +#include <spd.h> +#include "southbridge/amd/cs5536/early_smbus.c" +#include "southbridge/amd/cs5536/early_setup.c" +#include "superio/fintek/f81216/early_serial.c" +#include "arch/x86/include/arch/llshell.h" + +#define SERIAL_DEV PNP_DEV(0x4e, F81216_SP1) + +static inline int spd_read_byte(unsigned int device, unsigned int address) +{ + return smbus_read_byte(device, address); +} + +#define ManualConf 1 /* Do automatic strapped PLL config */ +#define PLLMSRhi 0x0000059C /* CPU and GLIU mult/div 500/400*/ +////#define PLLMSRhi 0x0000049C /* CPU and GLIU mult/div 500/333*/ +//#define PLLMSRhi 0x0000049e +//#define PLLMSRhi 0x0000039C /* CPU and GLIU mult/div 500/266*/ +//0x0000059C 0000 0000 0000 0000 0000 |0101 1|0|01 110|0 +/* Hold Count - how long we will sit in reset */ +#define PLLMSRlo 0x00DE6000 + +#include "northbridge/amd/lx/raminit.h" +#include "northbridge/amd/lx/pll_reset.c" +#include "northbridge/amd/lx/raminit.c" +#include "lib/generic_sdram.c" +#include "cpu/amd/model_lx/cpureginit.c" +#include "cpu/amd/model_lx/syspreinit.c" +#include "cpu/amd/model_lx/msrinit.c" + +void main(unsigned long bist) +{ + post_code(0x01); + + static const struct mem_controller memctrl[] = { + {.channel0 = {DIMM0, DIMM1}} + }; + + SystemPreInit(); + msr_init(); + + cs5536_early_setup(); + + /* Note: must do this AFTER the early_setup! It is counting on some + * early MSR setup for CS5536. + */ + // Cristi + // Need to initialize the Fintek superio for serials + // + f81216_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + uart_init(); + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + pll_reset(ManualConf); + + cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); + + sdram_initialize(1, memctrl); + llshell(); + + /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */ + return; +} Index: src/mainboard/jetway/j8/irq_tables.c =================================================================== --- src/mainboard/jetway/j8/irq_tables.c (revision 0) +++ src/mainboard/jetway/j8/irq_tables.c (revision 0) @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/pirq_routing.h> +#include <console/console.h> +#include <arch/io.h> +#include <arch/pirq_routing.h> +#include "southbridge/amd/cs5536/cs5536.h" + +/* Platform IRQs */ +#define PIRQA 11 +#define PIRQB 5 +#define PIRQC 10 +#define PIRQD 10 + +/* Map */ +#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */ +#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */ +#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */ +#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */ + +/* Link */ +#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */ +#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */ +#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */ +#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */ + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ + 0x00, /* Where the interrupt router lies (bus) */ + (0x0f<<3)|0x0, /* Where the interrupt router lies (dev) */ + 0xc00, /* IRQs devoted exclusively to PCI usage */ + 0x100b, /* Vendor */ + 0x2b, /* Device */ + 0, /* Miniport data */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0xe, /* u8 checksum. This has to be set to some + value that would give 0 after the sum of all + bytes for this structure (including checksum) */ + { + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00,(0x01<<3)|0x0, {{0x01, 0x0400}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, + {0x00,(0x0f<<3)|0x0, {{0x00, 0x0000}, {0x02, 0x0400}, {0x00, 0x0000}, {0x04, 0x00400}}, 0x0, 0x0}, + {0x00,(0x13<<3)|0x0, {{0x01, 0x0400}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, + {0x00,(0x12<<3)|0x0, {{0x03, 0x0400}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, + {0x00,(0x11<<3)|0x0, {{0x01, 0x0400}, {0x02, 0x0800}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, + {0x00,(0x0a<<3)|0x0, {{0x01, 0x0400}, {0x02, 0x0800}, {0x03, 0x0400}, {0x04, 0x00800}}, 0x1, 0x0}, + {0x00,(0x0b<<3)|0x0, {{0x02, 0x0800}, {0x03, 0x0400}, {0x04, 0x0800}, {0x01, 0x00400}}, 0x2, 0x0}, + {0x00,(0x0c<<3)|0x0, {{0x03, 0x0400}, {0x04, 0x0800}, {0x01, 0x0400}, {0x02, 0x00800}}, 0x3, 0x0}, + {0x00,(0x0d<<3)|0x0, {{0x04, 0x0800}, {0x01, 0x0400}, {0x02, 0x0800}, {0x03, 0x00400}}, 0x4, 0x0}, + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} Index: src/mainboard/jetway/j8/chip.h =================================================================== --- src/mainboard/jetway/j8/chip.h (revision 0) +++ src/mainboard/jetway/j8/chip.h (revision 0) @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; Index: src/mainboard/jetway/j8/mainboard.c =================================================================== --- src/mainboard/jetway/j8/mainboard.c (revision 0) +++ src/mainboard/jetway/j8/mainboard.c (revision 0) @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> + +struct chip_operations mainboard_ops = { + CHIP_NAME("Jetway LX-800 Mainboard") +}; Index: src/northbridge/amd/lx/northbridge.c =================================================================== --- src/northbridge/amd/lx/northbridge.c (revision 6237) +++ src/northbridge/amd/lx/northbridge.c (working copy) @@ -412,11 +412,11 @@ cpubug(); chipsetinit(); - // print_conf(); + print_conf(); do_vsmbios(); // do the magic stuff here, so prepare your tambourine ;) - // print_conf(); + print_conf(); graphics_init(); pci_set_method(dev); On Tue, Jan 18, 2011 at 10:28 AM, Cristian Craciunescu <ccristian(a)gmail.com>wrote: > I'm sure the problem is coming from PIRQ map; needs some fine tuning. The > board has four serials and all of them are connected the 81216DG super IO > chip so I'm using the first serial port, the onchip uarts are disabled. > There is an additional hwmon chip(f71858) which I did not touched > yet. Attached the patch with j8 dir in mainboard and f81216DG superio > added. > > > > > Regards, > Cristian > On Tue, Jan 18, 2011 at 10:01 AM, Cristian Craciunescu > <ccristian(a)gmail.com>wrote <ccristian(a)gmail.com%3Ewrote>: > > > Cristian Craciunescu wrote: > > > I've compiled suport for j8f9 board from jetw. using as template other > LX > > > mainboard. The system is booting with coreboot/seabios however the > serial > > > does not seam to work in kernel. GRUB bootloader works ok over serial > but > > as > > > soon as the linux kernel finish booting it does not respond over serial > > but > > > it can send messages to serial. Although the IRQs are detected > correctly > > > when the serial has input I can not see any irq messages incrementing > in > > > /proc/interrupts. Any hint? > > > > Something is wrong with the interrupt setup in coreboot if they are > > not being delivered to the kernel. > > > > Are you using the internal UART in CS5536 or do you have a superio? > > Which board did you use as template? > > Can you post a patch with your code so far? > > > > > > //Peter > > >

2 2

[commit] r6253 - in trunk: src/arch/x86 src/mainboard/getac/p470 src/mainboard/kontron/986lcd-m src/mainboard/roda/rk886ex src/pc80 util/cbfstool
by repository service 19 Jan '11

19 Jan '11

Author: oxygene Date: Fri Jan 14 08:40:24 2011 New Revision: 6253 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6253 Log: Allow coreboot to initialize CMOS if checksum is invalid. If a file "cmos.default", type "cmos default"(0xaa) is in CBFS, a wrong checksum leads to coreboot rewriting the first 128 bytes (except for clock data) with the data in cmos.default, then reboots the system so every component of coreboot works with the same set of values. Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Acked-by: Stefan Reinauer <stepan(a)coreboot.org> Modified: trunk/src/arch/x86/Kconfig trunk/src/mainboard/getac/p470/cmos.layout trunk/src/mainboard/kontron/986lcd-m/cmos.layout trunk/src/mainboard/roda/rk886ex/cmos.layout trunk/src/pc80/Makefile.inc trunk/src/pc80/mc146818rtc_early.c trunk/util/cbfstool/cbfs.h trunk/util/cbfstool/common.c Modified: trunk/src/arch/x86/Kconfig ============================================================================== --- trunk/src/arch/x86/Kconfig Thu Jan 13 12:40:38 2011 (r6252) +++ trunk/src/arch/x86/Kconfig Fri Jan 14 08:40:24 2011 (r6253) @@ -91,6 +91,13 @@ config BOOTBLOCK_NORTHBRIDGE_INIT string +config HAVE_CMOS_DEFAULT + def_bool n + +config CMOS_DEFAULT_FILE + string + depends on HAVE_CMOS_DEFAULT + config BOOTBLOCK_SOUTHBRIDGE_INIT string Modified: trunk/src/mainboard/getac/p470/cmos.layout ============================================================================== --- trunk/src/mainboard/getac/p470/cmos.layout Thu Jan 13 12:40:38 2011 (r6252) +++ trunk/src/mainboard/getac/p470/cmos.layout Fri Jan 14 08:40:24 2011 (r6253) @@ -92,7 +92,8 @@ # coreboot config options: bootloader 416 512 s 0 boot_devices 928 8 h 0 boot_default -#936 48 r 0 unused +936 1 e 8 cmos_defaults_loaded +#937 47 r 0 unused # coreboot config options: check sums 984 16 h 0 check_sum @@ -136,6 +137,8 @@ 7 0 Disable 7 1 Enable 7 2 Keep +8 0 No +8 1 Yes # ----------------------------------------------------------------- checksums Modified: trunk/src/mainboard/kontron/986lcd-m/cmos.layout ============================================================================== --- trunk/src/mainboard/kontron/986lcd-m/cmos.layout Thu Jan 13 12:40:38 2011 (r6252) +++ trunk/src/mainboard/kontron/986lcd-m/cmos.layout Fri Jan 14 08:40:24 2011 (r6253) @@ -90,7 +90,8 @@ # coreboot config options: bootloader 416 512 s 0 boot_devices 928 8 h 0 boot_default -#936 12 r 0 unused +936 1 e 11 cmos_defaults_loaded +#937 11 r 0 unused # coreboot config options: mainboard specific options 948 2 e 8 cpufan_cruise_control @@ -187,6 +188,8 @@ #10 13 69/156 #10 14 72/161 #10 15 75/167 +11 0 No +11 1 Yes # ----------------------------------------------------------------- checksums Modified: trunk/src/mainboard/roda/rk886ex/cmos.layout ============================================================================== --- trunk/src/mainboard/roda/rk886ex/cmos.layout Thu Jan 13 12:40:38 2011 (r6252) +++ trunk/src/mainboard/roda/rk886ex/cmos.layout Fri Jan 14 08:40:24 2011 (r6253) @@ -92,7 +92,8 @@ # coreboot config options: bootloader 416 512 s 0 boot_devices 928 8 h 0 boot_default -#936 48 r 0 unused +936 1 e 8 cmos_defaults_loaded +#937 47 r 0 unused # coreboot config options: check sums 984 16 h 0 check_sum @@ -136,6 +137,8 @@ 7 0 Disable 7 1 Enable 7 2 Keep +8 0 No +8 1 Yes # ----------------------------------------------------------------- checksums Modified: trunk/src/pc80/Makefile.inc ============================================================================== --- trunk/src/pc80/Makefile.inc Thu Jan 13 12:40:38 2011 (r6252) +++ trunk/src/pc80/Makefile.inc Fri Jan 14 08:40:24 2011 (r6253) @@ -10,3 +10,8 @@ $(obj)/pc80/mc146818rtc.ramstage.o : $(OPTION_TABLE_H) $(obj)/pc80/mc146818rtc_early.romstage.o : $(OPTION_TABLE_H) + +cbfs-files-$(CONFIG_HAVE_CMOS_DEFAULT) += $(CONFIG_CMOS_DEFAULT_FILE) +$(CONFIG_CMOS_DEFAULT_FILE)-name := cmos.default +$(CONFIG_CMOS_DEFAULT_FILE)-type := 0xaa + Modified: trunk/src/pc80/mc146818rtc_early.c ============================================================================== --- trunk/src/pc80/mc146818rtc_early.c Thu Jan 13 12:40:38 2011 (r6252) +++ trunk/src/pc80/mc146818rtc_early.c Fri Jan 14 08:40:24 2011 (r6253) @@ -1,5 +1,6 @@ #include <pc80/mc146818rtc.h> #include <fallback.h> +#include <cbfs.h> #if CONFIG_USE_OPTION_TABLE #include "option_table.h" #endif @@ -11,11 +12,18 @@ #error "CONFIG_MAX_REBOOT_CNT too high" #endif +#include <console/loglevel.h> + +int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3))); +#define printk_warning(fmt, arg...) do_printk(BIOS_WARNING ,fmt, ##arg) +#define printk_debug(fmt, arg...) do_printk(BIOS_DEBUG ,fmt, ##arg) + static int cmos_error(void) { unsigned char reg_d; /* See if the cmos error condition has been flagged */ reg_d = cmos_read(RTC_REG_D); + printk_debug("CMOS_REG_D(VRT): %x\n", reg_d & RTC_VRT); return (reg_d & RTC_VRT) == 0; } @@ -35,6 +43,7 @@ old_sum = cmos_read(LB_CKS_LOC) << 8; old_sum |= cmos_read(LB_CKS_LOC+1); + printk_debug("CMOS checksum: old = %lx, new=%lx\n", old_sum, sum); return sum == old_sum; #else return 0; @@ -51,9 +60,26 @@ static inline int do_normal_boot(void) { + char *cmos_default = cbfs_find_file("cmos.default", 0xaa); unsigned char byte; + int i; if (cmos_error() || !cmos_chksum_valid()) { + if (cmos_default) { + printk_warning("WARNING - CMOS CORRUPTED. RESTORING DEFAULTS.\n"); + /* First 14 bytes are reserved for + RTC and ignored by nvramtool, too. + Only 128 bytes: 128+ requires cmos configuration and + contains only suspend-to-ram data, which isn't part + of the recovery procedure. */ + for (i = 14; i < 128; i++) { + cmos_write(cmos_default[i], i); + } + /* Now reboot to run with default cmos. */ + outb(0x06, 0xcf9); + for (;;) asm("hlt"); /* Wait for reset! */ + } + /* There are no impossible values, no checksums so just * trust whatever value we have in the the cmos, * but clear the fallback bit. Modified: trunk/util/cbfstool/cbfs.h ============================================================================== --- trunk/util/cbfstool/cbfs.h Thu Jan 13 12:40:38 2011 (r6252) +++ trunk/util/cbfstool/cbfs.h Fri Jan 14 08:40:24 2011 (r6253) @@ -76,6 +76,7 @@ #define CBFS_COMPONENT_VSA 0x51 #define CBFS_COMPONENT_MBI 0x52 #define CBFS_COMPONENT_MICROCODE 0x53 +#define CBFS_COMPONENT_CMOS_DEFAULT 0xaa /* The deleted type is chosen to be a value * that can be written in a FLASH from all other Modified: trunk/util/cbfstool/common.c ============================================================================== --- trunk/util/cbfstool/common.c Thu Jan 13 12:40:38 2011 (r6252) +++ trunk/util/cbfstool/common.c Fri Jan 14 08:40:24 2011 (r6253) @@ -145,6 +145,7 @@ {CBFS_COMPONENT_VSA, "vsa"}, {CBFS_COMPONENT_MBI, "mbi"}, {CBFS_COMPONENT_MICROCODE, "microcode"}, + {CBFS_COMPONENT_CMOS_DEFAULT, "cmos default"}, {CBFS_COMPONENT_DELETED, "deleted"}, {CBFS_COMPONENT_NULL, "null"} };

3 3

[PATCH] Geode GX2 Kconfig framebuffer choice
by Nils 19 Jan '11

19 Jan '11

Add a GX2 Kconfig option to choose the framebuffer size. Signed-off-by: Nils Jacobs <njacobs8(a)hetnet.nl> This patch is buid and boot tested. Hi Peter, You wrote: >> >> +config VIDEO_MB >> + int >> + default 8 >> + depends on NORTHBRIDGE_AMD_GX2 >> + > >Acked-by: Peter Stuge <peter at stuge.se> > >r6211 > >But only on the condition that you send a followup patch to change >this option into a choice in the user interface. Please see e.g. how >src/southbridge/via/k8t890/Kconfig implements this. Thanks! Is the attached patch what you had in mind? Thanks, Nils.

2 1

[commit] r6275 - trunk/src/northbridge/amd/gx2
by repository service 19 Jan '11

19 Jan '11

Author: stuge Date: Wed Jan 19 08:25:26 2011 New Revision: 6275 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6275 Log: Add a GX2 Kconfig option to choose the framebuffer size. Signed-off-by: Nils Jacobs <njacobs8(a)hetnet.nl> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/northbridge/amd/gx2/Kconfig Modified: trunk/src/northbridge/amd/gx2/Kconfig ============================================================================== --- trunk/src/northbridge/amd/gx2/Kconfig Wed Jan 19 07:56:33 2011 (r6274) +++ trunk/src/northbridge/amd/gx2/Kconfig Wed Jan 19 08:25:26 2011 (r6275) @@ -21,9 +21,40 @@ bool select GEODE_VSA +choice + prompt "Framebuffer size" + default GX2_VIDEO_MB_8MB + depends on NORTHBRIDGE_AMD_GX2 && VGA_BRIDGE_SETUP + +config GX2_VIDEO_MB_4MB + bool "4MB" +config GX2_VIDEO_MB_8MB + bool "8MB" +config GX2_VIDEO_MB_16MB + bool "16MB" +config GX2_VIDEO_MB_32MB + bool "32MB" +config GX2_VIDEO_MB_64MB + bool "64MB" +config GX2_VIDEO_MB_128MB + bool "128MB" +config GX2_VIDEO_MB_256MB + bool "256MB" +config GX2_VIDEO_MB_CMOS + bool "Use CMOS option" + +endchoice + config VIDEO_MB int - default 8 + default 4 if GX2_VIDEO_MB_4MB + default 8 if GX2_VIDEO_MB_8MB + default 16 if GX2_VIDEO_MB_16MB + default 32 if GX2_VIDEO_MB_32MB + default 64 if GX2_VIDEO_MB_64MB + default 128 if GX2_VIDEO_MB_128MB + default 256 if GX2_VIDEO_MB_256MB + default -1 if GX2_VIDEO_MB_CMOS depends on NORTHBRIDGE_AMD_GX2 # The GX2_PROCESSOR_MHZ options let you chose the correct GX2 processor

1 0

PATCH for NOKIA IP530
by Marc Bertens 19 Jan '11

19 Jan '11

Hi all, Acked-by: Marc Bertens <mbertens.xs4all.nl> Tested-by: Marc Bertens <mbertens.xs4all.nl> Here is a new patch for the Nokia IP530, it contains; * Selection of the P3 cup in the Kconfig * In Kconfig the board revision can be selected. * In the devicetree,cb added comments and commented-out some things that where not needed, but for now left them in the file. * New PIRQ table for board revision B, did this by some macros to keep it simple. Marc Bertens

3 4

NULL pointer dereference in search_bus_device()
by Sven Schnelle 19 Jan '11

19 Jan '11

Hi List, during coreboot development i faced the problem that coreboot sometimes hanged after printing the List of PCI devices. It turned out that this is a NULL pointer dereference in search_bus_devices(). Not sure if the following patch is the correct fix, as i don't know that part of the code well. If it is not, please discard the patch and provide a better one :) commit 11a840272dd5f0d0f1a8414163f5404fb028c209 Author: Sven Schnelle <svens(a)stackframe.org> Date: Mon Jan 10 13:53:18 2011 +0100 Fix a NULL pointer dereference in search_bus_devices() Signed-off-by: Sven Schnelle <svens(a)stackframe.org> diff --git a/src/devices/device_util.c b/src/devices/device_util.c index 9081a36..d761cba 100644 --- a/src/devices/device_util.c +++ b/src/devices/device_util.c @@ -583,8 +583,9 @@ void search_bus_resources(struct bus *bus, unsigned long type_mask, if (subbus->link_num == IOINDEX_SUBTRACTIVE_LINK(res->index)) break; - search_bus_resources(subbus, type_mask, type, - search, gp); + if (subbus) + search_bus_resources(subbus, type_mask, type, + search, gp); continue; } search(gp, curdev, res);

5 9

Serial port 2 fix for Epia-Mii
by Snoke 19 Jan '11

19 Jan '11

Serial port 2 won't work on Epia-Mii. Following patch I get it work. Found solution at Linuxbios archive : [LinuxBIOS] EPIA M COM2 problem + possible solution? <http://www.coreboot.org/pipermail/coreboot/2006-February/013603.html>

2 1

Re: [coreboot] sb800 code derived from sb700 implementation
by Bao, Zheng 19 Jan '11

19 Jan '11

I personally like this patch, not because I did. It is easy to use and handle. I am gonna signed-off-by it. If I get support, I will check it in. Zheng Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> ________________________________________ From: coreboot-bounces(a)coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of She, Kerry Sent: Tuesday, January 04, 2011 4:12 PM To: coreboot(a)coreboot.org Subject: [coreboot] sb800 code derived from sb700 implementation Sorry to send again, forget the subject last email I have made a little bit cleanup from the patches originally made by Bao Zheng, This sb800 code is derived from sb700 implementation. Release this patch is NOT to confusing people, but make other patches based on this implementation also works. So this patch don't need to be checked into the tree. Regards, Kerry She < kerry.she(a)amd.com> Tel: 86-10-6280-1415 -- coreboot mailing list: coreboot(a)coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

3 3

← Newer
1
...
15
16
17
18
19
20
21
...
30
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot January 2011