coreboot January 2011

coreboot@coreboot.org

65 participants
299 discussions

Re: [coreboot] abuild error
by Nils 21 Jan '11

21 Jan '11

Op vrijdag 21 januari 2011 01:26:06 schreef u: > > Thanks for investigating. I have always used the same xgcc for coreboot and > seabios. I suppose your newly built xgcc is version 4.5.2. Is there any > chance the coreboot.org build system is not yet using 4.5.2, and that > explains the size difference? For the xgcc versions I have handy, there is > only a small size difference: > >4.4.4 Total size: 74448 Free space: 56624 Percent used: 56.8% (128KiB rom) >4.5.0 Total size: 73840 Free space: 57232 Percent used: 56.3% (128KiB rom) >4.5.1 Total size: 74000 Free space: 57072 Percent used: 56.5% (128KiB rom) > > Thanks, > Scott Thanks for your answer. Which coreboot revision and board did you use? Is that the technologic/ts5300 which gives me trouble? Are these numbers including SeaBios which is nowadays automatically included as payload? Thanks, Nils.

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[PATCH]nvramtool: Look at another place for the CMOS checksum specification
by Georgi, Patrick 20 Jan '11

20 Jan '11

Hi, This patch tells nvramtool about another place where it can find information about the CMOS checksum location and range before it reverts to its own default values. Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> -- Patrick Georgi SINA-Development - High Security secunet Security Networks AG - Mergenthalerallee 77 - 65760 Eschborn, Germany Phone +49 201 54 54-3610 - Fax +49 201 54 54-1325 - www.secunet.com Sitz: Kronprinzenstraße 30, 45128 Essen / Amtsgericht Essen HRB 13615 Vorstand: Dr. Rainer Baumgart (Vors.), Thomas Koelzer, Thomas Pleines Aufsichtsratsvorsitzender: Dr. Karsten Ottenberg

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[PATCH]nvramtool: Support CBFS Images in nvramtool
by Georgi, Patrick 20 Jan '11

20 Jan '11

This is the first patch of this series that actually adds a new feature. Use nvramtool -C to work on CBFS images that contain cmos_layout.bin for CMOS metadata and cmos.default for CMOS defaults. Read/Write/Enum on CMOS data work on cmos.default then. Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> -- Patrick Georgi SINA-Development - High Security secunet Security Networks AG - Mergenthalerallee 77 - 65760 Eschborn, Germany Phone +49 201 54 54-3610 - Fax +49 201 54 54-1325 - www.secunet.com Sitz: Kronprinzenstraße 30, 45128 Essen / Amtsgericht Essen HRB 13615 Vorstand: Dr. Rainer Baumgart (Vors.), Thomas Koelzer, Thomas Pleines Aufsichtsratsvorsitzender: Dr. Karsten Ottenberg

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[PATCH]nvramtool: Support CMOS data from non-CBFS file, too
by Georgi, Patrick 20 Jan '11

20 Jan '11

This patch adds a -D option to tell nvramtool to work on data in a plain CMOS image (as extracted by the nvramtool dump option, for example). Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> -- Patrick Georgi SINA-Development - High Security secunet Security Networks AG - Mergenthalerallee 77 - 65760 Eschborn, Germany Phone +49 201 54 54-3610 - Fax +49 201 54 54-1325 - www.secunet.com Sitz: Kronprinzenstraße 30, 45128 Essen / Amtsgericht Essen HRB 13615 Vorstand: Dr. Rainer Baumgart (Vors.), Thomas Koelzer, Thomas Pleines Aufsichtsratsvorsitzender: Dr. Karsten Ottenberg

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[PATCH]nvramtool: Teach it to work on data in memory
by Georgi, Patrick 20 Jan '11

20 Jan '11

Attached patch allows nvramtool to work on in-memory data. Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> -- Patrick Georgi SINA-Development - High Security secunet Security Networks AG - Mergenthalerallee 77 - 65760 Eschborn, Germany Phone +49 201 54 54-3610 - Fax +49 201 54 54-1325 - www.secunet.com Sitz: Kronprinzenstraße 30, 45128 Essen / Amtsgericht Essen HRB 13615 Vorstand: Dr. Rainer Baumgart (Vors.), Thomas Koelzer, Thomas Pleines Aufsichtsratsvorsitzender: Dr. Karsten Ottenberg

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[PATCH] superiotool IT8720F support
by Christian Ruppert 20 Jan '11

20 Jan '11

Hey guys, attached is a patch to add support for the IT8720F Super I/O to superiotool. There are three NANA bits in the GPIO reset part, the first two of those were unclear to me so I added them as NANA. One with more experience than me could/should take a look at those please but it should be ok to apply it anyway. -- Regards, Christian Ruppert Role: Gentoo Linux developer, Bugzilla administrator and Infrastructure member Fingerprint: EEB1 C341 7C84 B274 6C59 F243 5EAB 0C62 B427 ABC8

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[commit] r6281 - trunk/src/mainboard/amd/bimini_fam10
by repository service 20 Jan '11

20 Jan '11

Author: zbao Date: Thu Jan 20 07:28:25 2011 New Revision: 6281 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6281 Log: Remove the code for debugging. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Acked-by: Zheng Bao <zheng.bao(a)amd.com> Modified: trunk/src/mainboard/amd/bimini_fam10/dsdt.asl Modified: trunk/src/mainboard/amd/bimini_fam10/dsdt.asl ============================================================================== --- trunk/src/mainboard/amd/bimini_fam10/dsdt.asl Thu Jan 20 06:59:22 2011 (r6280) +++ trunk/src/mainboard/amd/bimini_fam10/dsdt.asl Thu Jan 20 07:28:25 2011 (r6281) @@ -27,7 +27,7 @@ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - #include "../../../arch/x86/acpi/debug.asl" /* Include global debug methods if needed */ + /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -842,10 +842,10 @@ * state of any device in the system. */ Method(\_PTS, 1) { - DBGO("\\_PTS\n") - DBGO("From S0 to S") - DBGO(Arg0) - DBGO("\n") + /* DBGO("\\_PTS\n") */ + /* DBGO("From S0 to S") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ /* Don't allow PCIRST# to reset USB */ if (LEqual(Arg0,3)){ @@ -921,10 +921,10 @@ * if non-zero the effective S-state the power supply entered */ Method(\_WAK, 1) { - DBGO("\\_WAK\n") - DBGO("From S") - DBGO(Arg0) - DBGO(" to S0\n") + /* DBGO("\\_WAK\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ /* Re-enable HPET */ Store(1,HPDE)

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build service results for r6279
by repository service 20 Jan '11

20 Jan '11

Dear coreboot readers! This is the automatic build system of coreboot. The developer "zbao" checked in revision 6279 to the coreboot repository. This caused the following changes: Change Log: Move some board specific functions to sb800.h. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Acked-by: Zheng Bao <zheng.bao(a)amd.com> Build Log: Compilation of amd:bimini_fam10 has been fixed If something broke during this checkin please be a pain in zbao's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r6280 - trunk/src/southbridge/amd/sb800
by repository service 20 Jan '11

20 Jan '11

Author: zbao Date: Thu Jan 20 06:59:22 2011 New Revision: 6280 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6280 Log: S3 feanture of SB800. Compiliant with SB700. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Acked-by: Zheng Bao <zheng.bao(a)amd.com> Modified: trunk/src/southbridge/amd/sb800/early_setup.c trunk/src/southbridge/amd/sb800/sb800.h Modified: trunk/src/southbridge/amd/sb800/early_setup.c ============================================================================== --- trunk/src/southbridge/amd/sb800/early_setup.c Thu Jan 20 06:41:11 2011 (r6279) +++ trunk/src/southbridge/amd/sb800/early_setup.c Thu Jan 20 06:59:22 2011 (r6280) @@ -646,4 +646,54 @@ { return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } + +int s3_save_nvram_early(u32 dword, int size, int nvram_pos) { + int i; + printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos); + + for (i = 0; i<size; i++) { + outb(nvram_pos, BIOSRAM_INDEX); + outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA); + nvram_pos++; + } + + return nvram_pos; +} + +int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) { + u32 data = *old_dword; + int i; + for (i = 0; i<size; i++) { + outb(nvram_pos, BIOSRAM_INDEX); + data &= ~(0xff << (i * 8)); + data |= inb(BIOSRAM_DATA) << (i *8); + nvram_pos++; + } + *old_dword = data; + printk(BIOS_DEBUG, "Loading %x of size %d to nvram pos:%d\n", *old_dword, size, + nvram_pos-size); + return nvram_pos; +} + +#if CONFIG_HAVE_ACPI_RESUME == 1 +static int acpi_is_wakeup_early(void) { + u16 tmp; + tmp = inw(ACPI_PM1_CNT_BLK); + printk(BIOS_DEBUG, "IN TEST WAKEUP %x\n", tmp); + return (((tmp & (7 << 10)) >> 10) == 3); +} +#endif + +struct cbmem_entry *get_cbmem_toc(void) { + uint32_t xdata = 0; + int xnvram_pos = 0xfc, xi; + for (xi = 0; xi<4; xi++) { + outb(xnvram_pos, BIOSRAM_INDEX); + xdata &= ~(0xff << (xi * 8)); + xdata |= inb(BIOSRAM_DATA) << (xi *8); + xnvram_pos++; + } + return (struct cbmem_entry *) xdata; +} + #endif Modified: trunk/src/southbridge/amd/sb800/sb800.h ============================================================================== --- trunk/src/southbridge/amd/sb800/sb800.h Thu Jan 20 06:41:11 2011 (r6279) +++ trunk/src/southbridge/amd/sb800/sb800.h Thu Jan 20 06:59:22 2011 (r6280) @@ -24,6 +24,8 @@ #include "chip.h" /* Power management index/data registers */ +#define BIOSRAM_INDEX 0xcd4 +#define BIOSRAM_DATA 0xcd5 #define PM_INDEX 0xcd6 #define PM_DATA 0xcd7 #define PM2_INDEX 0xcd0 @@ -47,6 +49,8 @@ #define REV_SB800_A11 0x11 #define REV_SB800_A12 0x12 +void sb800_enable(device_t dev); + #ifdef __PRE_RAM__ void sb800_lpc_port80(void); void sb800_pci_port80(void); @@ -55,7 +59,9 @@ /* void sb800_setup_sata_phys(struct device *dev); */ #endif -void sb800_enable(device_t dev); +int s3_save_nvram_early(u32 dword, int size, int nvram_pos); +int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); + void sb800_enable_usbdebug(unsigned int port); #endif /* SB800_H */

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build service results for r6278
by repository service 20 Jan '11

20 Jan '11

Dear coreboot readers! This is the automatic build system of coreboot. The developer "zbao" checked in revision 6278 to the coreboot repository. This caused the following changes: Change Log: Features of Bimini board: RS785 SB800 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Acked-by: Stefan Reinauer <stepan(a)coreboot.org> Build Log: Compilation of amd:bimini_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6278&device=bimini_fam10&v… If something broke during this checkin please be a pain in zbao's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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coreboot January 2011